cs4280.c revision 1.7.2.5
1 /* $NetBSD: cs4280.c,v 1.7.2.5 2001/01/18 09:23:24 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * 44 */ 45 46 /* 47 * TODO 48 * Joystick support 49 */ 50 51 #if defined(CS4280_DEBUG) 52 #define DPRINTF(x) if (cs4280debug) printf x 53 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 54 int cs4280debug = 0; 55 #else 56 #define DPRINTF(x) 57 #define DPRINTFN(n,x) 58 #endif 59 60 #include "midi.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/fcntl.h> 66 #include <sys/malloc.h> 67 #include <sys/device.h> 68 #include <sys/types.h> 69 #include <sys/systm.h> 70 71 #include <dev/pci/pcidevs.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/cs4280reg.h> 74 #include <dev/pci/cs4280_image.h> 75 76 #include <sys/audioio.h> 77 #include <dev/audio_if.h> 78 #include <dev/midi_if.h> 79 #include <dev/mulaw.h> 80 #include <dev/auconv.h> 81 82 #include <dev/ic/ac97reg.h> 83 #include <dev/ic/ac97var.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define CSCC_PCI_BA0 0x10 89 #define CSCC_PCI_BA1 0x14 90 91 struct cs4280_dma { 92 bus_dmamap_t map; 93 caddr_t addr; /* real dma buffer */ 94 caddr_t dum; /* dummy buffer for audio driver */ 95 bus_dma_segment_t segs[1]; 96 int nsegs; 97 size_t size; 98 struct cs4280_dma *next; 99 }; 100 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 101 #define BUFADDR(p) ((void *)((p)->dum)) 102 #define KERNADDR(p) ((void *)((p)->addr)) 103 104 /* 105 * Software state 106 */ 107 struct cs4280_softc { 108 struct device sc_dev; 109 110 pci_intr_handle_t * sc_ih; 111 112 /* I/O (BA0) */ 113 bus_space_tag_t ba0t; 114 bus_space_handle_t ba0h; 115 116 /* BA1 */ 117 bus_space_tag_t ba1t; 118 bus_space_handle_t ba1h; 119 120 /* DMA */ 121 bus_dma_tag_t sc_dmatag; 122 struct cs4280_dma *sc_dmas; 123 124 void (*sc_pintr)(void *); /* dma completion intr handler */ 125 void *sc_parg; /* arg for sc_intr() */ 126 char *sc_ps, *sc_pe, *sc_pn; 127 int sc_pcount; 128 int sc_pi; 129 struct cs4280_dma *sc_pdma; 130 char *sc_pbuf; 131 #ifdef DIAGNOSTIC 132 char sc_prun; 133 #endif 134 135 void (*sc_rintr)(void *); /* dma completion intr handler */ 136 void *sc_rarg; /* arg for sc_intr() */ 137 char *sc_rs, *sc_re, *sc_rn; 138 int sc_rcount; 139 int sc_ri; 140 struct cs4280_dma *sc_rdma; 141 char *sc_rbuf; 142 int sc_rparam; /* record format */ 143 #ifdef DIAGNOSTIC 144 char sc_rrun; 145 #endif 146 147 #if NMIDI > 0 148 void (*sc_iintr)(void *, int); /* midi input ready handler */ 149 void (*sc_ointr)(void *); /* midi output ready handler */ 150 void *sc_arg; 151 #endif 152 153 u_int32_t pctl; 154 u_int32_t cctl; 155 156 struct ac97_codec_if *codec_if; 157 struct ac97_host_if host_if; 158 159 char sc_suspend; 160 void *sc_powerhook; /* Power Hook */ 161 }; 162 163 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 164 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 165 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 166 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 167 168 int cs4280_match __P((struct device *, struct cfdata *, void *)); 169 void cs4280_attach __P((struct device *, struct device *, void *)); 170 int cs4280_intr __P((void *)); 171 void cs4280_reset __P((void *)); 172 int cs4280_download_image __P((struct cs4280_softc *)); 173 174 int cs4280_download(struct cs4280_softc *, u_int32_t *, u_int32_t, u_int32_t); 175 int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 176 struct cs4280_dma *)); 177 int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 178 179 #ifdef CS4280_DEBUG 180 int cs4280_check_images __P((struct cs4280_softc *)); 181 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 182 u_int32_t); 183 #endif 184 185 struct cfattach clcs_ca = { 186 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 187 }; 188 189 int cs4280_init __P((struct cs4280_softc *, int)); 190 int cs4280_open __P((void *, int)); 191 void cs4280_close __P((void *)); 192 193 int cs4280_query_encoding __P((void *, struct audio_encoding *)); 194 int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 195 int cs4280_round_blocksize __P((void *, int)); 196 197 int cs4280_halt_output __P((void *)); 198 int cs4280_halt_input __P((void *)); 199 200 int cs4280_getdev __P((void *, struct audio_device *)); 201 202 int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 203 int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 204 int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 205 void *cs4280_malloc __P((void *, int, size_t, int, int)); 206 void cs4280_free __P((void *, void *, int)); 207 size_t cs4280_round_buffersize __P((void *, int, size_t)); 208 paddr_t cs4280_mappage __P((void *, void *, off_t, int)); 209 int cs4280_get_props __P((void *)); 210 int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 211 void *, struct audio_params *)); 212 int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 213 void *, struct audio_params *)); 214 215 216 void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 217 void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 218 int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 219 char *)); 220 int cs4280_src_wait __P((struct cs4280_softc *)); 221 int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 222 int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 223 int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 224 void cs4280_reset_codec __P((void *sc)); 225 226 void cs4280_power __P((int, void *)); 227 228 void cs4280_clear_fifos __P((struct cs4280_softc *)); 229 230 #if NMIDI > 0 231 void cs4280_midi_close __P((void*)); 232 void cs4280_midi_getinfo __P((void *, struct midi_info *)); 233 int cs4280_midi_open __P((void *, int, void (*)(void *, int), 234 void (*)(void *), void *)); 235 int cs4280_midi_output __P((void *, int)); 236 #endif 237 238 struct audio_hw_if cs4280_hw_if = { 239 cs4280_open, 240 cs4280_close, 241 NULL, 242 cs4280_query_encoding, 243 cs4280_set_params, 244 cs4280_round_blocksize, 245 NULL, 246 NULL, 247 NULL, 248 NULL, 249 NULL, 250 cs4280_halt_output, 251 cs4280_halt_input, 252 NULL, 253 cs4280_getdev, 254 NULL, 255 cs4280_mixer_set_port, 256 cs4280_mixer_get_port, 257 cs4280_query_devinfo, 258 cs4280_malloc, 259 cs4280_free, 260 cs4280_round_buffersize, 261 cs4280_mappage, 262 cs4280_get_props, 263 cs4280_trigger_output, 264 cs4280_trigger_input, 265 }; 266 267 #if NMIDI > 0 268 struct midi_hw_if cs4280_midi_hw_if = { 269 cs4280_midi_open, 270 cs4280_midi_close, 271 cs4280_midi_output, 272 cs4280_midi_getinfo, 273 0, 274 }; 275 #endif 276 277 278 279 struct audio_device cs4280_device = { 280 "CS4280", 281 "", 282 "cs4280" 283 }; 284 285 286 int 287 cs4280_match(parent, match, aux) 288 struct device *parent; 289 struct cfdata *match; 290 void *aux; 291 { 292 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 293 294 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 295 return (0); 296 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 297 #if 0 /* I can't confirm */ 298 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 299 #endif 300 ) 301 return (1); 302 return (0); 303 } 304 305 int 306 cs4280_read_codec(sc_, add, data) 307 void *sc_; 308 u_int8_t add; 309 u_int16_t *data; 310 { 311 struct cs4280_softc *sc = sc_; 312 int n; 313 314 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 315 /* 316 * Make sure that there is not data sitting around from a preivous 317 * uncompleted access. 318 */ 319 BA0READ4(sc, CS4280_ACSDA); 320 321 /* Set up AC97 control registers. */ 322 BA0WRITE4(sc, CS4280_ACCAD, add); 323 BA0WRITE4(sc, CS4280_ACCDA, 0); 324 BA0WRITE4(sc, CS4280_ACCTL, 325 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 326 327 if (cs4280_src_wait(sc) < 0) { 328 printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 329 sc->sc_dev.dv_xname, add); 330 return (1); 331 } 332 333 /* wait for valid status bit is active */ 334 n = 0; 335 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 336 delay(1); 337 while (++n > 1000) { 338 printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 339 sc->sc_dev.dv_xname, add); 340 return (1); 341 } 342 } 343 *data = BA0READ4(sc, CS4280_ACSDA); 344 DPRINTFN(5,("data=0x%04x\n", *data)); 345 return (0); 346 } 347 348 int 349 cs4280_write_codec(sc_, add, data) 350 void *sc_; 351 u_int8_t add; 352 u_int16_t data; 353 { 354 struct cs4280_softc *sc = sc_; 355 356 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 357 BA0WRITE4(sc, CS4280_ACCAD, add); 358 BA0WRITE4(sc, CS4280_ACCDA, data); 359 BA0WRITE4(sc, CS4280_ACCTL, 360 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 361 362 if (cs4280_src_wait(sc) < 0) { 363 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 364 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 365 return (1); 366 } 367 return (0); 368 } 369 370 int 371 cs4280_src_wait(sc) 372 struct cs4280_softc *sc; 373 { 374 int n; 375 n = 0; 376 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 377 delay(1000); 378 while (++n > 1000) 379 return (-1); 380 } 381 return (0); 382 } 383 384 385 void 386 cs4280_set_adc_rate(sc, rate) 387 struct cs4280_softc *sc; 388 int rate; 389 { 390 /* calculate capture rate: 391 * 392 * capture_coefficient_increment = -round(rate*128*65536/48000; 393 * capture_phase_increment = floor(48000*65536*1024/rate); 394 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 395 * cy = floor(cx/200); 396 * capture_sample_rate_correction = cx - 200*cy; 397 * capture_delay = ceil(24*48000/rate); 398 * capture_num_triplets = floor(65536*rate/24000); 399 * capture_group_length = 24000/GCD(rate, 24000); 400 * where GCD means "Greatest Common Divisor". 401 * 402 * capture_coefficient_increment, capture_phase_increment and 403 * capture_num_triplets are 32-bit signed quantities. 404 * capture_sample_rate_correction and capture_group_length are 405 * 16-bit signed quantities. 406 * capture_delay is a 14-bit unsigned quantity. 407 */ 408 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 409 u_int16_t csrc, cgl, cdlay; 410 411 /* XXX 412 * Even though, embedded_audio_spec says capture rate range 11025 to 413 * 48000, dhwiface.cpp says, 414 * 415 * "We can only decimate by up to a factor of 1/9th the hardware rate. 416 * Return an error if an attempt is made to stray outside that limit." 417 * 418 * so assume range as 48000/9 to 48000 419 */ 420 421 if (rate < 8000) 422 rate = 8000; 423 if (rate > 48000) 424 rate = 48000; 425 426 cx = rate << 16; 427 cci = cx / 48000; 428 cx -= cci * 48000; 429 cx <<= 7; 430 cci <<= 7; 431 cci += cx / 48000; 432 cci = - cci; 433 434 cx = 48000 << 16; 435 cpi = cx / rate; 436 cx -= cpi * rate; 437 cx <<= 10; 438 cpi <<= 10; 439 cy = cx / rate; 440 cpi += cy; 441 cx -= cy * rate; 442 443 cy = cx / 200; 444 csrc = cx - 200*cy; 445 446 cdlay = ((48000 * 24) + rate - 1) / rate; 447 #if 0 448 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 449 #endif 450 451 cnt = rate << 16; 452 cnt /= 24000; 453 454 cgl = 1; 455 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 456 if (((rate / tmp1) * tmp1) != rate) 457 cgl *= 2; 458 } 459 if (((rate / 3) * 3) != rate) 460 cgl *= 3; 461 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 462 if (((rate / tmp1) * tmp1) != rate) 463 cgl *= 5; 464 } 465 #if 0 466 /* XXX what manual says */ 467 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 468 tmp1 |= csrc<<16; 469 BA1WRITE4(sc, CS4280_CSRC, tmp1); 470 #else 471 /* suggested by cs461x.c (ALSA driver) */ 472 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 473 #endif 474 475 #if 0 476 /* I am confused. The sample rate calculation section says 477 * cci *is* 32-bit signed quantity but in the parameter description 478 * section, CCI only assigned 16bit. 479 * I believe size of the variable. 480 */ 481 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 482 tmp1 |= cci<<16; 483 BA1WRITE4(sc, CS4280_CCI, tmp1); 484 #else 485 BA1WRITE4(sc, CS4280_CCI, cci); 486 #endif 487 488 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 489 tmp1 |= cdlay <<18; 490 BA1WRITE4(sc, CS4280_CD, tmp1); 491 492 BA1WRITE4(sc, CS4280_CPI, cpi); 493 494 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 495 tmp1 |= cgl; 496 BA1WRITE4(sc, CS4280_CGL, tmp1); 497 498 BA1WRITE4(sc, CS4280_CNT, cnt); 499 500 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 501 tmp1 |= cgl; 502 BA1WRITE4(sc, CS4280_CGC, tmp1); 503 } 504 505 void 506 cs4280_set_dac_rate(sc, rate) 507 struct cs4280_softc *sc; 508 int rate; 509 { 510 /* 511 * playback rate may range from 8000Hz to 48000Hz 512 * 513 * play_phase_increment = floor(rate*65536*1024/48000) 514 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 515 * py=floor(px/200) 516 * play_sample_rate_correction = px - 200*py 517 * 518 * play_phase_increment is a 32bit signed quantity. 519 * play_sample_rate_correction is a 16bit signed quantity. 520 */ 521 int32_t ppi; 522 int16_t psrc; 523 u_int32_t px, py; 524 525 if (rate < 8000) 526 rate = 8000; 527 if (rate > 48000) 528 rate = 48000; 529 px = rate << 16; 530 ppi = px/48000; 531 px -= ppi*48000; 532 ppi <<= 10; 533 px <<= 10; 534 py = px / 48000; 535 ppi += py; 536 px -= py*48000; 537 py = px/200; 538 px -= py*200; 539 psrc = px; 540 #if 0 541 /* what manual says */ 542 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 543 BA1WRITE4(sc, CS4280_PSRC, 544 ( ((psrc<<16) & PSRC_MASK) | px )); 545 #else 546 /* suggested by cs461x.c (ALSA driver) */ 547 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 548 #endif 549 BA1WRITE4(sc, CS4280_PPI, ppi); 550 } 551 552 void 553 cs4280_attach(parent, self, aux) 554 struct device *parent; 555 struct device *self; 556 void *aux; 557 { 558 struct cs4280_softc *sc = (struct cs4280_softc *)self; 559 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 560 pci_chipset_tag_t pc = pa->pa_pc; 561 char const *intrstr; 562 pci_intr_handle_t ih; 563 pcireg_t csr; 564 char devinfo[256]; 565 mixer_ctrl_t ctl; 566 u_int32_t mem; 567 568 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 569 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 570 571 /* Map I/O register */ 572 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 573 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 574 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 575 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 576 return; 577 } 578 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 579 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 580 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 581 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 582 return; 583 } 584 585 sc->sc_dmatag = pa->pa_dmat; 586 587 /* Enable the device (set bus master flag) */ 588 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 589 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 590 csr | PCI_COMMAND_MASTER_ENABLE); 591 592 /* LATENCY_TIMER setting */ 593 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 594 if ( PCI_LATTIMER(mem) < 32 ) { 595 mem &= 0xffff00ff; 596 mem |= 0x00002000; 597 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 598 } 599 600 /* Map and establish the interrupt. */ 601 if (pci_intr_map(pa, &ih)) { 602 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 603 return; 604 } 605 intrstr = pci_intr_string(pc, ih); 606 607 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 608 if (sc->sc_ih == NULL) { 609 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 610 if (intrstr != NULL) 611 printf(" at %s", intrstr); 612 printf("\n"); 613 return; 614 } 615 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 616 617 /* Initialization */ 618 if(cs4280_init(sc, 1) != 0) 619 return; 620 621 /* AC 97 attachement */ 622 sc->host_if.arg = sc; 623 sc->host_if.attach = cs4280_attach_codec; 624 sc->host_if.read = cs4280_read_codec; 625 sc->host_if.write = cs4280_write_codec; 626 sc->host_if.reset = cs4280_reset_codec; 627 628 if (ac97_attach(&sc->host_if) != 0) { 629 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 630 return; 631 } 632 633 /* Turn mute off of DAC, CD and master volumes by default */ 634 ctl.type = AUDIO_MIXER_ENUM; 635 ctl.un.ord = 0; /* off */ 636 637 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 638 AudioNmaster, AudioNmute); 639 cs4280_mixer_set_port(sc, &ctl); 640 641 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 642 AudioNdac, AudioNmute); 643 cs4280_mixer_set_port(sc, &ctl); 644 645 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 646 AudioNcd, AudioNmute); 647 cs4280_mixer_set_port(sc, &ctl); 648 649 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 650 651 #if NMIDI > 0 652 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 653 #endif 654 sc->sc_suspend = PWR_RESUME; 655 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 656 } 657 658 int 659 cs4280_intr(p) 660 void *p; 661 { 662 /* 663 * XXX 664 * 665 * Since CS4280 has only 4kB dma buffer and 666 * interrupt occurs every 2kB block, I create dummy buffer 667 * which returns to audio driver and actual dma buffer 668 * using in DMA transfer. 669 * 670 * 671 * ring buffer in audio.c is pointed by BUFADDR 672 * <------ ring buffer size == 64kB ------> 673 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 674 * |= = = =|= = = =|= = = =|= = = =|= = = =| 675 * | | | | | | <- call audio_intp every 676 * sc->sc_[pr]_count time. 677 * 678 * actual dma buffer is pointed by KERNADDR 679 * <-> dma buffer size = 4kB 680 * |= =| 681 * 682 * 683 */ 684 struct cs4280_softc *sc = p; 685 u_int32_t intr, mem; 686 char * empty_dma; 687 int handled = 0; 688 689 /* grab interrupt register then clear it */ 690 intr = BA0READ4(sc, CS4280_HISR); 691 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 692 693 /* Playback Interrupt */ 694 if (intr & HISR_PINT) { 695 handled = 1; 696 mem = BA1READ4(sc, CS4280_PFIE); 697 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 698 if (sc->sc_pintr) { 699 if ((sc->sc_pi%sc->sc_pcount) == 0) 700 sc->sc_pintr(sc->sc_parg); 701 } else { 702 printf("unexpected play intr\n"); 703 } 704 /* copy buffer */ 705 ++sc->sc_pi; 706 empty_dma = sc->sc_pdma->addr; 707 if (sc->sc_pi&1) 708 empty_dma += CS4280_ICHUNK; 709 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 710 sc->sc_pn += CS4280_ICHUNK; 711 if (sc->sc_pn >= sc->sc_pe) 712 sc->sc_pn = sc->sc_ps; 713 BA1WRITE4(sc, CS4280_PFIE, mem); 714 } 715 /* Capture Interrupt */ 716 if (intr & HISR_CINT) { 717 int i; 718 int16_t rdata; 719 720 handled = 1; 721 mem = BA1READ4(sc, CS4280_CIE); 722 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 723 ++sc->sc_ri; 724 empty_dma = sc->sc_rdma->addr; 725 if ((sc->sc_ri&1) == 0) 726 empty_dma += CS4280_ICHUNK; 727 728 /* 729 * XXX 730 * I think this audio data conversion should be 731 * happend in upper layer, but I put this here 732 * since there is no conversion function available. 733 */ 734 switch(sc->sc_rparam) { 735 case CF_16BIT_STEREO: 736 /* just copy it */ 737 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 738 sc->sc_rn += CS4280_ICHUNK; 739 break; 740 case CF_16BIT_MONO: 741 for (i = 0; i < 512; i++) { 742 rdata = *((int16_t *)empty_dma)++>>1; 743 rdata += *((int16_t *)empty_dma)++>>1; 744 *((int16_t *)sc->sc_rn)++ = rdata; 745 } 746 break; 747 case CF_8BIT_STEREO: 748 for (i = 0; i < 512; i++) { 749 rdata = *((int16_t*)empty_dma)++; 750 *sc->sc_rn++ = rdata >> 8; 751 rdata = *((int16_t*)empty_dma)++; 752 *sc->sc_rn++ = rdata >> 8; 753 } 754 break; 755 case CF_8BIT_MONO: 756 for (i = 0; i < 512; i++) { 757 rdata = *((int16_t*)empty_dma)++ >>1; 758 rdata += *((int16_t*)empty_dma)++ >>1; 759 *sc->sc_rn++ = rdata >>8; 760 } 761 break; 762 default: 763 /* Should not reach here */ 764 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 765 } 766 if (sc->sc_rn >= sc->sc_re) 767 sc->sc_rn = sc->sc_rs; 768 BA1WRITE4(sc, CS4280_CIE, mem); 769 if (sc->sc_rintr) { 770 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 771 sc->sc_rintr(sc->sc_rarg); 772 } else { 773 printf("unexpected record intr\n"); 774 } 775 } 776 777 #if NMIDI > 0 778 /* Midi port Interrupt */ 779 if (intr & HISR_MIDI) { 780 int data; 781 782 handled = 1; 783 DPRINTF(("i: %d: ", 784 BA0READ4(sc, CS4280_MIDSR))); 785 /* Read the received data */ 786 while ((sc->sc_iintr != NULL) && 787 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 788 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 789 DPRINTF(("r:%x\n",data)); 790 sc->sc_iintr(sc->sc_arg, data); 791 } 792 793 /* Write the data */ 794 #if 1 795 /* XXX: 796 * It seems "Transmit Buffer Full" never activate until EOI 797 * is deliverd. Shall I throw EOI top of this routine ? 798 */ 799 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 800 DPRINTF(("w: ")); 801 if (sc->sc_ointr != NULL) 802 sc->sc_ointr(sc->sc_arg); 803 } 804 #else 805 while ((sc->sc_ointr != NULL) && 806 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 807 DPRINTF(("w: ")); 808 sc->sc_ointr(sc->sc_arg); 809 } 810 #endif 811 DPRINTF(("\n")); 812 } 813 #endif 814 815 return (handled); 816 } 817 818 819 /* Download Proceessor Code and Data image */ 820 821 int 822 cs4280_download(sc, src, offset, len) 823 struct cs4280_softc *sc; 824 u_int32_t *src; 825 u_int32_t offset, len; 826 { 827 u_int32_t ctr; 828 829 #ifdef CS4280_DEBUG 830 u_int32_t con, data; 831 u_int8_t c0,c1,c2,c3; 832 #endif 833 if ((offset&3) || (len&3)) 834 return (-1); 835 836 len /= sizeof(u_int32_t); 837 for (ctr = 0; ctr < len; ctr++) { 838 /* XXX: 839 * I cannot confirm this is the right thing or not 840 * on BIG-ENDIAN machines. 841 */ 842 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 843 #ifdef CS4280_DEBUG 844 data = htole32(*(src+ctr)); 845 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 846 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 847 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 848 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 849 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 850 if (data != con ) { 851 printf("0x%06x: write=0x%08x read=0x%08x\n", 852 offset+ctr*4, data, con); 853 return (-1); 854 } 855 #endif 856 } 857 return (0); 858 } 859 860 int 861 cs4280_download_image(sc) 862 struct cs4280_softc *sc; 863 { 864 int idx, err; 865 u_int32_t offset = 0; 866 867 err = 0; 868 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 869 err = cs4280_download(sc, &BA1Struct.map[offset], 870 BA1Struct.memory[idx].offset, 871 BA1Struct.memory[idx].size); 872 if (err != 0) { 873 printf("%s: load_image failed at %d\n", 874 sc->sc_dev.dv_xname, idx); 875 return (-1); 876 } 877 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 878 } 879 return (err); 880 } 881 882 #ifdef CS4280_DEBUG 883 int 884 cs4280_checkimage(sc, src, offset, len) 885 struct cs4280_softc *sc; 886 u_int32_t *src; 887 u_int32_t offset, len; 888 { 889 u_int32_t ctr, data; 890 int err = 0; 891 892 if ((offset&3) || (len&3)) 893 return -1; 894 895 len /= sizeof(u_int32_t); 896 for (ctr = 0; ctr < len; ctr++) { 897 /* I cannot confirm this is the right thing 898 * on BIG-ENDIAN machines 899 */ 900 data = BA1READ4(sc, offset+ctr*4); 901 if (data != htole32(*(src+ctr))) { 902 printf("0x%06x: 0x%08x(0x%08x)\n", 903 offset+ctr*4, data, *(src+ctr)); 904 *(src+ctr) = data; 905 ++err; 906 } 907 } 908 return (err); 909 } 910 911 int 912 cs4280_check_images(sc) 913 struct cs4280_softc *sc; 914 { 915 int idx, err; 916 u_int32_t offset = 0; 917 918 err = 0; 919 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 920 for (idx = 0; idx < 1; ++idx) { 921 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 922 BA1Struct.memory[idx].offset, 923 BA1Struct.memory[idx].size); 924 if (err != 0) { 925 printf("%s: check_image failed at %d\n", 926 sc->sc_dev.dv_xname, idx); 927 } 928 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 929 } 930 return (err); 931 } 932 933 #endif 934 935 int 936 cs4280_attach_codec(sc_, codec_if) 937 void *sc_; 938 struct ac97_codec_if *codec_if; 939 { 940 struct cs4280_softc *sc = sc_; 941 942 sc->codec_if = codec_if; 943 return (0); 944 } 945 946 void 947 cs4280_reset_codec(sc_) 948 void *sc_; 949 { 950 struct cs4280_softc *sc = sc_; 951 int n; 952 953 /* Reset codec */ 954 BA0WRITE4(sc, CS4280_ACCTL, 0); 955 delay(100); /* delay 100us */ 956 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 957 958 /* 959 * It looks like we do the following procedure, too 960 */ 961 962 /* Enable AC-link sync generation */ 963 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 964 delay(50*1000); /* XXX delay 50ms */ 965 966 /* Assert valid frame signal */ 967 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 968 969 /* Wait for valid AC97 input slot */ 970 n = 0; 971 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 972 delay(1000); 973 if (++n > 1000) { 974 printf("reset_codec: AC97 inputs slot ready timeout\n"); 975 return; 976 } 977 } 978 } 979 980 981 /* Processor Soft Reset */ 982 void 983 cs4280_reset(sc_) 984 void *sc_; 985 { 986 struct cs4280_softc *sc = sc_; 987 988 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 989 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 990 delay(100); 991 /* Clear RSTSP bit in SPCR */ 992 BA1WRITE4(sc, CS4280_SPCR, 0); 993 /* enable DMA reqest */ 994 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 995 } 996 997 int 998 cs4280_open(addr, flags) 999 void *addr; 1000 int flags; 1001 { 1002 return (0); 1003 } 1004 1005 void 1006 cs4280_close(addr) 1007 void *addr; 1008 { 1009 struct cs4280_softc *sc = addr; 1010 1011 cs4280_halt_output(sc); 1012 cs4280_halt_input(sc); 1013 1014 sc->sc_pintr = 0; 1015 sc->sc_rintr = 0; 1016 } 1017 1018 int 1019 cs4280_query_encoding(addr, fp) 1020 void *addr; 1021 struct audio_encoding *fp; 1022 { 1023 switch (fp->index) { 1024 case 0: 1025 strcpy(fp->name, AudioEulinear); 1026 fp->encoding = AUDIO_ENCODING_ULINEAR; 1027 fp->precision = 8; 1028 fp->flags = 0; 1029 break; 1030 case 1: 1031 strcpy(fp->name, AudioEmulaw); 1032 fp->encoding = AUDIO_ENCODING_ULAW; 1033 fp->precision = 8; 1034 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1035 break; 1036 case 2: 1037 strcpy(fp->name, AudioEalaw); 1038 fp->encoding = AUDIO_ENCODING_ALAW; 1039 fp->precision = 8; 1040 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1041 break; 1042 case 3: 1043 strcpy(fp->name, AudioEslinear); 1044 fp->encoding = AUDIO_ENCODING_SLINEAR; 1045 fp->precision = 8; 1046 fp->flags = 0; 1047 break; 1048 case 4: 1049 strcpy(fp->name, AudioEslinear_le); 1050 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1051 fp->precision = 16; 1052 fp->flags = 0; 1053 break; 1054 case 5: 1055 strcpy(fp->name, AudioEulinear_le); 1056 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1057 fp->precision = 16; 1058 fp->flags = 0; 1059 break; 1060 case 6: 1061 strcpy(fp->name, AudioEslinear_be); 1062 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1063 fp->precision = 16; 1064 fp->flags = 0; 1065 break; 1066 case 7: 1067 strcpy(fp->name, AudioEulinear_be); 1068 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1069 fp->precision = 16; 1070 fp->flags = 0; 1071 break; 1072 default: 1073 return (EINVAL); 1074 } 1075 return (0); 1076 } 1077 1078 int 1079 cs4280_set_params(addr, setmode, usemode, play, rec) 1080 void *addr; 1081 int setmode, usemode; 1082 struct audio_params *play, *rec; 1083 { 1084 struct cs4280_softc *sc = addr; 1085 struct audio_params *p; 1086 int mode; 1087 1088 for (mode = AUMODE_RECORD; mode != -1; 1089 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1090 if ((setmode & mode) == 0) 1091 continue; 1092 1093 p = mode == AUMODE_PLAY ? play : rec; 1094 1095 if (p == play) { 1096 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1097 p->sample_rate, p->precision, p->channels)); 1098 /* play back data format may be 8- or 16-bit and 1099 * either stereo or mono. 1100 * playback rate may range from 8000Hz to 48000Hz 1101 */ 1102 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1103 (p->precision != 8 && p->precision != 16) || 1104 (p->channels != 1 && p->channels != 2) ) { 1105 return (EINVAL); 1106 } 1107 } else { 1108 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1109 p->sample_rate, p->precision, p->channels)); 1110 /* capture data format must be 16bit stereo 1111 * and sample rate range from 11025Hz to 48000Hz. 1112 * 1113 * XXX: it looks like to work with 8000Hz, 1114 * although data sheets say lower limit is 1115 * 11025 Hz. 1116 */ 1117 1118 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1119 (p->precision != 8 && p->precision != 16) || 1120 (p->channels != 1 && p->channels != 2) ) { 1121 return (EINVAL); 1122 } 1123 } 1124 p->factor = 1; 1125 p->sw_code = 0; 1126 1127 /* capturing data is slinear */ 1128 switch (p->encoding) { 1129 case AUDIO_ENCODING_SLINEAR_BE: 1130 if (mode == AUMODE_RECORD) { 1131 if (p->precision == 16) 1132 p->sw_code = swap_bytes; 1133 } 1134 break; 1135 case AUDIO_ENCODING_SLINEAR_LE: 1136 break; 1137 case AUDIO_ENCODING_ULINEAR_BE: 1138 if (mode == AUMODE_RECORD) { 1139 if (p->precision == 16) 1140 p->sw_code = change_sign16_swap_bytes_le; 1141 else 1142 p->sw_code = change_sign8; 1143 } 1144 break; 1145 case AUDIO_ENCODING_ULINEAR_LE: 1146 if (mode == AUMODE_RECORD) { 1147 if (p->precision == 16) 1148 p->sw_code = change_sign16_le; 1149 else 1150 p->sw_code = change_sign8; 1151 } 1152 break; 1153 case AUDIO_ENCODING_ULAW: 1154 if (mode == AUMODE_PLAY) { 1155 p->factor = 2; 1156 p->sw_code = mulaw_to_slinear16_le; 1157 } else { 1158 p->sw_code = slinear8_to_mulaw; 1159 } 1160 break; 1161 case AUDIO_ENCODING_ALAW: 1162 if (mode == AUMODE_PLAY) { 1163 p->factor = 2; 1164 p->sw_code = alaw_to_slinear16_le; 1165 } else { 1166 p->sw_code = slinear8_to_alaw; 1167 } 1168 break; 1169 default: 1170 return (EINVAL); 1171 } 1172 } 1173 1174 /* set sample rate */ 1175 cs4280_set_dac_rate(sc, play->sample_rate); 1176 cs4280_set_adc_rate(sc, rec->sample_rate); 1177 return (0); 1178 } 1179 1180 int 1181 cs4280_round_blocksize(hdl, blk) 1182 void *hdl; 1183 int blk; 1184 { 1185 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1186 } 1187 1188 size_t 1189 cs4280_round_buffersize(addr, direction, size) 1190 void *addr; 1191 int direction; 1192 size_t size; 1193 { 1194 /* although real dma buffer size is 4KB, 1195 * let the audio.c driver use a larger buffer. 1196 * ( suggested by Lennart Augustsson. ) 1197 */ 1198 return (size); 1199 } 1200 1201 int 1202 cs4280_get_props(hdl) 1203 void *hdl; 1204 { 1205 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1206 #ifdef notyet 1207 /* XXX 1208 * How can I mmap ? 1209 */ 1210 AUDIO_PROP_MMAP 1211 #endif 1212 1213 } 1214 1215 int 1216 cs4280_mixer_get_port(addr, cp) 1217 void *addr; 1218 mixer_ctrl_t *cp; 1219 { 1220 struct cs4280_softc *sc = addr; 1221 1222 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1223 } 1224 1225 paddr_t 1226 cs4280_mappage(addr, mem, off, prot) 1227 void *addr; 1228 void *mem; 1229 off_t off; 1230 int prot; 1231 { 1232 struct cs4280_softc *sc = addr; 1233 struct cs4280_dma *p; 1234 1235 if (off < 0) 1236 return (-1); 1237 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1238 ; 1239 if (!p) { 1240 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1241 return (-1); 1242 } 1243 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1244 off, prot, BUS_DMA_WAITOK)); 1245 } 1246 1247 1248 int 1249 cs4280_query_devinfo(addr, dip) 1250 void *addr; 1251 mixer_devinfo_t *dip; 1252 { 1253 struct cs4280_softc *sc = addr; 1254 1255 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1256 } 1257 1258 int 1259 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1260 struct cs4280_softc *sc; 1261 char *class, *device, *qualifier; 1262 { 1263 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1264 device, qualifier)); 1265 } 1266 1267 int 1268 cs4280_halt_output(addr) 1269 void *addr; 1270 { 1271 struct cs4280_softc *sc = addr; 1272 u_int32_t mem; 1273 1274 mem = BA1READ4(sc, CS4280_PCTL); 1275 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1276 #ifdef DIAGNOSTIC 1277 sc->sc_prun = 0; 1278 #endif 1279 return (0); 1280 } 1281 1282 int 1283 cs4280_halt_input(addr) 1284 void *addr; 1285 { 1286 struct cs4280_softc *sc = addr; 1287 u_int32_t mem; 1288 1289 mem = BA1READ4(sc, CS4280_CCTL); 1290 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1291 #ifdef DIAGNOSTIC 1292 sc->sc_rrun = 0; 1293 #endif 1294 return (0); 1295 } 1296 1297 int 1298 cs4280_getdev(addr, retp) 1299 void *addr; 1300 struct audio_device *retp; 1301 { 1302 *retp = cs4280_device; 1303 return (0); 1304 } 1305 1306 int 1307 cs4280_mixer_set_port(addr, cp) 1308 void *addr; 1309 mixer_ctrl_t *cp; 1310 { 1311 struct cs4280_softc *sc = addr; 1312 int val; 1313 1314 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1315 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1316 return (val); 1317 } 1318 1319 1320 int 1321 cs4280_freemem(sc, p) 1322 struct cs4280_softc *sc; 1323 struct cs4280_dma *p; 1324 { 1325 bus_dmamap_unload(sc->sc_dmatag, p->map); 1326 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1327 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1328 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1329 return (0); 1330 } 1331 1332 int 1333 cs4280_allocmem(sc, size, align, p) 1334 struct cs4280_softc *sc; 1335 size_t size; 1336 size_t align; 1337 struct cs4280_dma *p; 1338 { 1339 int error; 1340 1341 /* XXX */ 1342 p->size = size; 1343 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1344 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1345 &p->nsegs, BUS_DMA_NOWAIT); 1346 if (error) { 1347 printf("%s: unable to allocate dma, error=%d\n", 1348 sc->sc_dev.dv_xname, error); 1349 return (error); 1350 } 1351 1352 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1353 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1354 if (error) { 1355 printf("%s: unable to map dma, error=%d\n", 1356 sc->sc_dev.dv_xname, error); 1357 goto free; 1358 } 1359 1360 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1361 0, BUS_DMA_NOWAIT, &p->map); 1362 if (error) { 1363 printf("%s: unable to create dma map, error=%d\n", 1364 sc->sc_dev.dv_xname, error); 1365 goto unmap; 1366 } 1367 1368 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1369 BUS_DMA_NOWAIT); 1370 if (error) { 1371 printf("%s: unable to load dma map, error=%d\n", 1372 sc->sc_dev.dv_xname, error); 1373 goto destroy; 1374 } 1375 return (0); 1376 1377 destroy: 1378 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1379 unmap: 1380 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1381 free: 1382 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1383 return (error); 1384 } 1385 1386 1387 void * 1388 cs4280_malloc(addr, direction, size, pool, flags) 1389 void *addr; 1390 int direction; 1391 size_t size; 1392 int pool, flags; 1393 { 1394 struct cs4280_softc *sc = addr; 1395 struct cs4280_dma *p; 1396 caddr_t q; 1397 int error; 1398 1399 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1400 q = malloc(size, pool, flags); 1401 if (!q) 1402 return (0); 1403 p = malloc(sizeof(*p), pool, flags); 1404 if (!p) { 1405 free(q,pool); 1406 return (0); 1407 } 1408 /* 1409 * cs4280 has fixed 4kB buffer 1410 */ 1411 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1412 1413 if (error) { 1414 free(q, pool); 1415 free(p, pool); 1416 return (0); 1417 } 1418 1419 p->next = sc->sc_dmas; 1420 sc->sc_dmas = p; 1421 p->dum = q; /* return to audio driver */ 1422 1423 return (p->dum); 1424 } 1425 1426 void 1427 cs4280_free(addr, ptr, pool) 1428 void *addr; 1429 void *ptr; 1430 int pool; 1431 { 1432 struct cs4280_softc *sc = addr; 1433 struct cs4280_dma **pp, *p; 1434 1435 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1436 if (BUFADDR(p) == ptr) { 1437 cs4280_freemem(sc, p); 1438 *pp = p->next; 1439 free(p->dum, pool); 1440 free(p, pool); 1441 return; 1442 } 1443 } 1444 } 1445 1446 int 1447 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1448 void *addr; 1449 void *start, *end; 1450 int blksize; 1451 void (*intr) __P((void *)); 1452 void *arg; 1453 struct audio_params *param; 1454 { 1455 struct cs4280_softc *sc = addr; 1456 u_int32_t pfie, pctl, mem, pdtc; 1457 struct cs4280_dma *p; 1458 1459 #ifdef DIAGNOSTIC 1460 if (sc->sc_prun) 1461 printf("cs4280_trigger_output: already running\n"); 1462 sc->sc_prun = 1; 1463 #endif 1464 1465 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1466 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1467 sc->sc_pintr = intr; 1468 sc->sc_parg = arg; 1469 1470 /* stop playback DMA */ 1471 mem = BA1READ4(sc, CS4280_PCTL); 1472 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1473 1474 /* setup PDTC */ 1475 pdtc = BA1READ4(sc, CS4280_PDTC); 1476 pdtc &= ~PDTC_MASK; 1477 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1478 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1479 1480 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1481 param->precision, param->factor, param->channels, 1482 param->encoding)); 1483 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1484 ; 1485 if (p == NULL) { 1486 printf("cs4280_trigger_output: bad addr %p\n", start); 1487 return (EINVAL); 1488 } 1489 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1490 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1491 "4kB align\n", DMAADDR(p)); 1492 return (EINVAL); 1493 } 1494 1495 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1496 sc->sc_ps = (char *)start; 1497 sc->sc_pe = (char *)end; 1498 sc->sc_pdma = p; 1499 sc->sc_pbuf = KERNADDR(p); 1500 sc->sc_pi = 0; 1501 sc->sc_pn = sc->sc_ps; 1502 if (blksize >= CS4280_DCHUNK) { 1503 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1504 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1505 ++sc->sc_pi; 1506 } else { 1507 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1508 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1509 } 1510 1511 /* initiate playback dma */ 1512 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1513 1514 /* set PFIE */ 1515 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1516 1517 if (param->precision * param->factor == 8) 1518 pfie |= PFIE_8BIT; 1519 if (param->channels == 1) 1520 pfie |= PFIE_MONO; 1521 1522 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1523 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1524 pfie |= PFIE_SWAPPED; 1525 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1526 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1527 pfie |= PFIE_UNSIGNED; 1528 1529 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1530 1531 cs4280_set_dac_rate(sc, param->sample_rate); 1532 1533 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1534 pctl |= sc->pctl; 1535 BA1WRITE4(sc, CS4280_PCTL, pctl); 1536 return (0); 1537 } 1538 1539 int 1540 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1541 void *addr; 1542 void *start, *end; 1543 int blksize; 1544 void (*intr) __P((void *)); 1545 void *arg; 1546 struct audio_params *param; 1547 { 1548 struct cs4280_softc *sc = addr; 1549 u_int32_t cctl, cie; 1550 struct cs4280_dma *p; 1551 1552 #ifdef DIAGNOSTIC 1553 if (sc->sc_rrun) 1554 printf("cs4280_trigger_input: already running\n"); 1555 sc->sc_rrun = 1; 1556 #endif 1557 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1558 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1559 sc->sc_rintr = intr; 1560 sc->sc_rarg = arg; 1561 1562 sc->sc_ri = 0; 1563 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1564 sc->sc_rs = (char *)start; 1565 sc->sc_re = (char *)end; 1566 sc->sc_rn = sc->sc_rs; 1567 1568 /* setup format information for internal converter */ 1569 sc->sc_rparam = 0; 1570 if (param->precision == 8) { 1571 sc->sc_rparam += CF_8BIT; 1572 sc->sc_rcount <<= 1; 1573 } 1574 if (param->channels == 1) { 1575 sc->sc_rparam += CF_MONO; 1576 sc->sc_rcount <<= 1; 1577 } 1578 1579 /* stop capture DMA */ 1580 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1581 BA1WRITE4(sc, CS4280_CCTL, cctl); 1582 1583 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1584 ; 1585 if (!p) { 1586 printf("cs4280_trigger_input: bad addr %p\n", start); 1587 return (EINVAL); 1588 } 1589 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1590 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1591 "4kB align\n", DMAADDR(p)); 1592 return (EINVAL); 1593 } 1594 sc->sc_rdma = p; 1595 sc->sc_rbuf = KERNADDR(p); 1596 1597 /* initiate capture dma */ 1598 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1599 1600 /* set CIE */ 1601 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1602 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1603 1604 cs4280_set_adc_rate(sc, param->sample_rate); 1605 1606 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1607 cctl |= sc->cctl; 1608 BA1WRITE4(sc, CS4280_CCTL, cctl); 1609 return (0); 1610 } 1611 1612 int 1613 cs4280_init(sc, init) 1614 struct cs4280_softc *sc; 1615 int init; 1616 { 1617 int n; 1618 u_int32_t mem; 1619 1620 /* Start PLL out in known state */ 1621 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1622 /* Start serial ports out in known state */ 1623 BA0WRITE4(sc, CS4280_SERMC1, 0); 1624 1625 /* Specify type of CODEC */ 1626 /* XXX should not be here */ 1627 #define SERACC_CODEC_TYPE_1_03 1628 #ifdef SERACC_CODEC_TYPE_1_03 1629 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1630 #else 1631 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1632 #endif 1633 1634 /* Reset codec */ 1635 BA0WRITE4(sc, CS4280_ACCTL, 0); 1636 delay(100); /* delay 100us */ 1637 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1638 1639 /* Enable AC-link sync generation */ 1640 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1641 delay(50*1000); /* delay 50ms */ 1642 1643 /* Set the serial port timing configuration */ 1644 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1645 1646 /* Setup clock control */ 1647 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1648 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1649 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1650 1651 /* Power up the PLL */ 1652 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1653 delay(50*1000); /* delay 50ms */ 1654 1655 /* Turn on clock */ 1656 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1657 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1658 1659 /* Set the serial port FIFO pointer to the 1660 * first sample in FIFO. (not documented) */ 1661 cs4280_clear_fifos(sc); 1662 1663 #if 0 1664 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1665 BA0WRITE4(sc, CS4280_SERBSP, 0); 1666 #endif 1667 1668 /* Configure the serial port */ 1669 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1670 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1671 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1672 1673 /* Wait for CODEC ready */ 1674 n = 0; 1675 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1676 delay(125); 1677 if (++n > 1000) { 1678 printf("%s: codec ready timeout\n", 1679 sc->sc_dev.dv_xname); 1680 return(1); 1681 } 1682 } 1683 1684 /* Assert valid frame signal */ 1685 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1686 1687 /* Wait for valid AC97 input slot */ 1688 n = 0; 1689 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1690 (ACISV_ISV3 | ACISV_ISV4)) { 1691 delay(1000); 1692 if (++n > 1000) { 1693 printf("AC97 inputs slot ready timeout\n"); 1694 return(1); 1695 } 1696 } 1697 1698 /* Set AC97 output slot valid signals */ 1699 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1700 1701 /* reset the processor */ 1702 cs4280_reset(sc); 1703 1704 /* Download the image to the processor */ 1705 if (cs4280_download_image(sc) != 0) { 1706 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1707 return(1); 1708 } 1709 1710 /* Save playback parameter and then write zero. 1711 * this ensures that DMA doesn't immediately occur upon 1712 * starting the processor core 1713 */ 1714 mem = BA1READ4(sc, CS4280_PCTL); 1715 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1716 cs4280_halt_output(sc); 1717 1718 /* Save capture parameter and then write zero. 1719 * this ensures that DMA doesn't immediately occur upon 1720 * starting the processor core 1721 */ 1722 mem = BA1READ4(sc, CS4280_CCTL); 1723 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1724 cs4280_halt_input(sc); 1725 1726 /* Processor Startup Procedure */ 1727 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1728 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1729 1730 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1731 n = 0; 1732 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1733 delay(10); 1734 if (++n > 1000) { 1735 printf("SPCR 1->0 transition timeout\n"); 1736 return(1); 1737 } 1738 } 1739 1740 n = 0; 1741 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1742 delay(10); 1743 if (++n > 1000) { 1744 printf("SPCS 0->1 transition timeout\n"); 1745 return(1); 1746 } 1747 } 1748 /* Processor is now running !!! */ 1749 1750 /* Setup volume */ 1751 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1752 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1753 1754 /* Interrupt enable */ 1755 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1756 1757 /* playback interrupt enable */ 1758 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1759 mem |= PFIE_PI_ENABLE; 1760 BA1WRITE4(sc, CS4280_PFIE, mem); 1761 /* capture interrupt enable */ 1762 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1763 mem |= CIE_CI_ENABLE; 1764 BA1WRITE4(sc, CS4280_CIE, mem); 1765 1766 #if NMIDI > 0 1767 /* Reset midi port */ 1768 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1769 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1770 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1771 /* midi interrupt enable */ 1772 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1773 BA0WRITE4(sc, CS4280_MIDCR, mem); 1774 #endif 1775 return(0); 1776 } 1777 1778 void 1779 cs4280_power(why, v) 1780 int why; 1781 void *v; 1782 { 1783 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1784 1785 DPRINTF(("%s: cs4280_power why=%d\n", 1786 sc->sc_dev.dv_xname, why)); 1787 switch (why) { 1788 case PWR_SUSPEND: 1789 case PWR_STANDBY: 1790 sc->sc_suspend = why; 1791 1792 cs4280_halt_output(sc); 1793 cs4280_halt_input(sc); 1794 /* should I powerdown here ? */ 1795 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1796 break; 1797 case PWR_RESUME: 1798 if (sc->sc_suspend == PWR_RESUME) { 1799 printf("cs4280_power: odd, resume without suspend.\n"); 1800 sc->sc_suspend = why; 1801 return; 1802 } 1803 sc->sc_suspend = why; 1804 cs4280_init(sc, 0); 1805 cs4280_reset_codec(sc); 1806 1807 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1808 break; 1809 case PWR_SOFTSUSPEND: 1810 case PWR_SOFTSTANDBY: 1811 case PWR_SOFTRESUME: 1812 break; 1813 } 1814 } 1815 1816 void 1817 cs4280_clear_fifos(sc) 1818 struct cs4280_softc *sc; 1819 { 1820 int pd = 0, cnt, n; 1821 u_int32_t mem; 1822 1823 /* 1824 * If device power down, power up the device and keep power down 1825 * state. 1826 */ 1827 mem = BA0READ4(sc, CS4280_CLKCR1); 1828 if (!(mem & CLKCR1_SWCE)) { 1829 printf("cs4280_clear_fifo: power down found.\n"); 1830 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1831 pd = 1; 1832 } 1833 BA0WRITE4(sc, CS4280_SERBWP, 0); 1834 for (cnt = 0; cnt < 256; cnt++) { 1835 n = 0; 1836 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1837 delay(1000); 1838 if (++n > 1000) { 1839 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1840 break; 1841 } 1842 } 1843 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1844 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1845 } 1846 if (pd) 1847 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1848 } 1849 1850 #if NMIDI > 0 1851 int 1852 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1853 void *addr; 1854 int flags; 1855 void (*iintr)__P((void *, int)); 1856 void (*ointr)__P((void *)); 1857 void *arg; 1858 { 1859 struct cs4280_softc *sc = addr; 1860 u_int32_t mem; 1861 1862 DPRINTF(("midi_open\n")); 1863 sc->sc_iintr = iintr; 1864 sc->sc_ointr = ointr; 1865 sc->sc_arg = arg; 1866 1867 /* midi interrupt enable */ 1868 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1869 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1870 BA0WRITE4(sc, CS4280_MIDCR, mem); 1871 #ifdef CS4280_DEBUG 1872 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1873 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1874 return(EINVAL); 1875 } 1876 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1877 #endif 1878 return (0); 1879 } 1880 1881 void 1882 cs4280_midi_close(addr) 1883 void *addr; 1884 { 1885 struct cs4280_softc *sc = addr; 1886 u_int32_t mem; 1887 1888 DPRINTF(("midi_close\n")); 1889 mem = BA0READ4(sc, CS4280_MIDCR); 1890 mem &= ~MIDCR_MASK; 1891 BA0WRITE4(sc, CS4280_MIDCR, mem); 1892 1893 sc->sc_iintr = 0; 1894 sc->sc_ointr = 0; 1895 } 1896 1897 int 1898 cs4280_midi_output(addr, d) 1899 void *addr; 1900 int d; 1901 { 1902 struct cs4280_softc *sc = addr; 1903 u_int32_t mem; 1904 int x; 1905 1906 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1907 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1908 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1909 mem |= d & MIDWP_MASK; 1910 DPRINTFN(5,("midi_output d=0x%08x",d)); 1911 BA0WRITE4(sc, CS4280_MIDWP, mem); 1912 #ifdef DIAGNOSTIC 1913 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1914 DPRINTF(("Bad write data: %d %d", 1915 mem, BA0READ4(sc, CS4280_MIDWP))); 1916 return(EIO); 1917 } 1918 #endif 1919 return (0); 1920 } 1921 delay(MIDI_BUSY_DELAY); 1922 } 1923 return (EIO); 1924 } 1925 1926 void 1927 cs4280_midi_getinfo(addr, mi) 1928 void *addr; 1929 struct midi_info *mi; 1930 { 1931 mi->name = "CS4280 MIDI UART"; 1932 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1933 } 1934 1935 #endif 1936
Indexes created Thu Oct 02 14:10:14 GMT 2025