cs4280.c revision 1.7.2.6
1 /* $NetBSD: cs4280.c,v 1.7.2.6 2001/02/11 19:15:48 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include "midi.h" 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/fcntl.h> 60 #include <sys/malloc.h> 61 #include <sys/device.h> 62 #include <sys/proc.h> 63 #include <sys/types.h> 64 #include <sys/systm.h> 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/cs4280reg.h> 69 #include <dev/pci/cs4280_image.h> 70 #include <dev/pci/cs428xreg.h> 71 72 #include <sys/audioio.h> 73 #include <dev/audio_if.h> 74 #include <dev/midi_if.h> 75 #include <dev/mulaw.h> 76 #include <dev/auconv.h> 77 78 #include <dev/ic/ac97reg.h> 79 #include <dev/ic/ac97var.h> 80 81 #include <dev/pci/cs428x.h> 82 83 #include <machine/bus.h> 84 #include <machine/bswap.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 int cs4280_match(struct device *, struct cfdata *, void *); 91 void cs4280_attach(struct device *, struct device *, void *); 92 int cs4280_intr(void *); 93 int cs4280_query_encoding(void *, struct audio_encoding *); 94 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 95 int cs4280_halt_output(void *); 96 int cs4280_halt_input(void *); 97 int cs4280_getdev(void *, struct audio_device *); 98 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 99 void *, struct audio_params *); 100 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 101 void *, struct audio_params *); 102 103 void cs4280_reset_codec(void *); 104 105 /* For PowerHook */ 106 void cs4280_power(int, void *); 107 108 /* Internal functions */ 109 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 110 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 111 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 112 int cs4280_download_image(struct cs428x_softc *); 113 void cs4280_reset(void *); 114 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 115 int cs4280_init(struct cs428x_softc *, int); 116 void cs4280_clear_fifos(struct cs428x_softc *); 117 118 #if CS4280_DEBUG > 10 119 /* Thease two function is only for checking image loading is succeeded or not. */ 120 int cs4280_check_images(struct cs428x_softc *); 121 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 122 #endif 123 124 struct audio_hw_if cs4280_hw_if = { 125 cs428x_open, 126 cs428x_close, 127 NULL, 128 cs4280_query_encoding, 129 cs4280_set_params, 130 cs428x_round_blocksize, 131 NULL, 132 NULL, 133 NULL, 134 NULL, 135 NULL, 136 cs4280_halt_output, 137 cs4280_halt_input, 138 NULL, 139 cs4280_getdev, 140 NULL, 141 cs428x_mixer_set_port, 142 cs428x_mixer_get_port, 143 cs428x_query_devinfo, 144 cs428x_malloc, 145 cs428x_free, 146 cs428x_round_buffersize, 147 cs428x_mappage, 148 cs428x_get_props, 149 cs4280_trigger_output, 150 cs4280_trigger_input, 151 }; 152 153 #if NMIDI > 0 154 /* Midi Interface */ 155 int cs4280_midi_open(void *, int, void (*)(void *, int), 156 void (*)(void *), void *); 157 void cs4280_midi_close(void*); 158 int cs4280_midi_output(void *, int); 159 void cs4280_midi_getinfo(void *, struct midi_info *); 160 161 struct midi_hw_if cs4280_midi_hw_if = { 162 cs4280_midi_open, 163 cs4280_midi_close, 164 cs4280_midi_output, 165 cs4280_midi_getinfo, 166 0, 167 }; 168 #endif 169 170 struct cfattach clcs_ca = { 171 sizeof(struct cs428x_softc), cs4280_match, cs4280_attach 172 }; 173 174 struct audio_device cs4280_device = { 175 "CS4280", 176 "", 177 "cs4280" 178 }; 179 180 181 int 182 cs4280_match(parent, match, aux) 183 struct device *parent; 184 struct cfdata *match; 185 void *aux; 186 { 187 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 188 189 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 190 return 0; 191 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 192 #if 0 /* I can't confirm */ 193 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 194 #endif 195 ) 196 return 1; 197 return 0; 198 } 199 200 void 201 cs4280_attach(parent, self, aux) 202 struct device *parent; 203 struct device *self; 204 void *aux; 205 { 206 struct cs428x_softc *sc = (struct cs428x_softc *)self; 207 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 208 pci_chipset_tag_t pc = pa->pa_pc; 209 char const *intrstr; 210 pci_intr_handle_t ih; 211 pcireg_t csr; 212 char devinfo[256]; 213 mixer_ctrl_t ctl; 214 u_int32_t mem; 215 216 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 217 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 218 219 /* Map I/O register */ 220 if (pci_mapreg_map(pa, PCI_BA0, 221 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 222 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 223 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 224 return; 225 } 226 if (pci_mapreg_map(pa, PCI_BA1, 227 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 228 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 229 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 233 sc->sc_dmatag = pa->pa_dmat; 234 235 /* Enable the device (set bus master flag) */ 236 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 237 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 238 csr | PCI_COMMAND_MASTER_ENABLE); 239 240 /* LATENCY_TIMER setting */ 241 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 242 if ( PCI_LATTIMER(mem) < 32 ) { 243 mem &= 0xffff00ff; 244 mem |= 0x00002000; 245 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 246 } 247 248 /* Map and establish the interrupt. */ 249 if (pci_intr_map(pa, &ih)) { 250 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 251 return; 252 } 253 intrstr = pci_intr_string(pc, ih); 254 255 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 256 if (sc->sc_ih == NULL) { 257 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 258 if (intrstr != NULL) 259 printf(" at %s", intrstr); 260 printf("\n"); 261 return; 262 } 263 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 264 265 /* Initialization */ 266 if(cs4280_init(sc, 1) != 0) 267 return; 268 269 sc->type = TYPE_CS4280; 270 sc->halt_input = cs4280_halt_input; 271 sc->halt_output = cs4280_halt_output; 272 273 /* setup buffer related parameters */ 274 sc->dma_size = CS4280_DCHUNK; 275 sc->dma_align = CS4280_DALIGN; 276 sc->hw_blocksize = CS4280_ICHUNK; 277 278 /* AC 97 attachment */ 279 sc->host_if.arg = sc; 280 sc->host_if.attach = cs428x_attach_codec; 281 sc->host_if.read = cs428x_read_codec; 282 sc->host_if.write = cs428x_write_codec; 283 sc->host_if.reset = cs4280_reset_codec; 284 if (ac97_attach(&sc->host_if) != 0) { 285 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 286 return; 287 } 288 289 /* Turn mute off of DAC, CD and master volumes by default */ 290 ctl.type = AUDIO_MIXER_ENUM; 291 ctl.un.ord = 0; /* off */ 292 293 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 294 AudioNmaster, AudioNmute); 295 cs428x_mixer_set_port(sc, &ctl); 296 297 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 298 AudioNdac, AudioNmute); 299 cs428x_mixer_set_port(sc, &ctl); 300 301 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 302 AudioNcd, AudioNmute); 303 cs428x_mixer_set_port(sc, &ctl); 304 305 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 306 307 #if NMIDI > 0 308 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 309 #endif 310 311 sc->sc_suspend = PWR_RESUME; 312 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 313 } 314 315 /* Interrupt handling function */ 316 int 317 cs4280_intr(p) 318 void *p; 319 { 320 /* 321 * XXX 322 * 323 * Since CS4280 has only 4kB dma buffer and 324 * interrupt occurs every 2kB block, I create dummy buffer 325 * which returns to audio driver and actual dma buffer 326 * using in DMA transfer. 327 * 328 * 329 * ring buffer in audio.c is pointed by BUFADDR 330 * <------ ring buffer size == 64kB ------> 331 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 332 * |= = = =|= = = =|= = = =|= = = =|= = = =| 333 * | | | | | | <- call audio_intp every 334 * sc->sc_[pr]_count time. 335 * 336 * actual dma buffer is pointed by KERNADDR 337 * <-> dma buffer size = 4kB 338 * |= =| 339 * 340 * 341 */ 342 struct cs428x_softc *sc = p; 343 u_int32_t intr, mem; 344 char * empty_dma; 345 int handled = 0; 346 347 /* grab interrupt register then clear it */ 348 intr = BA0READ4(sc, CS4280_HISR); 349 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 350 351 /* Playback Interrupt */ 352 if (intr & HISR_PINT) { 353 handled = 1; 354 mem = BA1READ4(sc, CS4280_PFIE); 355 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 356 if (sc->sc_pintr) { 357 if ((sc->sc_pi%sc->sc_pcount) == 0) 358 sc->sc_pintr(sc->sc_parg); 359 } else { 360 printf("unexpected play intr\n"); 361 } 362 /* copy buffer */ 363 ++sc->sc_pi; 364 empty_dma = sc->sc_pdma->addr; 365 if (sc->sc_pi&1) 366 empty_dma += sc->hw_blocksize; 367 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 368 sc->sc_pn += sc->hw_blocksize; 369 if (sc->sc_pn >= sc->sc_pe) 370 sc->sc_pn = sc->sc_ps; 371 BA1WRITE4(sc, CS4280_PFIE, mem); 372 } 373 /* Capture Interrupt */ 374 if (intr & HISR_CINT) { 375 int i; 376 int16_t rdata; 377 378 handled = 1; 379 mem = BA1READ4(sc, CS4280_CIE); 380 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 381 ++sc->sc_ri; 382 empty_dma = sc->sc_rdma->addr; 383 if ((sc->sc_ri&1) == 0) 384 empty_dma += sc->hw_blocksize; 385 386 /* 387 * XXX 388 * I think this audio data conversion should be 389 * happend in upper layer, but I put this here 390 * since there is no conversion function available. 391 */ 392 switch(sc->sc_rparam) { 393 case CF_16BIT_STEREO: 394 /* just copy it */ 395 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 396 sc->sc_rn += sc->hw_blocksize; 397 break; 398 case CF_16BIT_MONO: 399 for (i = 0; i < 512; i++) { 400 rdata = *((int16_t *)empty_dma)++>>1; 401 rdata += *((int16_t *)empty_dma)++>>1; 402 *((int16_t *)sc->sc_rn)++ = rdata; 403 } 404 break; 405 case CF_8BIT_STEREO: 406 for (i = 0; i < 512; i++) { 407 rdata = *((int16_t*)empty_dma)++; 408 *sc->sc_rn++ = rdata >> 8; 409 rdata = *((int16_t*)empty_dma)++; 410 *sc->sc_rn++ = rdata >> 8; 411 } 412 break; 413 case CF_8BIT_MONO: 414 for (i = 0; i < 512; i++) { 415 rdata = *((int16_t*)empty_dma)++ >>1; 416 rdata += *((int16_t*)empty_dma)++ >>1; 417 *sc->sc_rn++ = rdata >>8; 418 } 419 break; 420 default: 421 /* Should not reach here */ 422 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 423 } 424 if (sc->sc_rn >= sc->sc_re) 425 sc->sc_rn = sc->sc_rs; 426 BA1WRITE4(sc, CS4280_CIE, mem); 427 if (sc->sc_rintr) { 428 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 429 sc->sc_rintr(sc->sc_rarg); 430 } else { 431 printf("unexpected record intr\n"); 432 } 433 } 434 435 #if NMIDI > 0 436 /* Midi port Interrupt */ 437 if (intr & HISR_MIDI) { 438 int data; 439 440 handled = 1; 441 DPRINTF(("i: %d: ", 442 BA0READ4(sc, CS4280_MIDSR))); 443 /* Read the received data */ 444 while ((sc->sc_iintr != NULL) && 445 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 446 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 447 DPRINTF(("r:%x\n",data)); 448 sc->sc_iintr(sc->sc_arg, data); 449 } 450 451 /* Write the data */ 452 #if 1 453 /* XXX: 454 * It seems "Transmit Buffer Full" never activate until EOI 455 * is deliverd. Shall I throw EOI top of this routine ? 456 */ 457 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 458 DPRINTF(("w: ")); 459 if (sc->sc_ointr != NULL) 460 sc->sc_ointr(sc->sc_arg); 461 } 462 #else 463 while ((sc->sc_ointr != NULL) && 464 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 465 DPRINTF(("w: ")); 466 sc->sc_ointr(sc->sc_arg); 467 } 468 #endif 469 DPRINTF(("\n")); 470 } 471 #endif 472 473 return handled; 474 } 475 476 int 477 cs4280_query_encoding(addr, fp) 478 void *addr; 479 struct audio_encoding *fp; 480 { 481 switch (fp->index) { 482 case 0: 483 strcpy(fp->name, AudioEulinear); 484 fp->encoding = AUDIO_ENCODING_ULINEAR; 485 fp->precision = 8; 486 fp->flags = 0; 487 break; 488 case 1: 489 strcpy(fp->name, AudioEmulaw); 490 fp->encoding = AUDIO_ENCODING_ULAW; 491 fp->precision = 8; 492 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 493 break; 494 case 2: 495 strcpy(fp->name, AudioEalaw); 496 fp->encoding = AUDIO_ENCODING_ALAW; 497 fp->precision = 8; 498 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 499 break; 500 case 3: 501 strcpy(fp->name, AudioEslinear); 502 fp->encoding = AUDIO_ENCODING_SLINEAR; 503 fp->precision = 8; 504 fp->flags = 0; 505 break; 506 case 4: 507 strcpy(fp->name, AudioEslinear_le); 508 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 509 fp->precision = 16; 510 fp->flags = 0; 511 break; 512 case 5: 513 strcpy(fp->name, AudioEulinear_le); 514 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 515 fp->precision = 16; 516 fp->flags = 0; 517 break; 518 case 6: 519 strcpy(fp->name, AudioEslinear_be); 520 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 521 fp->precision = 16; 522 fp->flags = 0; 523 break; 524 case 7: 525 strcpy(fp->name, AudioEulinear_be); 526 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 527 fp->precision = 16; 528 fp->flags = 0; 529 break; 530 default: 531 return EINVAL; 532 } 533 return 0; 534 } 535 536 int 537 cs4280_set_params(addr, setmode, usemode, play, rec) 538 void *addr; 539 int setmode, usemode; 540 struct audio_params *play, *rec; 541 { 542 struct cs428x_softc *sc = addr; 543 struct audio_params *p; 544 int mode; 545 546 for (mode = AUMODE_RECORD; mode != -1; 547 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 548 if ((setmode & mode) == 0) 549 continue; 550 551 p = mode == AUMODE_PLAY ? play : rec; 552 553 if (p == play) { 554 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 555 p->sample_rate, p->precision, p->channels)); 556 /* play back data format may be 8- or 16-bit and 557 * either stereo or mono. 558 * playback rate may range from 8000Hz to 48000Hz 559 */ 560 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 561 (p->precision != 8 && p->precision != 16) || 562 (p->channels != 1 && p->channels != 2) ) { 563 return EINVAL; 564 } 565 } else { 566 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 567 p->sample_rate, p->precision, p->channels)); 568 /* capture data format must be 16bit stereo 569 * and sample rate range from 11025Hz to 48000Hz. 570 * 571 * XXX: it looks like to work with 8000Hz, 572 * although data sheets say lower limit is 573 * 11025 Hz. 574 */ 575 576 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 577 (p->precision != 8 && p->precision != 16) || 578 (p->channels != 1 && p->channels != 2) ) { 579 return EINVAL; 580 } 581 } 582 p->factor = 1; 583 p->sw_code = 0; 584 585 /* capturing data is slinear */ 586 switch (p->encoding) { 587 case AUDIO_ENCODING_SLINEAR_BE: 588 if (mode == AUMODE_RECORD) { 589 if (p->precision == 16) 590 p->sw_code = swap_bytes; 591 } 592 break; 593 case AUDIO_ENCODING_SLINEAR_LE: 594 break; 595 case AUDIO_ENCODING_ULINEAR_BE: 596 if (mode == AUMODE_RECORD) { 597 if (p->precision == 16) 598 p->sw_code = change_sign16_swap_bytes_le; 599 else 600 p->sw_code = change_sign8; 601 } 602 break; 603 case AUDIO_ENCODING_ULINEAR_LE: 604 if (mode == AUMODE_RECORD) { 605 if (p->precision == 16) 606 p->sw_code = change_sign16_le; 607 else 608 p->sw_code = change_sign8; 609 } 610 break; 611 case AUDIO_ENCODING_ULAW: 612 if (mode == AUMODE_PLAY) { 613 p->factor = 2; 614 p->sw_code = mulaw_to_slinear16_le; 615 } else { 616 p->sw_code = slinear8_to_mulaw; 617 } 618 break; 619 case AUDIO_ENCODING_ALAW: 620 if (mode == AUMODE_PLAY) { 621 p->factor = 2; 622 p->sw_code = alaw_to_slinear16_le; 623 } else { 624 p->sw_code = slinear8_to_alaw; 625 } 626 break; 627 default: 628 return EINVAL; 629 } 630 } 631 632 /* set sample rate */ 633 cs4280_set_dac_rate(sc, play->sample_rate); 634 cs4280_set_adc_rate(sc, rec->sample_rate); 635 return 0; 636 } 637 638 int 639 cs4280_halt_output(addr) 640 void *addr; 641 { 642 struct cs428x_softc *sc = addr; 643 u_int32_t mem; 644 645 mem = BA1READ4(sc, CS4280_PCTL); 646 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 647 #ifdef DIAGNOSTIC 648 sc->sc_prun = 0; 649 #endif 650 return 0; 651 } 652 653 int 654 cs4280_halt_input(addr) 655 void *addr; 656 { 657 struct cs428x_softc *sc = addr; 658 u_int32_t mem; 659 660 mem = BA1READ4(sc, CS4280_CCTL); 661 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 662 #ifdef DIAGNOSTIC 663 sc->sc_rrun = 0; 664 #endif 665 return 0; 666 } 667 668 int 669 cs4280_getdev(addr, retp) 670 void *addr; 671 struct audio_device *retp; 672 { 673 *retp = cs4280_device; 674 return 0; 675 } 676 677 int 678 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 679 void *addr; 680 void *start, *end; 681 int blksize; 682 void (*intr) __P((void *)); 683 void *arg; 684 struct audio_params *param; 685 { 686 struct cs428x_softc *sc = addr; 687 u_int32_t pfie, pctl, pdtc; 688 struct cs428x_dma *p; 689 690 #ifdef DIAGNOSTIC 691 if (sc->sc_prun) 692 printf("cs4280_trigger_output: already running\n"); 693 sc->sc_prun = 1; 694 #endif 695 696 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 697 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 698 sc->sc_pintr = intr; 699 sc->sc_parg = arg; 700 701 /* stop playback DMA */ 702 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 703 704 /* setup PDTC */ 705 pdtc = BA1READ4(sc, CS4280_PDTC); 706 pdtc &= ~PDTC_MASK; 707 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 708 BA1WRITE4(sc, CS4280_PDTC, pdtc); 709 710 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 711 param->precision, param->factor, param->channels, 712 param->encoding)); 713 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 714 ; 715 if (p == NULL) { 716 printf("cs4280_trigger_output: bad addr %p\n", start); 717 return EINVAL; 718 } 719 if (DMAADDR(p) % sc->dma_align != 0 ) { 720 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 721 "4kB align\n", DMAADDR(p)); 722 return EINVAL; 723 } 724 725 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 726 sc->sc_ps = (char *)start; 727 sc->sc_pe = (char *)end; 728 sc->sc_pdma = p; 729 sc->sc_pbuf = KERNADDR(p); 730 sc->sc_pi = 0; 731 sc->sc_pn = sc->sc_ps; 732 if (blksize >= sc->dma_size) { 733 sc->sc_pn = sc->sc_ps + sc->dma_size; 734 memcpy(sc->sc_pbuf, start, sc->dma_size); 735 ++sc->sc_pi; 736 } else { 737 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 738 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 739 } 740 741 /* initiate playback dma */ 742 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 743 744 /* set PFIE */ 745 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 746 747 if (param->precision * param->factor == 8) 748 pfie |= PFIE_8BIT; 749 if (param->channels == 1) 750 pfie |= PFIE_MONO; 751 752 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 753 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 754 pfie |= PFIE_SWAPPED; 755 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 756 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 757 pfie |= PFIE_UNSIGNED; 758 759 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 760 761 cs4280_set_dac_rate(sc, param->sample_rate); 762 763 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 764 pctl |= sc->pctl; 765 BA1WRITE4(sc, CS4280_PCTL, pctl); 766 return 0; 767 } 768 769 int 770 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 771 void *addr; 772 void *start, *end; 773 int blksize; 774 void (*intr) __P((void *)); 775 void *arg; 776 struct audio_params *param; 777 { 778 struct cs428x_softc *sc = addr; 779 u_int32_t cctl, cie; 780 struct cs428x_dma *p; 781 782 #ifdef DIAGNOSTIC 783 if (sc->sc_rrun) 784 printf("cs4280_trigger_input: already running\n"); 785 sc->sc_rrun = 1; 786 #endif 787 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 788 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 789 sc->sc_rintr = intr; 790 sc->sc_rarg = arg; 791 792 /* stop capture DMA */ 793 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 794 795 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 796 ; 797 if (p == NULL) { 798 printf("cs4280_trigger_input: bad addr %p\n", start); 799 return EINVAL; 800 } 801 if (DMAADDR(p) % sc->dma_align != 0) { 802 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 803 "4kB align\n", DMAADDR(p)); 804 return EINVAL; 805 } 806 807 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 808 sc->sc_rs = (char *)start; 809 sc->sc_re = (char *)end; 810 sc->sc_rdma = p; 811 sc->sc_rbuf = KERNADDR(p); 812 sc->sc_ri = 0; 813 sc->sc_rn = sc->sc_rs; 814 815 /* initiate capture dma */ 816 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 817 818 /* setup format information for internal converter */ 819 sc->sc_rparam = 0; 820 if (param->precision == 8) { 821 sc->sc_rparam += CF_8BIT; 822 sc->sc_rcount <<= 1; 823 } 824 if (param->channels == 1) { 825 sc->sc_rparam += CF_MONO; 826 sc->sc_rcount <<= 1; 827 } 828 829 /* set CIE */ 830 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 831 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 832 833 cs4280_set_adc_rate(sc, param->sample_rate); 834 835 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 836 cctl |= sc->cctl; 837 BA1WRITE4(sc, CS4280_CCTL, cctl); 838 return 0; 839 } 840 841 /* Power Hook */ 842 void 843 cs4280_power(why, v) 844 int why; 845 void *v; 846 { 847 struct cs428x_softc *sc = (struct cs428x_softc *)v; 848 849 DPRINTF(("%s: cs4280_power why=%d\n", 850 sc->sc_dev.dv_xname, why)); 851 switch (why) { 852 case PWR_SUSPEND: 853 case PWR_STANDBY: 854 sc->sc_suspend = why; 855 856 cs4280_halt_output(sc); 857 cs4280_halt_input(sc); 858 /* should I powerdown here ? */ 859 cs428x_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 860 break; 861 case PWR_RESUME: 862 if (sc->sc_suspend == PWR_RESUME) { 863 printf("cs4280_power: odd, resume without suspend.\n"); 864 sc->sc_suspend = why; 865 return; 866 } 867 sc->sc_suspend = why; 868 cs4280_init(sc, 0); 869 cs4280_reset_codec(sc); 870 871 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 872 break; 873 case PWR_SOFTSUSPEND: 874 case PWR_SOFTSTANDBY: 875 case PWR_SOFTRESUME: 876 break; 877 } 878 } 879 880 /* control AC97 codec */ 881 void 882 cs4280_reset_codec(void *addr) 883 { 884 struct cs428x_softc *sc; 885 int n; 886 887 sc = addr; 888 889 /* Reset codec */ 890 BA0WRITE4(sc, CS428X_ACCTL, 0); 891 delay(100); /* delay 100us */ 892 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 893 894 /* 895 * It looks like we do the following procedure, too 896 */ 897 898 /* Enable AC-link sync generation */ 899 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 900 delay(50*1000); /* XXX delay 50ms */ 901 902 /* Assert valid frame signal */ 903 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 904 905 /* Wait for valid AC97 input slot */ 906 n = 0; 907 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 908 (ACISV_ISV3 | ACISV_ISV4)) { 909 delay(1000); 910 if (++n > 1000) { 911 printf("reset_codec: AC97 inputs slot ready timeout\n"); 912 return; 913 } 914 } 915 } 916 917 918 /* Internal functions */ 919 920 void 921 cs4280_set_adc_rate(sc, rate) 922 struct cs428x_softc *sc; 923 int rate; 924 { 925 /* calculate capture rate: 926 * 927 * capture_coefficient_increment = -round(rate*128*65536/48000; 928 * capture_phase_increment = floor(48000*65536*1024/rate); 929 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 930 * cy = floor(cx/200); 931 * capture_sample_rate_correction = cx - 200*cy; 932 * capture_delay = ceil(24*48000/rate); 933 * capture_num_triplets = floor(65536*rate/24000); 934 * capture_group_length = 24000/GCD(rate, 24000); 935 * where GCD means "Greatest Common Divisor". 936 * 937 * capture_coefficient_increment, capture_phase_increment and 938 * capture_num_triplets are 32-bit signed quantities. 939 * capture_sample_rate_correction and capture_group_length are 940 * 16-bit signed quantities. 941 * capture_delay is a 14-bit unsigned quantity. 942 */ 943 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 944 u_int16_t csrc, cgl, cdlay; 945 946 /* XXX 947 * Even though, embedded_audio_spec says capture rate range 11025 to 948 * 48000, dhwiface.cpp says, 949 * 950 * "We can only decimate by up to a factor of 1/9th the hardware rate. 951 * Return an error if an attempt is made to stray outside that limit." 952 * 953 * so assume range as 48000/9 to 48000 954 */ 955 956 if (rate < 8000) 957 rate = 8000; 958 if (rate > 48000) 959 rate = 48000; 960 961 cx = rate << 16; 962 cci = cx / 48000; 963 cx -= cci * 48000; 964 cx <<= 7; 965 cci <<= 7; 966 cci += cx / 48000; 967 cci = - cci; 968 969 cx = 48000 << 16; 970 cpi = cx / rate; 971 cx -= cpi * rate; 972 cx <<= 10; 973 cpi <<= 10; 974 cy = cx / rate; 975 cpi += cy; 976 cx -= cy * rate; 977 978 cy = cx / 200; 979 csrc = cx - 200*cy; 980 981 cdlay = ((48000 * 24) + rate - 1) / rate; 982 #if 0 983 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 984 #endif 985 986 cnt = rate << 16; 987 cnt /= 24000; 988 989 cgl = 1; 990 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 991 if (((rate / tmp1) * tmp1) != rate) 992 cgl *= 2; 993 } 994 if (((rate / 3) * 3) != rate) 995 cgl *= 3; 996 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 997 if (((rate / tmp1) * tmp1) != rate) 998 cgl *= 5; 999 } 1000 #if 0 1001 /* XXX what manual says */ 1002 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1003 tmp1 |= csrc<<16; 1004 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1005 #else 1006 /* suggested by cs461x.c (ALSA driver) */ 1007 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1008 #endif 1009 1010 #if 0 1011 /* I am confused. The sample rate calculation section says 1012 * cci *is* 32-bit signed quantity but in the parameter description 1013 * section, CCI only assigned 16bit. 1014 * I believe size of the variable. 1015 */ 1016 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1017 tmp1 |= cci<<16; 1018 BA1WRITE4(sc, CS4280_CCI, tmp1); 1019 #else 1020 BA1WRITE4(sc, CS4280_CCI, cci); 1021 #endif 1022 1023 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1024 tmp1 |= cdlay <<18; 1025 BA1WRITE4(sc, CS4280_CD, tmp1); 1026 1027 BA1WRITE4(sc, CS4280_CPI, cpi); 1028 1029 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1030 tmp1 |= cgl; 1031 BA1WRITE4(sc, CS4280_CGL, tmp1); 1032 1033 BA1WRITE4(sc, CS4280_CNT, cnt); 1034 1035 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1036 tmp1 |= cgl; 1037 BA1WRITE4(sc, CS4280_CGC, tmp1); 1038 } 1039 1040 void 1041 cs4280_set_dac_rate(sc, rate) 1042 struct cs428x_softc *sc; 1043 int rate; 1044 { 1045 /* 1046 * playback rate may range from 8000Hz to 48000Hz 1047 * 1048 * play_phase_increment = floor(rate*65536*1024/48000) 1049 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1050 * py=floor(px/200) 1051 * play_sample_rate_correction = px - 200*py 1052 * 1053 * play_phase_increment is a 32bit signed quantity. 1054 * play_sample_rate_correction is a 16bit signed quantity. 1055 */ 1056 int32_t ppi; 1057 int16_t psrc; 1058 u_int32_t px, py; 1059 1060 if (rate < 8000) 1061 rate = 8000; 1062 if (rate > 48000) 1063 rate = 48000; 1064 px = rate << 16; 1065 ppi = px/48000; 1066 px -= ppi*48000; 1067 ppi <<= 10; 1068 px <<= 10; 1069 py = px / 48000; 1070 ppi += py; 1071 px -= py*48000; 1072 py = px/200; 1073 px -= py*200; 1074 psrc = px; 1075 #if 0 1076 /* what manual says */ 1077 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1078 BA1WRITE4(sc, CS4280_PSRC, 1079 ( ((psrc<<16) & PSRC_MASK) | px )); 1080 #else 1081 /* suggested by cs461x.c (ALSA driver) */ 1082 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1083 #endif 1084 BA1WRITE4(sc, CS4280_PPI, ppi); 1085 } 1086 1087 /* Download Proceessor Code and Data image */ 1088 int 1089 cs4280_download(sc, src, offset, len) 1090 struct cs428x_softc *sc; 1091 const u_int32_t *src; 1092 u_int32_t offset, len; 1093 { 1094 u_int32_t ctr; 1095 1096 #if CS4280_DEBUG > 10 1097 u_int32_t con, data; 1098 u_int8_t c0,c1,c2,c3; 1099 #endif 1100 if ((offset&3) || (len&3)) 1101 return -1; 1102 1103 len /= sizeof(u_int32_t); 1104 for (ctr = 0; ctr < len; ctr++) { 1105 /* XXX: 1106 * I cannot confirm this is the right thing or not 1107 * on BIG-ENDIAN machines. 1108 */ 1109 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1110 #if CS4280_DEBUG > 10 1111 data = htole32(*(src+ctr)); 1112 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1113 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1114 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1115 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1116 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1117 if (data != con ) { 1118 printf("0x%06x: write=0x%08x read=0x%08x\n", 1119 offset+ctr*4, data, con); 1120 return -1; 1121 } 1122 #endif 1123 } 1124 return 0; 1125 } 1126 1127 int 1128 cs4280_download_image(sc) 1129 struct cs428x_softc *sc; 1130 { 1131 int idx, err; 1132 u_int32_t offset = 0; 1133 1134 err = 0; 1135 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1136 err = cs4280_download(sc, &BA1Struct.map[offset], 1137 BA1Struct.memory[idx].offset, 1138 BA1Struct.memory[idx].size); 1139 if (err != 0) { 1140 printf("%s: load_image failed at %d\n", 1141 sc->sc_dev.dv_xname, idx); 1142 return -1; 1143 } 1144 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1145 } 1146 return err; 1147 } 1148 1149 /* Processor Soft Reset */ 1150 void 1151 cs4280_reset(sc_) 1152 void *sc_; 1153 { 1154 struct cs428x_softc *sc = sc_; 1155 1156 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1157 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1158 delay(100); 1159 /* Clear RSTSP bit in SPCR */ 1160 BA1WRITE4(sc, CS4280_SPCR, 0); 1161 /* enable DMA reqest */ 1162 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1163 } 1164 1165 int 1166 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1167 struct cs428x_softc *sc; 1168 char *class, *device, *qualifier; 1169 { 1170 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1171 device, qualifier)); 1172 } 1173 1174 int 1175 cs4280_init(sc, init) 1176 struct cs428x_softc *sc; 1177 int init; 1178 { 1179 int n; 1180 u_int32_t mem; 1181 1182 /* Start PLL out in known state */ 1183 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1184 /* Start serial ports out in known state */ 1185 BA0WRITE4(sc, CS4280_SERMC1, 0); 1186 1187 /* Specify type of CODEC */ 1188 /* XXX should not be here */ 1189 #define SERACC_CODEC_TYPE_1_03 1190 #ifdef SERACC_CODEC_TYPE_1_03 1191 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1192 #else 1193 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1194 #endif 1195 1196 /* Reset codec */ 1197 BA0WRITE4(sc, CS428X_ACCTL, 0); 1198 delay(100); /* delay 100us */ 1199 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1200 1201 /* Enable AC-link sync generation */ 1202 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1203 delay(50*1000); /* delay 50ms */ 1204 1205 /* Set the serial port timing configuration */ 1206 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1207 1208 /* Setup clock control */ 1209 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1210 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1211 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1212 1213 /* Power up the PLL */ 1214 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1215 delay(50*1000); /* delay 50ms */ 1216 1217 /* Turn on clock */ 1218 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1219 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1220 1221 /* Set the serial port FIFO pointer to the 1222 * first sample in FIFO. (not documented) */ 1223 cs4280_clear_fifos(sc); 1224 1225 #if 0 1226 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1227 BA0WRITE4(sc, CS4280_SERBSP, 0); 1228 #endif 1229 1230 /* Configure the serial port */ 1231 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1232 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1233 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1234 1235 /* Wait for CODEC ready */ 1236 n = 0; 1237 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1238 delay(125); 1239 if (++n > 1000) { 1240 printf("%s: codec ready timeout\n", 1241 sc->sc_dev.dv_xname); 1242 return(1); 1243 } 1244 } 1245 1246 /* Assert valid frame signal */ 1247 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1248 1249 /* Wait for valid AC97 input slot */ 1250 n = 0; 1251 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1252 (ACISV_ISV3 | ACISV_ISV4)) { 1253 delay(1000); 1254 if (++n > 1000) { 1255 printf("AC97 inputs slot ready timeout\n"); 1256 return(1); 1257 } 1258 } 1259 1260 /* Set AC97 output slot valid signals */ 1261 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1262 1263 /* reset the processor */ 1264 cs4280_reset(sc); 1265 1266 /* Download the image to the processor */ 1267 if (cs4280_download_image(sc) != 0) { 1268 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1269 return(1); 1270 } 1271 1272 /* Save playback parameter and then write zero. 1273 * this ensures that DMA doesn't immediately occur upon 1274 * starting the processor core 1275 */ 1276 mem = BA1READ4(sc, CS4280_PCTL); 1277 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1278 cs4280_halt_output(sc); 1279 1280 /* Save capture parameter and then write zero. 1281 * this ensures that DMA doesn't immediately occur upon 1282 * starting the processor core 1283 */ 1284 mem = BA1READ4(sc, CS4280_CCTL); 1285 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1286 cs4280_halt_input(sc); 1287 1288 /* Processor Startup Procedure */ 1289 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1290 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1291 1292 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1293 n = 0; 1294 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1295 delay(10); 1296 if (++n > 1000) { 1297 printf("SPCR 1->0 transition timeout\n"); 1298 return(1); 1299 } 1300 } 1301 1302 n = 0; 1303 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1304 delay(10); 1305 if (++n > 1000) { 1306 printf("SPCS 0->1 transition timeout\n"); 1307 return(1); 1308 } 1309 } 1310 /* Processor is now running !!! */ 1311 1312 /* Setup volume */ 1313 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1314 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1315 1316 /* Interrupt enable */ 1317 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1318 1319 /* playback interrupt enable */ 1320 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1321 mem |= PFIE_PI_ENABLE; 1322 BA1WRITE4(sc, CS4280_PFIE, mem); 1323 /* capture interrupt enable */ 1324 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1325 mem |= CIE_CI_ENABLE; 1326 BA1WRITE4(sc, CS4280_CIE, mem); 1327 1328 #if NMIDI > 0 1329 /* Reset midi port */ 1330 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1331 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1332 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1333 /* midi interrupt enable */ 1334 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1335 BA0WRITE4(sc, CS4280_MIDCR, mem); 1336 #endif 1337 return(0); 1338 } 1339 1340 void 1341 cs4280_clear_fifos(sc) 1342 struct cs428x_softc *sc; 1343 { 1344 int pd = 0, cnt, n; 1345 u_int32_t mem; 1346 1347 /* 1348 * If device power down, power up the device and keep power down 1349 * state. 1350 */ 1351 mem = BA0READ4(sc, CS4280_CLKCR1); 1352 if (!(mem & CLKCR1_SWCE)) { 1353 printf("cs4280_clear_fifo: power down found.\n"); 1354 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1355 pd = 1; 1356 } 1357 BA0WRITE4(sc, CS4280_SERBWP, 0); 1358 for (cnt = 0; cnt < 256; cnt++) { 1359 n = 0; 1360 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1361 delay(1000); 1362 if (++n > 1000) { 1363 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1364 break; 1365 } 1366 } 1367 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1368 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1369 } 1370 if (pd) 1371 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1372 } 1373 1374 #if NMIDI > 0 1375 int 1376 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1377 void *addr; 1378 int flags; 1379 void (*iintr)__P((void *, int)); 1380 void (*ointr)__P((void *)); 1381 void *arg; 1382 { 1383 struct cs428x_softc *sc = addr; 1384 u_int32_t mem; 1385 1386 DPRINTF(("midi_open\n")); 1387 sc->sc_iintr = iintr; 1388 sc->sc_ointr = ointr; 1389 sc->sc_arg = arg; 1390 1391 /* midi interrupt enable */ 1392 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1393 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1394 BA0WRITE4(sc, CS4280_MIDCR, mem); 1395 #ifdef CS4280_DEBUG 1396 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1397 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1398 return(EINVAL); 1399 } 1400 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1401 #endif 1402 return 0; 1403 } 1404 1405 void 1406 cs4280_midi_close(addr) 1407 void *addr; 1408 { 1409 struct cs428x_softc *sc = addr; 1410 u_int32_t mem; 1411 1412 DPRINTF(("midi_close\n")); 1413 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1414 mem = BA0READ4(sc, CS4280_MIDCR); 1415 mem &= ~MIDCR_MASK; 1416 BA0WRITE4(sc, CS4280_MIDCR, mem); 1417 1418 sc->sc_iintr = 0; 1419 sc->sc_ointr = 0; 1420 } 1421 1422 int 1423 cs4280_midi_output(addr, d) 1424 void *addr; 1425 int d; 1426 { 1427 struct cs428x_softc *sc = addr; 1428 u_int32_t mem; 1429 int x; 1430 1431 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1432 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1433 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1434 mem |= d & MIDWP_MASK; 1435 DPRINTFN(5,("midi_output d=0x%08x",d)); 1436 BA0WRITE4(sc, CS4280_MIDWP, mem); 1437 #ifdef DIAGNOSTIC 1438 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1439 DPRINTF(("Bad write data: %d %d", 1440 mem, BA0READ4(sc, CS4280_MIDWP))); 1441 return(EIO); 1442 } 1443 #endif 1444 return 0; 1445 } 1446 delay(MIDI_BUSY_DELAY); 1447 } 1448 return (EIO); 1449 } 1450 1451 void 1452 cs4280_midi_getinfo(addr, mi) 1453 void *addr; 1454 struct midi_info *mi; 1455 { 1456 mi->name = "CS4280 MIDI UART"; 1457 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1458 } 1459 1460 #endif 1461 1462 /* DEBUG functions */ 1463 #if CS4280_DEBUG > 10 1464 int 1465 cs4280_checkimage(sc, src, offset, len) 1466 struct cs428x_softc *sc; 1467 u_int32_t *src; 1468 u_int32_t offset, len; 1469 { 1470 u_int32_t ctr, data; 1471 int err = 0; 1472 1473 if ((offset&3) || (len&3)) 1474 return -1; 1475 1476 len /= sizeof(u_int32_t); 1477 for (ctr = 0; ctr < len; ctr++) { 1478 /* I cannot confirm this is the right thing 1479 * on BIG-ENDIAN machines 1480 */ 1481 data = BA1READ4(sc, offset+ctr*4); 1482 if (data != htole32(*(src+ctr))) { 1483 printf("0x%06x: 0x%08x(0x%08x)\n", 1484 offset+ctr*4, data, *(src+ctr)); 1485 *(src+ctr) = data; 1486 ++err; 1487 } 1488 } 1489 return err; 1490 } 1491 1492 int 1493 cs4280_check_images(sc) 1494 struct cs428x_softc *sc; 1495 { 1496 int idx, err; 1497 u_int32_t offset = 0; 1498 1499 err = 0; 1500 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1501 for (idx = 0; idx < 1; ++idx) { 1502 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1503 BA1Struct.memory[idx].offset, 1504 BA1Struct.memory[idx].size); 1505 if (err != 0) { 1506 printf("%s: check_image failed at %d\n", 1507 sc->sc_dev.dv_xname, idx); 1508 } 1509 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1510 } 1511 return err; 1512 } 1513 1514 #endif 1515
Indexes created Thu Oct 02 14:10:14 GMT 2025