cs4280.c revision 1.7.2.7
1 /* $NetBSD: cs4280.c,v 1.7.2.7 2001/03/12 13:31:05 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include "midi.h" 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/fcntl.h> 60 #include <sys/malloc.h> 61 #include <sys/device.h> 62 #include <sys/proc.h> 63 #include <sys/types.h> 64 #include <sys/systm.h> 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/cs4280reg.h> 69 #include <dev/pci/cs4280_image.h> 70 #include <dev/pci/cs428xreg.h> 71 72 #include <sys/audioio.h> 73 #include <dev/audio_if.h> 74 #include <dev/midi_if.h> 75 #include <dev/mulaw.h> 76 #include <dev/auconv.h> 77 78 #include <dev/ic/ac97reg.h> 79 #include <dev/ic/ac97var.h> 80 81 #include <dev/pci/cs428x.h> 82 83 #include <machine/bus.h> 84 #include <machine/bswap.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 int cs4280_match(struct device *, struct cfdata *, void *); 91 void cs4280_attach(struct device *, struct device *, void *); 92 int cs4280_intr(void *); 93 int cs4280_query_encoding(void *, struct audio_encoding *); 94 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 95 int cs4280_halt_output(void *); 96 int cs4280_halt_input(void *); 97 int cs4280_getdev(void *, struct audio_device *); 98 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 99 void *, struct audio_params *); 100 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 101 void *, struct audio_params *); 102 103 void cs4280_reset_codec(void *); 104 105 /* For PowerHook */ 106 void cs4280_power(int, void *); 107 108 /* Internal functions */ 109 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 110 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 111 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 112 int cs4280_download_image(struct cs428x_softc *); 113 void cs4280_reset(void *); 114 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 115 int cs4280_init(struct cs428x_softc *, int); 116 void cs4280_clear_fifos(struct cs428x_softc *); 117 118 #if CS4280_DEBUG > 10 119 /* Thease two function is only for checking image loading is succeeded or not. */ 120 int cs4280_check_images(struct cs428x_softc *); 121 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 122 #endif 123 124 struct audio_hw_if cs4280_hw_if = { 125 cs428x_open, 126 cs428x_close, 127 NULL, 128 cs4280_query_encoding, 129 cs4280_set_params, 130 cs428x_round_blocksize, 131 NULL, 132 NULL, 133 NULL, 134 NULL, 135 NULL, 136 cs4280_halt_output, 137 cs4280_halt_input, 138 NULL, 139 cs4280_getdev, 140 NULL, 141 cs428x_mixer_set_port, 142 cs428x_mixer_get_port, 143 cs428x_query_devinfo, 144 cs428x_malloc, 145 cs428x_free, 146 cs428x_round_buffersize, 147 cs428x_mappage, 148 cs428x_get_props, 149 cs4280_trigger_output, 150 cs4280_trigger_input, 151 }; 152 153 #if NMIDI > 0 154 /* Midi Interface */ 155 int cs4280_midi_open(void *, int, void (*)(void *, int), 156 void (*)(void *), void *); 157 void cs4280_midi_close(void*); 158 int cs4280_midi_output(void *, int); 159 void cs4280_midi_getinfo(void *, struct midi_info *); 160 161 struct midi_hw_if cs4280_midi_hw_if = { 162 cs4280_midi_open, 163 cs4280_midi_close, 164 cs4280_midi_output, 165 cs4280_midi_getinfo, 166 0, 167 }; 168 #endif 169 170 struct cfattach clcs_ca = { 171 sizeof(struct cs428x_softc), cs4280_match, cs4280_attach 172 }; 173 174 struct audio_device cs4280_device = { 175 "CS4280", 176 "", 177 "cs4280" 178 }; 179 180 181 int 182 cs4280_match(parent, match, aux) 183 struct device *parent; 184 struct cfdata *match; 185 void *aux; 186 { 187 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 188 189 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 190 return 0; 191 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 192 #if 0 /* I can't confirm */ 193 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 194 #endif 195 ) 196 return 1; 197 return 0; 198 } 199 200 void 201 cs4280_attach(parent, self, aux) 202 struct device *parent; 203 struct device *self; 204 void *aux; 205 { 206 struct cs428x_softc *sc = (struct cs428x_softc *)self; 207 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 208 pci_chipset_tag_t pc = pa->pa_pc; 209 char const *intrstr; 210 pci_intr_handle_t ih; 211 pcireg_t reg; 212 char devinfo[256]; 213 mixer_ctrl_t ctl; 214 u_int32_t mem; 215 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 216 217 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 218 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 219 220 /* Map I/O register */ 221 if (pci_mapreg_map(pa, PCI_BA0, 222 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 223 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 224 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 225 return; 226 } 227 if (pci_mapreg_map(pa, PCI_BA1, 228 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 229 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 230 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 231 return; 232 } 233 234 sc->sc_dmatag = pa->pa_dmat; 235 236 /* Check and set Power State */ 237 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 238 &pci_pwrmgmt_cap_reg, 0)) { 239 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 240 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 241 pci_pwrmgmt_csr_reg); 242 DPRINTF(("%s: Power State is %d\n", 243 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 244 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 245 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 246 (reg & ~PCI_PMCSR_STATE_MASK) | 247 PCI_PMCSR_STATE_D0); 248 } 249 } 250 251 /* Enable the device (set bus master flag) */ 252 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 253 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 254 reg | PCI_COMMAND_MASTER_ENABLE); 255 256 /* LATENCY_TIMER setting */ 257 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 258 if ( PCI_LATTIMER(mem) < 32 ) { 259 mem &= 0xffff00ff; 260 mem |= 0x00002000; 261 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 262 } 263 264 /* Map and establish the interrupt. */ 265 if (pci_intr_map(pa, &ih)) { 266 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 267 return; 268 } 269 intrstr = pci_intr_string(pc, ih); 270 271 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 272 if (sc->sc_ih == NULL) { 273 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 274 if (intrstr != NULL) 275 printf(" at %s", intrstr); 276 printf("\n"); 277 return; 278 } 279 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 280 281 /* Initialization */ 282 if(cs4280_init(sc, 1) != 0) 283 return; 284 285 sc->type = TYPE_CS4280; 286 sc->halt_input = cs4280_halt_input; 287 sc->halt_output = cs4280_halt_output; 288 289 /* setup buffer related parameters */ 290 sc->dma_size = CS4280_DCHUNK; 291 sc->dma_align = CS4280_DALIGN; 292 sc->hw_blocksize = CS4280_ICHUNK; 293 294 /* AC 97 attachment */ 295 sc->host_if.arg = sc; 296 sc->host_if.attach = cs428x_attach_codec; 297 sc->host_if.read = cs428x_read_codec; 298 sc->host_if.write = cs428x_write_codec; 299 sc->host_if.reset = cs4280_reset_codec; 300 if (ac97_attach(&sc->host_if) != 0) { 301 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 302 return; 303 } 304 305 /* Turn mute off of DAC, CD and master volumes by default */ 306 ctl.type = AUDIO_MIXER_ENUM; 307 ctl.un.ord = 0; /* off */ 308 309 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 310 AudioNmaster, AudioNmute); 311 cs428x_mixer_set_port(sc, &ctl); 312 313 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 314 AudioNdac, AudioNmute); 315 cs428x_mixer_set_port(sc, &ctl); 316 317 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 318 AudioNcd, AudioNmute); 319 cs428x_mixer_set_port(sc, &ctl); 320 321 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 322 323 #if NMIDI > 0 324 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 325 #endif 326 327 sc->sc_suspend = PWR_RESUME; 328 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 329 } 330 331 /* Interrupt handling function */ 332 int 333 cs4280_intr(p) 334 void *p; 335 { 336 /* 337 * XXX 338 * 339 * Since CS4280 has only 4kB dma buffer and 340 * interrupt occurs every 2kB block, I create dummy buffer 341 * which returns to audio driver and actual dma buffer 342 * using in DMA transfer. 343 * 344 * 345 * ring buffer in audio.c is pointed by BUFADDR 346 * <------ ring buffer size == 64kB ------> 347 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 348 * |= = = =|= = = =|= = = =|= = = =|= = = =| 349 * | | | | | | <- call audio_intp every 350 * sc->sc_[pr]_count time. 351 * 352 * actual dma buffer is pointed by KERNADDR 353 * <-> dma buffer size = 4kB 354 * |= =| 355 * 356 * 357 */ 358 struct cs428x_softc *sc = p; 359 u_int32_t intr, mem; 360 char * empty_dma; 361 int handled = 0; 362 363 /* grab interrupt register then clear it */ 364 intr = BA0READ4(sc, CS4280_HISR); 365 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 366 367 /* Playback Interrupt */ 368 if (intr & HISR_PINT) { 369 handled = 1; 370 mem = BA1READ4(sc, CS4280_PFIE); 371 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 372 if (sc->sc_pintr) { 373 if ((sc->sc_pi%sc->sc_pcount) == 0) 374 sc->sc_pintr(sc->sc_parg); 375 } else { 376 printf("unexpected play intr\n"); 377 } 378 /* copy buffer */ 379 ++sc->sc_pi; 380 empty_dma = sc->sc_pdma->addr; 381 if (sc->sc_pi&1) 382 empty_dma += sc->hw_blocksize; 383 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 384 sc->sc_pn += sc->hw_blocksize; 385 if (sc->sc_pn >= sc->sc_pe) 386 sc->sc_pn = sc->sc_ps; 387 BA1WRITE4(sc, CS4280_PFIE, mem); 388 } 389 /* Capture Interrupt */ 390 if (intr & HISR_CINT) { 391 int i; 392 int16_t rdata; 393 394 handled = 1; 395 mem = BA1READ4(sc, CS4280_CIE); 396 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 397 ++sc->sc_ri; 398 empty_dma = sc->sc_rdma->addr; 399 if ((sc->sc_ri&1) == 0) 400 empty_dma += sc->hw_blocksize; 401 402 /* 403 * XXX 404 * I think this audio data conversion should be 405 * happend in upper layer, but I put this here 406 * since there is no conversion function available. 407 */ 408 switch(sc->sc_rparam) { 409 case CF_16BIT_STEREO: 410 /* just copy it */ 411 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 412 sc->sc_rn += sc->hw_blocksize; 413 break; 414 case CF_16BIT_MONO: 415 for (i = 0; i < 512; i++) { 416 rdata = *((int16_t *)empty_dma)++>>1; 417 rdata += *((int16_t *)empty_dma)++>>1; 418 *((int16_t *)sc->sc_rn)++ = rdata; 419 } 420 break; 421 case CF_8BIT_STEREO: 422 for (i = 0; i < 512; i++) { 423 rdata = *((int16_t*)empty_dma)++; 424 *sc->sc_rn++ = rdata >> 8; 425 rdata = *((int16_t*)empty_dma)++; 426 *sc->sc_rn++ = rdata >> 8; 427 } 428 break; 429 case CF_8BIT_MONO: 430 for (i = 0; i < 512; i++) { 431 rdata = *((int16_t*)empty_dma)++ >>1; 432 rdata += *((int16_t*)empty_dma)++ >>1; 433 *sc->sc_rn++ = rdata >>8; 434 } 435 break; 436 default: 437 /* Should not reach here */ 438 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 439 } 440 if (sc->sc_rn >= sc->sc_re) 441 sc->sc_rn = sc->sc_rs; 442 BA1WRITE4(sc, CS4280_CIE, mem); 443 if (sc->sc_rintr) { 444 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 445 sc->sc_rintr(sc->sc_rarg); 446 } else { 447 printf("unexpected record intr\n"); 448 } 449 } 450 451 #if NMIDI > 0 452 /* Midi port Interrupt */ 453 if (intr & HISR_MIDI) { 454 int data; 455 456 handled = 1; 457 DPRINTF(("i: %d: ", 458 BA0READ4(sc, CS4280_MIDSR))); 459 /* Read the received data */ 460 while ((sc->sc_iintr != NULL) && 461 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 462 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 463 DPRINTF(("r:%x\n",data)); 464 sc->sc_iintr(sc->sc_arg, data); 465 } 466 467 /* Write the data */ 468 #if 1 469 /* XXX: 470 * It seems "Transmit Buffer Full" never activate until EOI 471 * is deliverd. Shall I throw EOI top of this routine ? 472 */ 473 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 474 DPRINTF(("w: ")); 475 if (sc->sc_ointr != NULL) 476 sc->sc_ointr(sc->sc_arg); 477 } 478 #else 479 while ((sc->sc_ointr != NULL) && 480 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 481 DPRINTF(("w: ")); 482 sc->sc_ointr(sc->sc_arg); 483 } 484 #endif 485 DPRINTF(("\n")); 486 } 487 #endif 488 489 return handled; 490 } 491 492 int 493 cs4280_query_encoding(addr, fp) 494 void *addr; 495 struct audio_encoding *fp; 496 { 497 switch (fp->index) { 498 case 0: 499 strcpy(fp->name, AudioEulinear); 500 fp->encoding = AUDIO_ENCODING_ULINEAR; 501 fp->precision = 8; 502 fp->flags = 0; 503 break; 504 case 1: 505 strcpy(fp->name, AudioEmulaw); 506 fp->encoding = AUDIO_ENCODING_ULAW; 507 fp->precision = 8; 508 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 509 break; 510 case 2: 511 strcpy(fp->name, AudioEalaw); 512 fp->encoding = AUDIO_ENCODING_ALAW; 513 fp->precision = 8; 514 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 515 break; 516 case 3: 517 strcpy(fp->name, AudioEslinear); 518 fp->encoding = AUDIO_ENCODING_SLINEAR; 519 fp->precision = 8; 520 fp->flags = 0; 521 break; 522 case 4: 523 strcpy(fp->name, AudioEslinear_le); 524 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 525 fp->precision = 16; 526 fp->flags = 0; 527 break; 528 case 5: 529 strcpy(fp->name, AudioEulinear_le); 530 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 531 fp->precision = 16; 532 fp->flags = 0; 533 break; 534 case 6: 535 strcpy(fp->name, AudioEslinear_be); 536 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 537 fp->precision = 16; 538 fp->flags = 0; 539 break; 540 case 7: 541 strcpy(fp->name, AudioEulinear_be); 542 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 543 fp->precision = 16; 544 fp->flags = 0; 545 break; 546 default: 547 return EINVAL; 548 } 549 return 0; 550 } 551 552 int 553 cs4280_set_params(addr, setmode, usemode, play, rec) 554 void *addr; 555 int setmode, usemode; 556 struct audio_params *play, *rec; 557 { 558 struct cs428x_softc *sc = addr; 559 struct audio_params *p; 560 int mode; 561 562 for (mode = AUMODE_RECORD; mode != -1; 563 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 564 if ((setmode & mode) == 0) 565 continue; 566 567 p = mode == AUMODE_PLAY ? play : rec; 568 569 if (p == play) { 570 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 571 p->sample_rate, p->precision, p->channels)); 572 /* play back data format may be 8- or 16-bit and 573 * either stereo or mono. 574 * playback rate may range from 8000Hz to 48000Hz 575 */ 576 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 577 (p->precision != 8 && p->precision != 16) || 578 (p->channels != 1 && p->channels != 2) ) { 579 return EINVAL; 580 } 581 } else { 582 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 583 p->sample_rate, p->precision, p->channels)); 584 /* capture data format must be 16bit stereo 585 * and sample rate range from 11025Hz to 48000Hz. 586 * 587 * XXX: it looks like to work with 8000Hz, 588 * although data sheets say lower limit is 589 * 11025 Hz. 590 */ 591 592 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 593 (p->precision != 8 && p->precision != 16) || 594 (p->channels != 1 && p->channels != 2) ) { 595 return EINVAL; 596 } 597 } 598 p->factor = 1; 599 p->sw_code = 0; 600 601 /* capturing data is slinear */ 602 switch (p->encoding) { 603 case AUDIO_ENCODING_SLINEAR_BE: 604 if (mode == AUMODE_RECORD) { 605 if (p->precision == 16) 606 p->sw_code = swap_bytes; 607 } 608 break; 609 case AUDIO_ENCODING_SLINEAR_LE: 610 break; 611 case AUDIO_ENCODING_ULINEAR_BE: 612 if (mode == AUMODE_RECORD) { 613 if (p->precision == 16) 614 p->sw_code = change_sign16_swap_bytes_le; 615 else 616 p->sw_code = change_sign8; 617 } 618 break; 619 case AUDIO_ENCODING_ULINEAR_LE: 620 if (mode == AUMODE_RECORD) { 621 if (p->precision == 16) 622 p->sw_code = change_sign16_le; 623 else 624 p->sw_code = change_sign8; 625 } 626 break; 627 case AUDIO_ENCODING_ULAW: 628 if (mode == AUMODE_PLAY) { 629 p->factor = 2; 630 p->sw_code = mulaw_to_slinear16_le; 631 } else { 632 p->sw_code = slinear8_to_mulaw; 633 } 634 break; 635 case AUDIO_ENCODING_ALAW: 636 if (mode == AUMODE_PLAY) { 637 p->factor = 2; 638 p->sw_code = alaw_to_slinear16_le; 639 } else { 640 p->sw_code = slinear8_to_alaw; 641 } 642 break; 643 default: 644 return EINVAL; 645 } 646 } 647 648 /* set sample rate */ 649 cs4280_set_dac_rate(sc, play->sample_rate); 650 cs4280_set_adc_rate(sc, rec->sample_rate); 651 return 0; 652 } 653 654 int 655 cs4280_halt_output(addr) 656 void *addr; 657 { 658 struct cs428x_softc *sc = addr; 659 u_int32_t mem; 660 661 mem = BA1READ4(sc, CS4280_PCTL); 662 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 663 #ifdef DIAGNOSTIC 664 sc->sc_prun = 0; 665 #endif 666 return 0; 667 } 668 669 int 670 cs4280_halt_input(addr) 671 void *addr; 672 { 673 struct cs428x_softc *sc = addr; 674 u_int32_t mem; 675 676 mem = BA1READ4(sc, CS4280_CCTL); 677 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 678 #ifdef DIAGNOSTIC 679 sc->sc_rrun = 0; 680 #endif 681 return 0; 682 } 683 684 int 685 cs4280_getdev(addr, retp) 686 void *addr; 687 struct audio_device *retp; 688 { 689 *retp = cs4280_device; 690 return 0; 691 } 692 693 int 694 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 695 void *addr; 696 void *start, *end; 697 int blksize; 698 void (*intr) __P((void *)); 699 void *arg; 700 struct audio_params *param; 701 { 702 struct cs428x_softc *sc = addr; 703 u_int32_t pfie, pctl, pdtc; 704 struct cs428x_dma *p; 705 706 #ifdef DIAGNOSTIC 707 if (sc->sc_prun) 708 printf("cs4280_trigger_output: already running\n"); 709 sc->sc_prun = 1; 710 #endif 711 712 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 713 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 714 sc->sc_pintr = intr; 715 sc->sc_parg = arg; 716 717 /* stop playback DMA */ 718 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 719 720 /* setup PDTC */ 721 pdtc = BA1READ4(sc, CS4280_PDTC); 722 pdtc &= ~PDTC_MASK; 723 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 724 BA1WRITE4(sc, CS4280_PDTC, pdtc); 725 726 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 727 param->precision, param->factor, param->channels, 728 param->encoding)); 729 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 730 ; 731 if (p == NULL) { 732 printf("cs4280_trigger_output: bad addr %p\n", start); 733 return EINVAL; 734 } 735 if (DMAADDR(p) % sc->dma_align != 0 ) { 736 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 737 "4kB align\n", DMAADDR(p)); 738 return EINVAL; 739 } 740 741 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 742 sc->sc_ps = (char *)start; 743 sc->sc_pe = (char *)end; 744 sc->sc_pdma = p; 745 sc->sc_pbuf = KERNADDR(p); 746 sc->sc_pi = 0; 747 sc->sc_pn = sc->sc_ps; 748 if (blksize >= sc->dma_size) { 749 sc->sc_pn = sc->sc_ps + sc->dma_size; 750 memcpy(sc->sc_pbuf, start, sc->dma_size); 751 ++sc->sc_pi; 752 } else { 753 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 754 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 755 } 756 757 /* initiate playback dma */ 758 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 759 760 /* set PFIE */ 761 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 762 763 if (param->precision * param->factor == 8) 764 pfie |= PFIE_8BIT; 765 if (param->channels == 1) 766 pfie |= PFIE_MONO; 767 768 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 769 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 770 pfie |= PFIE_SWAPPED; 771 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 772 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 773 pfie |= PFIE_UNSIGNED; 774 775 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 776 777 cs4280_set_dac_rate(sc, param->sample_rate); 778 779 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 780 pctl |= sc->pctl; 781 BA1WRITE4(sc, CS4280_PCTL, pctl); 782 return 0; 783 } 784 785 int 786 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 787 void *addr; 788 void *start, *end; 789 int blksize; 790 void (*intr) __P((void *)); 791 void *arg; 792 struct audio_params *param; 793 { 794 struct cs428x_softc *sc = addr; 795 u_int32_t cctl, cie; 796 struct cs428x_dma *p; 797 798 #ifdef DIAGNOSTIC 799 if (sc->sc_rrun) 800 printf("cs4280_trigger_input: already running\n"); 801 sc->sc_rrun = 1; 802 #endif 803 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 804 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 805 sc->sc_rintr = intr; 806 sc->sc_rarg = arg; 807 808 /* stop capture DMA */ 809 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 810 811 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 812 ; 813 if (p == NULL) { 814 printf("cs4280_trigger_input: bad addr %p\n", start); 815 return EINVAL; 816 } 817 if (DMAADDR(p) % sc->dma_align != 0) { 818 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 819 "4kB align\n", DMAADDR(p)); 820 return EINVAL; 821 } 822 823 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 824 sc->sc_rs = (char *)start; 825 sc->sc_re = (char *)end; 826 sc->sc_rdma = p; 827 sc->sc_rbuf = KERNADDR(p); 828 sc->sc_ri = 0; 829 sc->sc_rn = sc->sc_rs; 830 831 /* initiate capture dma */ 832 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 833 834 /* setup format information for internal converter */ 835 sc->sc_rparam = 0; 836 if (param->precision == 8) { 837 sc->sc_rparam += CF_8BIT; 838 sc->sc_rcount <<= 1; 839 } 840 if (param->channels == 1) { 841 sc->sc_rparam += CF_MONO; 842 sc->sc_rcount <<= 1; 843 } 844 845 /* set CIE */ 846 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 847 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 848 849 cs4280_set_adc_rate(sc, param->sample_rate); 850 851 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 852 cctl |= sc->cctl; 853 BA1WRITE4(sc, CS4280_CCTL, cctl); 854 return 0; 855 } 856 857 /* Power Hook */ 858 void 859 cs4280_power(why, v) 860 int why; 861 void *v; 862 { 863 struct cs428x_softc *sc = (struct cs428x_softc *)v; 864 865 DPRINTF(("%s: cs4280_power why=%d\n", 866 sc->sc_dev.dv_xname, why)); 867 switch (why) { 868 case PWR_SUSPEND: 869 case PWR_STANDBY: 870 sc->sc_suspend = why; 871 872 cs4280_halt_output(sc); 873 cs4280_halt_input(sc); 874 /* should I powerdown here ? */ 875 cs428x_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 876 break; 877 case PWR_RESUME: 878 if (sc->sc_suspend == PWR_RESUME) { 879 printf("cs4280_power: odd, resume without suspend.\n"); 880 sc->sc_suspend = why; 881 return; 882 } 883 sc->sc_suspend = why; 884 cs4280_init(sc, 0); 885 cs4280_reset_codec(sc); 886 887 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 888 break; 889 case PWR_SOFTSUSPEND: 890 case PWR_SOFTSTANDBY: 891 case PWR_SOFTRESUME: 892 break; 893 } 894 } 895 896 /* control AC97 codec */ 897 void 898 cs4280_reset_codec(void *addr) 899 { 900 struct cs428x_softc *sc; 901 int n; 902 903 sc = addr; 904 905 /* Reset codec */ 906 BA0WRITE4(sc, CS428X_ACCTL, 0); 907 delay(100); /* delay 100us */ 908 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 909 910 /* 911 * It looks like we do the following procedure, too 912 */ 913 914 /* Enable AC-link sync generation */ 915 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 916 delay(50*1000); /* XXX delay 50ms */ 917 918 /* Assert valid frame signal */ 919 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 920 921 /* Wait for valid AC97 input slot */ 922 n = 0; 923 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 924 (ACISV_ISV3 | ACISV_ISV4)) { 925 delay(1000); 926 if (++n > 1000) { 927 printf("reset_codec: AC97 inputs slot ready timeout\n"); 928 return; 929 } 930 } 931 } 932 933 934 /* Internal functions */ 935 936 void 937 cs4280_set_adc_rate(sc, rate) 938 struct cs428x_softc *sc; 939 int rate; 940 { 941 /* calculate capture rate: 942 * 943 * capture_coefficient_increment = -round(rate*128*65536/48000; 944 * capture_phase_increment = floor(48000*65536*1024/rate); 945 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 946 * cy = floor(cx/200); 947 * capture_sample_rate_correction = cx - 200*cy; 948 * capture_delay = ceil(24*48000/rate); 949 * capture_num_triplets = floor(65536*rate/24000); 950 * capture_group_length = 24000/GCD(rate, 24000); 951 * where GCD means "Greatest Common Divisor". 952 * 953 * capture_coefficient_increment, capture_phase_increment and 954 * capture_num_triplets are 32-bit signed quantities. 955 * capture_sample_rate_correction and capture_group_length are 956 * 16-bit signed quantities. 957 * capture_delay is a 14-bit unsigned quantity. 958 */ 959 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 960 u_int16_t csrc, cgl, cdlay; 961 962 /* XXX 963 * Even though, embedded_audio_spec says capture rate range 11025 to 964 * 48000, dhwiface.cpp says, 965 * 966 * "We can only decimate by up to a factor of 1/9th the hardware rate. 967 * Return an error if an attempt is made to stray outside that limit." 968 * 969 * so assume range as 48000/9 to 48000 970 */ 971 972 if (rate < 8000) 973 rate = 8000; 974 if (rate > 48000) 975 rate = 48000; 976 977 cx = rate << 16; 978 cci = cx / 48000; 979 cx -= cci * 48000; 980 cx <<= 7; 981 cci <<= 7; 982 cci += cx / 48000; 983 cci = - cci; 984 985 cx = 48000 << 16; 986 cpi = cx / rate; 987 cx -= cpi * rate; 988 cx <<= 10; 989 cpi <<= 10; 990 cy = cx / rate; 991 cpi += cy; 992 cx -= cy * rate; 993 994 cy = cx / 200; 995 csrc = cx - 200*cy; 996 997 cdlay = ((48000 * 24) + rate - 1) / rate; 998 #if 0 999 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1000 #endif 1001 1002 cnt = rate << 16; 1003 cnt /= 24000; 1004 1005 cgl = 1; 1006 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1007 if (((rate / tmp1) * tmp1) != rate) 1008 cgl *= 2; 1009 } 1010 if (((rate / 3) * 3) != rate) 1011 cgl *= 3; 1012 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1013 if (((rate / tmp1) * tmp1) != rate) 1014 cgl *= 5; 1015 } 1016 #if 0 1017 /* XXX what manual says */ 1018 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1019 tmp1 |= csrc<<16; 1020 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1021 #else 1022 /* suggested by cs461x.c (ALSA driver) */ 1023 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1024 #endif 1025 1026 #if 0 1027 /* I am confused. The sample rate calculation section says 1028 * cci *is* 32-bit signed quantity but in the parameter description 1029 * section, CCI only assigned 16bit. 1030 * I believe size of the variable. 1031 */ 1032 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1033 tmp1 |= cci<<16; 1034 BA1WRITE4(sc, CS4280_CCI, tmp1); 1035 #else 1036 BA1WRITE4(sc, CS4280_CCI, cci); 1037 #endif 1038 1039 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1040 tmp1 |= cdlay <<18; 1041 BA1WRITE4(sc, CS4280_CD, tmp1); 1042 1043 BA1WRITE4(sc, CS4280_CPI, cpi); 1044 1045 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1046 tmp1 |= cgl; 1047 BA1WRITE4(sc, CS4280_CGL, tmp1); 1048 1049 BA1WRITE4(sc, CS4280_CNT, cnt); 1050 1051 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1052 tmp1 |= cgl; 1053 BA1WRITE4(sc, CS4280_CGC, tmp1); 1054 } 1055 1056 void 1057 cs4280_set_dac_rate(sc, rate) 1058 struct cs428x_softc *sc; 1059 int rate; 1060 { 1061 /* 1062 * playback rate may range from 8000Hz to 48000Hz 1063 * 1064 * play_phase_increment = floor(rate*65536*1024/48000) 1065 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1066 * py=floor(px/200) 1067 * play_sample_rate_correction = px - 200*py 1068 * 1069 * play_phase_increment is a 32bit signed quantity. 1070 * play_sample_rate_correction is a 16bit signed quantity. 1071 */ 1072 int32_t ppi; 1073 int16_t psrc; 1074 u_int32_t px, py; 1075 1076 if (rate < 8000) 1077 rate = 8000; 1078 if (rate > 48000) 1079 rate = 48000; 1080 px = rate << 16; 1081 ppi = px/48000; 1082 px -= ppi*48000; 1083 ppi <<= 10; 1084 px <<= 10; 1085 py = px / 48000; 1086 ppi += py; 1087 px -= py*48000; 1088 py = px/200; 1089 px -= py*200; 1090 psrc = px; 1091 #if 0 1092 /* what manual says */ 1093 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1094 BA1WRITE4(sc, CS4280_PSRC, 1095 ( ((psrc<<16) & PSRC_MASK) | px )); 1096 #else 1097 /* suggested by cs461x.c (ALSA driver) */ 1098 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1099 #endif 1100 BA1WRITE4(sc, CS4280_PPI, ppi); 1101 } 1102 1103 /* Download Proceessor Code and Data image */ 1104 int 1105 cs4280_download(sc, src, offset, len) 1106 struct cs428x_softc *sc; 1107 const u_int32_t *src; 1108 u_int32_t offset, len; 1109 { 1110 u_int32_t ctr; 1111 1112 #if CS4280_DEBUG > 10 1113 u_int32_t con, data; 1114 u_int8_t c0,c1,c2,c3; 1115 #endif 1116 if ((offset&3) || (len&3)) 1117 return -1; 1118 1119 len /= sizeof(u_int32_t); 1120 for (ctr = 0; ctr < len; ctr++) { 1121 /* XXX: 1122 * I cannot confirm this is the right thing or not 1123 * on BIG-ENDIAN machines. 1124 */ 1125 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1126 #if CS4280_DEBUG > 10 1127 data = htole32(*(src+ctr)); 1128 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1129 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1130 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1131 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1132 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1133 if (data != con ) { 1134 printf("0x%06x: write=0x%08x read=0x%08x\n", 1135 offset+ctr*4, data, con); 1136 return -1; 1137 } 1138 #endif 1139 } 1140 return 0; 1141 } 1142 1143 int 1144 cs4280_download_image(sc) 1145 struct cs428x_softc *sc; 1146 { 1147 int idx, err; 1148 u_int32_t offset = 0; 1149 1150 err = 0; 1151 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1152 err = cs4280_download(sc, &BA1Struct.map[offset], 1153 BA1Struct.memory[idx].offset, 1154 BA1Struct.memory[idx].size); 1155 if (err != 0) { 1156 printf("%s: load_image failed at %d\n", 1157 sc->sc_dev.dv_xname, idx); 1158 return -1; 1159 } 1160 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1161 } 1162 return err; 1163 } 1164 1165 /* Processor Soft Reset */ 1166 void 1167 cs4280_reset(sc_) 1168 void *sc_; 1169 { 1170 struct cs428x_softc *sc = sc_; 1171 1172 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1173 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1174 delay(100); 1175 /* Clear RSTSP bit in SPCR */ 1176 BA1WRITE4(sc, CS4280_SPCR, 0); 1177 /* enable DMA reqest */ 1178 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1179 } 1180 1181 int 1182 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1183 struct cs428x_softc *sc; 1184 char *class, *device, *qualifier; 1185 { 1186 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1187 device, qualifier)); 1188 } 1189 1190 int 1191 cs4280_init(sc, init) 1192 struct cs428x_softc *sc; 1193 int init; 1194 { 1195 int n; 1196 u_int32_t mem; 1197 1198 /* Start PLL out in known state */ 1199 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1200 /* Start serial ports out in known state */ 1201 BA0WRITE4(sc, CS4280_SERMC1, 0); 1202 1203 /* Specify type of CODEC */ 1204 /* XXX should not be here */ 1205 #define SERACC_CODEC_TYPE_1_03 1206 #ifdef SERACC_CODEC_TYPE_1_03 1207 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1208 #else 1209 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1210 #endif 1211 1212 /* Reset codec */ 1213 BA0WRITE4(sc, CS428X_ACCTL, 0); 1214 delay(100); /* delay 100us */ 1215 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1216 1217 /* Enable AC-link sync generation */ 1218 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1219 delay(50*1000); /* delay 50ms */ 1220 1221 /* Set the serial port timing configuration */ 1222 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1223 1224 /* Setup clock control */ 1225 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1226 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1227 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1228 1229 /* Power up the PLL */ 1230 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1231 delay(50*1000); /* delay 50ms */ 1232 1233 /* Turn on clock */ 1234 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1235 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1236 1237 /* Set the serial port FIFO pointer to the 1238 * first sample in FIFO. (not documented) */ 1239 cs4280_clear_fifos(sc); 1240 1241 #if 0 1242 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1243 BA0WRITE4(sc, CS4280_SERBSP, 0); 1244 #endif 1245 1246 /* Configure the serial port */ 1247 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1248 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1249 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1250 1251 /* Wait for CODEC ready */ 1252 n = 0; 1253 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1254 delay(125); 1255 if (++n > 1000) { 1256 printf("%s: codec ready timeout\n", 1257 sc->sc_dev.dv_xname); 1258 return(1); 1259 } 1260 } 1261 1262 /* Assert valid frame signal */ 1263 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1264 1265 /* Wait for valid AC97 input slot */ 1266 n = 0; 1267 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1268 (ACISV_ISV3 | ACISV_ISV4)) { 1269 delay(1000); 1270 if (++n > 1000) { 1271 printf("AC97 inputs slot ready timeout\n"); 1272 return(1); 1273 } 1274 } 1275 1276 /* Set AC97 output slot valid signals */ 1277 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1278 1279 /* reset the processor */ 1280 cs4280_reset(sc); 1281 1282 /* Download the image to the processor */ 1283 if (cs4280_download_image(sc) != 0) { 1284 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1285 return(1); 1286 } 1287 1288 /* Save playback parameter and then write zero. 1289 * this ensures that DMA doesn't immediately occur upon 1290 * starting the processor core 1291 */ 1292 mem = BA1READ4(sc, CS4280_PCTL); 1293 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1294 cs4280_halt_output(sc); 1295 1296 /* Save capture parameter and then write zero. 1297 * this ensures that DMA doesn't immediately occur upon 1298 * starting the processor core 1299 */ 1300 mem = BA1READ4(sc, CS4280_CCTL); 1301 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1302 cs4280_halt_input(sc); 1303 1304 /* Processor Startup Procedure */ 1305 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1306 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1307 1308 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1309 n = 0; 1310 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1311 delay(10); 1312 if (++n > 1000) { 1313 printf("SPCR 1->0 transition timeout\n"); 1314 return(1); 1315 } 1316 } 1317 1318 n = 0; 1319 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1320 delay(10); 1321 if (++n > 1000) { 1322 printf("SPCS 0->1 transition timeout\n"); 1323 return(1); 1324 } 1325 } 1326 /* Processor is now running !!! */ 1327 1328 /* Setup volume */ 1329 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1330 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1331 1332 /* Interrupt enable */ 1333 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1334 1335 /* playback interrupt enable */ 1336 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1337 mem |= PFIE_PI_ENABLE; 1338 BA1WRITE4(sc, CS4280_PFIE, mem); 1339 /* capture interrupt enable */ 1340 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1341 mem |= CIE_CI_ENABLE; 1342 BA1WRITE4(sc, CS4280_CIE, mem); 1343 1344 #if NMIDI > 0 1345 /* Reset midi port */ 1346 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1347 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1348 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1349 /* midi interrupt enable */ 1350 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1351 BA0WRITE4(sc, CS4280_MIDCR, mem); 1352 #endif 1353 return(0); 1354 } 1355 1356 void 1357 cs4280_clear_fifos(sc) 1358 struct cs428x_softc *sc; 1359 { 1360 int pd = 0, cnt, n; 1361 u_int32_t mem; 1362 1363 /* 1364 * If device power down, power up the device and keep power down 1365 * state. 1366 */ 1367 mem = BA0READ4(sc, CS4280_CLKCR1); 1368 if (!(mem & CLKCR1_SWCE)) { 1369 printf("cs4280_clear_fifo: power down found.\n"); 1370 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1371 pd = 1; 1372 } 1373 BA0WRITE4(sc, CS4280_SERBWP, 0); 1374 for (cnt = 0; cnt < 256; cnt++) { 1375 n = 0; 1376 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1377 delay(1000); 1378 if (++n > 1000) { 1379 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1380 break; 1381 } 1382 } 1383 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1384 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1385 } 1386 if (pd) 1387 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1388 } 1389 1390 #if NMIDI > 0 1391 int 1392 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1393 void *addr; 1394 int flags; 1395 void (*iintr)__P((void *, int)); 1396 void (*ointr)__P((void *)); 1397 void *arg; 1398 { 1399 struct cs428x_softc *sc = addr; 1400 u_int32_t mem; 1401 1402 DPRINTF(("midi_open\n")); 1403 sc->sc_iintr = iintr; 1404 sc->sc_ointr = ointr; 1405 sc->sc_arg = arg; 1406 1407 /* midi interrupt enable */ 1408 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1409 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1410 BA0WRITE4(sc, CS4280_MIDCR, mem); 1411 #ifdef CS4280_DEBUG 1412 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1413 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1414 return(EINVAL); 1415 } 1416 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1417 #endif 1418 return 0; 1419 } 1420 1421 void 1422 cs4280_midi_close(addr) 1423 void *addr; 1424 { 1425 struct cs428x_softc *sc = addr; 1426 u_int32_t mem; 1427 1428 DPRINTF(("midi_close\n")); 1429 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1430 mem = BA0READ4(sc, CS4280_MIDCR); 1431 mem &= ~MIDCR_MASK; 1432 BA0WRITE4(sc, CS4280_MIDCR, mem); 1433 1434 sc->sc_iintr = 0; 1435 sc->sc_ointr = 0; 1436 } 1437 1438 int 1439 cs4280_midi_output(addr, d) 1440 void *addr; 1441 int d; 1442 { 1443 struct cs428x_softc *sc = addr; 1444 u_int32_t mem; 1445 int x; 1446 1447 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1448 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1449 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1450 mem |= d & MIDWP_MASK; 1451 DPRINTFN(5,("midi_output d=0x%08x",d)); 1452 BA0WRITE4(sc, CS4280_MIDWP, mem); 1453 #ifdef DIAGNOSTIC 1454 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1455 DPRINTF(("Bad write data: %d %d", 1456 mem, BA0READ4(sc, CS4280_MIDWP))); 1457 return(EIO); 1458 } 1459 #endif 1460 return 0; 1461 } 1462 delay(MIDI_BUSY_DELAY); 1463 } 1464 return (EIO); 1465 } 1466 1467 void 1468 cs4280_midi_getinfo(addr, mi) 1469 void *addr; 1470 struct midi_info *mi; 1471 { 1472 mi->name = "CS4280 MIDI UART"; 1473 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1474 } 1475 1476 #endif 1477 1478 /* DEBUG functions */ 1479 #if CS4280_DEBUG > 10 1480 int 1481 cs4280_checkimage(sc, src, offset, len) 1482 struct cs428x_softc *sc; 1483 u_int32_t *src; 1484 u_int32_t offset, len; 1485 { 1486 u_int32_t ctr, data; 1487 int err = 0; 1488 1489 if ((offset&3) || (len&3)) 1490 return -1; 1491 1492 len /= sizeof(u_int32_t); 1493 for (ctr = 0; ctr < len; ctr++) { 1494 /* I cannot confirm this is the right thing 1495 * on BIG-ENDIAN machines 1496 */ 1497 data = BA1READ4(sc, offset+ctr*4); 1498 if (data != htole32(*(src+ctr))) { 1499 printf("0x%06x: 0x%08x(0x%08x)\n", 1500 offset+ctr*4, data, *(src+ctr)); 1501 *(src+ctr) = data; 1502 ++err; 1503 } 1504 } 1505 return err; 1506 } 1507 1508 int 1509 cs4280_check_images(sc) 1510 struct cs428x_softc *sc; 1511 { 1512 int idx, err; 1513 u_int32_t offset = 0; 1514 1515 err = 0; 1516 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1517 for (idx = 0; idx < 1; ++idx) { 1518 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1519 BA1Struct.memory[idx].offset, 1520 BA1Struct.memory[idx].size); 1521 if (err != 0) { 1522 printf("%s: check_image failed at %d\n", 1523 sc->sc_dev.dv_xname, idx); 1524 } 1525 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1526 } 1527 return err; 1528 } 1529 1530 #endif 1531
Indexes created Thu Oct 02 14:10:14 GMT 2025