cs4280.c revision 1.7.2.8
1 /* $NetBSD: cs4280.c,v 1.7.2.8 2001/04/21 17:49:10 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include "midi.h" 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/fcntl.h> 60 #include <sys/malloc.h> 61 #include <sys/device.h> 62 #include <sys/proc.h> 63 #include <sys/types.h> 64 #include <sys/systm.h> 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/cs4280reg.h> 69 #include <dev/pci/cs4280_image.h> 70 #include <dev/pci/cs428xreg.h> 71 72 #include <sys/audioio.h> 73 #include <dev/audio_if.h> 74 #include <dev/midi_if.h> 75 #include <dev/mulaw.h> 76 #include <dev/auconv.h> 77 78 #include <dev/ic/ac97reg.h> 79 #include <dev/ic/ac97var.h> 80 81 #include <dev/pci/cs428x.h> 82 83 #include <machine/bus.h> 84 #include <machine/bswap.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 int cs4280_match(struct device *, struct cfdata *, void *); 91 void cs4280_attach(struct device *, struct device *, void *); 92 int cs4280_intr(void *); 93 int cs4280_query_encoding(void *, struct audio_encoding *); 94 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 95 int cs4280_halt_output(void *); 96 int cs4280_halt_input(void *); 97 int cs4280_getdev(void *, struct audio_device *); 98 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 99 void *, struct audio_params *); 100 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 101 void *, struct audio_params *); 102 103 void cs4280_reset_codec(void *); 104 105 /* For PowerHook */ 106 void cs4280_power(int, void *); 107 108 /* Internal functions */ 109 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 110 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 111 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 112 int cs4280_download_image(struct cs428x_softc *); 113 void cs4280_reset(void *); 114 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 115 int cs4280_init(struct cs428x_softc *, int); 116 void cs4280_clear_fifos(struct cs428x_softc *); 117 118 #if CS4280_DEBUG > 10 119 /* Thease two function is only for checking image loading is succeeded or not. */ 120 int cs4280_check_images(struct cs428x_softc *); 121 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 122 #endif 123 124 struct audio_hw_if cs4280_hw_if = { 125 cs428x_open, 126 cs428x_close, 127 NULL, 128 cs4280_query_encoding, 129 cs4280_set_params, 130 cs428x_round_blocksize, 131 NULL, 132 NULL, 133 NULL, 134 NULL, 135 NULL, 136 cs4280_halt_output, 137 cs4280_halt_input, 138 NULL, 139 cs4280_getdev, 140 NULL, 141 cs428x_mixer_set_port, 142 cs428x_mixer_get_port, 143 cs428x_query_devinfo, 144 cs428x_malloc, 145 cs428x_free, 146 cs428x_round_buffersize, 147 cs428x_mappage, 148 cs428x_get_props, 149 cs4280_trigger_output, 150 cs4280_trigger_input, 151 }; 152 153 #if NMIDI > 0 154 /* Midi Interface */ 155 int cs4280_midi_open(void *, int, void (*)(void *, int), 156 void (*)(void *), void *); 157 void cs4280_midi_close(void*); 158 int cs4280_midi_output(void *, int); 159 void cs4280_midi_getinfo(void *, struct midi_info *); 160 161 struct midi_hw_if cs4280_midi_hw_if = { 162 cs4280_midi_open, 163 cs4280_midi_close, 164 cs4280_midi_output, 165 cs4280_midi_getinfo, 166 0, 167 }; 168 #endif 169 170 struct cfattach clcs_ca = { 171 sizeof(struct cs428x_softc), cs4280_match, cs4280_attach 172 }; 173 174 struct audio_device cs4280_device = { 175 "CS4280", 176 "", 177 "cs4280" 178 }; 179 180 181 int 182 cs4280_match(parent, match, aux) 183 struct device *parent; 184 struct cfdata *match; 185 void *aux; 186 { 187 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 188 189 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 190 return 0; 191 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 192 #if 0 /* I can't confirm */ 193 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 194 #endif 195 ) 196 return 1; 197 return 0; 198 } 199 200 void 201 cs4280_attach(parent, self, aux) 202 struct device *parent; 203 struct device *self; 204 void *aux; 205 { 206 struct cs428x_softc *sc = (struct cs428x_softc *)self; 207 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 208 pci_chipset_tag_t pc = pa->pa_pc; 209 char const *intrstr; 210 pci_intr_handle_t ih; 211 pcireg_t reg; 212 char devinfo[256]; 213 mixer_ctrl_t ctl; 214 u_int32_t mem; 215 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 216 217 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 218 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 219 220 /* Map I/O register */ 221 if (pci_mapreg_map(pa, PCI_BA0, 222 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 223 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 224 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 225 return; 226 } 227 if (pci_mapreg_map(pa, PCI_BA1, 228 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 229 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 230 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 231 return; 232 } 233 234 sc->sc_dmatag = pa->pa_dmat; 235 236 /* Check and set Power State */ 237 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 238 &pci_pwrmgmt_cap_reg, 0)) { 239 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 240 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 241 pci_pwrmgmt_csr_reg); 242 DPRINTF(("%s: Power State is %d\n", 243 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 244 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 245 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 246 (reg & ~PCI_PMCSR_STATE_MASK) | 247 PCI_PMCSR_STATE_D0); 248 } 249 } 250 251 /* Enable the device (set bus master flag) */ 252 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 253 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 254 reg | PCI_COMMAND_MASTER_ENABLE); 255 256 /* LATENCY_TIMER setting */ 257 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 258 if ( PCI_LATTIMER(mem) < 32 ) { 259 mem &= 0xffff00ff; 260 mem |= 0x00002000; 261 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 262 } 263 264 /* Map and establish the interrupt. */ 265 if (pci_intr_map(pa, &ih)) { 266 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 267 return; 268 } 269 intrstr = pci_intr_string(pc, ih); 270 271 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 272 if (sc->sc_ih == NULL) { 273 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 274 if (intrstr != NULL) 275 printf(" at %s", intrstr); 276 printf("\n"); 277 return; 278 } 279 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 280 281 /* Initialization */ 282 if(cs4280_init(sc, 1) != 0) 283 return; 284 285 sc->type = TYPE_CS4280; 286 sc->halt_input = cs4280_halt_input; 287 sc->halt_output = cs4280_halt_output; 288 289 /* setup buffer related parameters */ 290 sc->dma_size = CS4280_DCHUNK; 291 sc->dma_align = CS4280_DALIGN; 292 sc->hw_blocksize = CS4280_ICHUNK; 293 294 /* AC 97 attachment */ 295 sc->host_if.arg = sc; 296 sc->host_if.attach = cs428x_attach_codec; 297 sc->host_if.read = cs428x_read_codec; 298 sc->host_if.write = cs428x_write_codec; 299 sc->host_if.reset = cs4280_reset_codec; 300 if (ac97_attach(&sc->host_if) != 0) { 301 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 302 return; 303 } 304 305 /* Turn mute off of DAC, CD and master volumes by default */ 306 ctl.type = AUDIO_MIXER_ENUM; 307 ctl.un.ord = 0; /* off */ 308 309 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 310 AudioNmaster, AudioNmute); 311 cs428x_mixer_set_port(sc, &ctl); 312 313 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 314 AudioNdac, AudioNmute); 315 cs428x_mixer_set_port(sc, &ctl); 316 317 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 318 AudioNcd, AudioNmute); 319 cs428x_mixer_set_port(sc, &ctl); 320 321 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 322 323 #if NMIDI > 0 324 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 325 #endif 326 327 sc->sc_suspend = PWR_RESUME; 328 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 329 } 330 331 /* Interrupt handling function */ 332 int 333 cs4280_intr(p) 334 void *p; 335 { 336 /* 337 * XXX 338 * 339 * Since CS4280 has only 4kB dma buffer and 340 * interrupt occurs every 2kB block, I create dummy buffer 341 * which returns to audio driver and actual dma buffer 342 * using in DMA transfer. 343 * 344 * 345 * ring buffer in audio.c is pointed by BUFADDR 346 * <------ ring buffer size == 64kB ------> 347 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 348 * |= = = =|= = = =|= = = =|= = = =|= = = =| 349 * | | | | | | <- call audio_intp every 350 * sc->sc_[pr]_count time. 351 * 352 * actual dma buffer is pointed by KERNADDR 353 * <-> dma buffer size = 4kB 354 * |= =| 355 * 356 * 357 */ 358 struct cs428x_softc *sc = p; 359 u_int32_t intr, mem; 360 char * empty_dma; 361 int handled = 0; 362 363 /* grab interrupt register then clear it */ 364 intr = BA0READ4(sc, CS4280_HISR); 365 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 366 367 /* Playback Interrupt */ 368 if (intr & HISR_PINT) { 369 handled = 1; 370 mem = BA1READ4(sc, CS4280_PFIE); 371 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 372 if (sc->sc_pintr) { 373 if ((sc->sc_pi%sc->sc_pcount) == 0) 374 sc->sc_pintr(sc->sc_parg); 375 } else { 376 printf("unexpected play intr\n"); 377 } 378 /* copy buffer */ 379 ++sc->sc_pi; 380 empty_dma = sc->sc_pdma->addr; 381 if (sc->sc_pi&1) 382 empty_dma += sc->hw_blocksize; 383 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 384 sc->sc_pn += sc->hw_blocksize; 385 if (sc->sc_pn >= sc->sc_pe) 386 sc->sc_pn = sc->sc_ps; 387 BA1WRITE4(sc, CS4280_PFIE, mem); 388 } 389 /* Capture Interrupt */ 390 if (intr & HISR_CINT) { 391 int i; 392 int16_t rdata; 393 394 handled = 1; 395 mem = BA1READ4(sc, CS4280_CIE); 396 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 397 ++sc->sc_ri; 398 empty_dma = sc->sc_rdma->addr; 399 if ((sc->sc_ri&1) == 0) 400 empty_dma += sc->hw_blocksize; 401 402 /* 403 * XXX 404 * I think this audio data conversion should be 405 * happend in upper layer, but I put this here 406 * since there is no conversion function available. 407 */ 408 switch(sc->sc_rparam) { 409 case CF_16BIT_STEREO: 410 /* just copy it */ 411 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 412 sc->sc_rn += sc->hw_blocksize; 413 break; 414 case CF_16BIT_MONO: 415 for (i = 0; i < 512; i++) { 416 rdata = *((int16_t *)empty_dma)++>>1; 417 rdata += *((int16_t *)empty_dma)++>>1; 418 *((int16_t *)sc->sc_rn)++ = rdata; 419 } 420 break; 421 case CF_8BIT_STEREO: 422 for (i = 0; i < 512; i++) { 423 rdata = *((int16_t*)empty_dma)++; 424 *sc->sc_rn++ = rdata >> 8; 425 rdata = *((int16_t*)empty_dma)++; 426 *sc->sc_rn++ = rdata >> 8; 427 } 428 break; 429 case CF_8BIT_MONO: 430 for (i = 0; i < 512; i++) { 431 rdata = *((int16_t*)empty_dma)++ >>1; 432 rdata += *((int16_t*)empty_dma)++ >>1; 433 *sc->sc_rn++ = rdata >>8; 434 } 435 break; 436 default: 437 /* Should not reach here */ 438 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 439 } 440 if (sc->sc_rn >= sc->sc_re) 441 sc->sc_rn = sc->sc_rs; 442 BA1WRITE4(sc, CS4280_CIE, mem); 443 if (sc->sc_rintr) { 444 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 445 sc->sc_rintr(sc->sc_rarg); 446 } else { 447 printf("unexpected record intr\n"); 448 } 449 } 450 451 #if NMIDI > 0 452 /* Midi port Interrupt */ 453 if (intr & HISR_MIDI) { 454 int data; 455 456 handled = 1; 457 DPRINTF(("i: %d: ", 458 BA0READ4(sc, CS4280_MIDSR))); 459 /* Read the received data */ 460 while ((sc->sc_iintr != NULL) && 461 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 462 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 463 DPRINTF(("r:%x\n",data)); 464 sc->sc_iintr(sc->sc_arg, data); 465 } 466 467 /* Write the data */ 468 #if 1 469 /* XXX: 470 * It seems "Transmit Buffer Full" never activate until EOI 471 * is deliverd. Shall I throw EOI top of this routine ? 472 */ 473 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 474 DPRINTF(("w: ")); 475 if (sc->sc_ointr != NULL) 476 sc->sc_ointr(sc->sc_arg); 477 } 478 #else 479 while ((sc->sc_ointr != NULL) && 480 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 481 DPRINTF(("w: ")); 482 sc->sc_ointr(sc->sc_arg); 483 } 484 #endif 485 DPRINTF(("\n")); 486 } 487 #endif 488 489 return handled; 490 } 491 492 int 493 cs4280_query_encoding(addr, fp) 494 void *addr; 495 struct audio_encoding *fp; 496 { 497 switch (fp->index) { 498 case 0: 499 strcpy(fp->name, AudioEulinear); 500 fp->encoding = AUDIO_ENCODING_ULINEAR; 501 fp->precision = 8; 502 fp->flags = 0; 503 break; 504 case 1: 505 strcpy(fp->name, AudioEmulaw); 506 fp->encoding = AUDIO_ENCODING_ULAW; 507 fp->precision = 8; 508 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 509 break; 510 case 2: 511 strcpy(fp->name, AudioEalaw); 512 fp->encoding = AUDIO_ENCODING_ALAW; 513 fp->precision = 8; 514 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 515 break; 516 case 3: 517 strcpy(fp->name, AudioEslinear); 518 fp->encoding = AUDIO_ENCODING_SLINEAR; 519 fp->precision = 8; 520 fp->flags = 0; 521 break; 522 case 4: 523 strcpy(fp->name, AudioEslinear_le); 524 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 525 fp->precision = 16; 526 fp->flags = 0; 527 break; 528 case 5: 529 strcpy(fp->name, AudioEulinear_le); 530 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 531 fp->precision = 16; 532 fp->flags = 0; 533 break; 534 case 6: 535 strcpy(fp->name, AudioEslinear_be); 536 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 537 fp->precision = 16; 538 fp->flags = 0; 539 break; 540 case 7: 541 strcpy(fp->name, AudioEulinear_be); 542 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 543 fp->precision = 16; 544 fp->flags = 0; 545 break; 546 default: 547 return EINVAL; 548 } 549 return 0; 550 } 551 552 int 553 cs4280_set_params(addr, setmode, usemode, play, rec) 554 void *addr; 555 int setmode, usemode; 556 struct audio_params *play, *rec; 557 { 558 struct cs428x_softc *sc = addr; 559 struct audio_params *p; 560 int mode; 561 562 for (mode = AUMODE_RECORD; mode != -1; 563 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 564 if ((setmode & mode) == 0) 565 continue; 566 567 p = mode == AUMODE_PLAY ? play : rec; 568 569 if (p == play) { 570 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 571 p->sample_rate, p->precision, p->channels)); 572 /* play back data format may be 8- or 16-bit and 573 * either stereo or mono. 574 * playback rate may range from 8000Hz to 48000Hz 575 */ 576 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 577 (p->precision != 8 && p->precision != 16) || 578 (p->channels != 1 && p->channels != 2) ) { 579 return EINVAL; 580 } 581 } else { 582 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 583 p->sample_rate, p->precision, p->channels)); 584 /* capture data format must be 16bit stereo 585 * and sample rate range from 11025Hz to 48000Hz. 586 * 587 * XXX: it looks like to work with 8000Hz, 588 * although data sheets say lower limit is 589 * 11025 Hz. 590 */ 591 592 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 593 (p->precision != 8 && p->precision != 16) || 594 (p->channels != 1 && p->channels != 2) ) { 595 return EINVAL; 596 } 597 } 598 p->factor = 1; 599 p->sw_code = 0; 600 601 /* capturing data is slinear */ 602 switch (p->encoding) { 603 case AUDIO_ENCODING_SLINEAR_BE: 604 if (mode == AUMODE_RECORD) { 605 if (p->precision == 16) 606 p->sw_code = swap_bytes; 607 } 608 break; 609 case AUDIO_ENCODING_SLINEAR_LE: 610 break; 611 case AUDIO_ENCODING_ULINEAR_BE: 612 if (mode == AUMODE_RECORD) { 613 if (p->precision == 16) 614 p->sw_code = change_sign16_swap_bytes_le; 615 else 616 p->sw_code = change_sign8; 617 } 618 break; 619 case AUDIO_ENCODING_ULINEAR_LE: 620 if (mode == AUMODE_RECORD) { 621 if (p->precision == 16) 622 p->sw_code = change_sign16_le; 623 else 624 p->sw_code = change_sign8; 625 } 626 break; 627 case AUDIO_ENCODING_ULAW: 628 if (mode == AUMODE_PLAY) { 629 p->factor = 2; 630 p->sw_code = mulaw_to_slinear16_le; 631 } else { 632 p->sw_code = slinear8_to_mulaw; 633 } 634 break; 635 case AUDIO_ENCODING_ALAW: 636 if (mode == AUMODE_PLAY) { 637 p->factor = 2; 638 p->sw_code = alaw_to_slinear16_le; 639 } else { 640 p->sw_code = slinear8_to_alaw; 641 } 642 break; 643 default: 644 return EINVAL; 645 } 646 } 647 648 /* set sample rate */ 649 cs4280_set_dac_rate(sc, play->sample_rate); 650 cs4280_set_adc_rate(sc, rec->sample_rate); 651 return 0; 652 } 653 654 int 655 cs4280_halt_output(addr) 656 void *addr; 657 { 658 struct cs428x_softc *sc = addr; 659 u_int32_t mem; 660 661 mem = BA1READ4(sc, CS4280_PCTL); 662 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 663 sc->sc_prun = 0; 664 return 0; 665 } 666 667 int 668 cs4280_halt_input(addr) 669 void *addr; 670 { 671 struct cs428x_softc *sc = addr; 672 u_int32_t mem; 673 674 mem = BA1READ4(sc, CS4280_CCTL); 675 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 676 sc->sc_rrun = 0; 677 return 0; 678 } 679 680 int 681 cs4280_getdev(addr, retp) 682 void *addr; 683 struct audio_device *retp; 684 { 685 *retp = cs4280_device; 686 return 0; 687 } 688 689 int 690 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 691 void *addr; 692 void *start, *end; 693 int blksize; 694 void (*intr) __P((void *)); 695 void *arg; 696 struct audio_params *param; 697 { 698 struct cs428x_softc *sc = addr; 699 u_int32_t pfie, pctl, pdtc; 700 struct cs428x_dma *p; 701 702 #ifdef DIAGNOSTIC 703 if (sc->sc_prun) 704 printf("cs4280_trigger_output: already running\n"); 705 #endif 706 sc->sc_prun = 1; 707 708 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 709 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 710 sc->sc_pintr = intr; 711 sc->sc_parg = arg; 712 713 /* stop playback DMA */ 714 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 715 716 /* setup PDTC */ 717 pdtc = BA1READ4(sc, CS4280_PDTC); 718 pdtc &= ~PDTC_MASK; 719 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 720 BA1WRITE4(sc, CS4280_PDTC, pdtc); 721 722 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 723 param->precision, param->factor, param->channels, 724 param->encoding)); 725 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 726 ; 727 if (p == NULL) { 728 printf("cs4280_trigger_output: bad addr %p\n", start); 729 return EINVAL; 730 } 731 if (DMAADDR(p) % sc->dma_align != 0 ) { 732 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 733 "4kB align\n", DMAADDR(p)); 734 return EINVAL; 735 } 736 737 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 738 sc->sc_ps = (char *)start; 739 sc->sc_pe = (char *)end; 740 sc->sc_pdma = p; 741 sc->sc_pbuf = KERNADDR(p); 742 sc->sc_pi = 0; 743 sc->sc_pn = sc->sc_ps; 744 if (blksize >= sc->dma_size) { 745 sc->sc_pn = sc->sc_ps + sc->dma_size; 746 memcpy(sc->sc_pbuf, start, sc->dma_size); 747 ++sc->sc_pi; 748 } else { 749 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 750 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 751 } 752 753 /* initiate playback dma */ 754 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 755 756 /* set PFIE */ 757 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 758 759 if (param->precision * param->factor == 8) 760 pfie |= PFIE_8BIT; 761 if (param->channels == 1) 762 pfie |= PFIE_MONO; 763 764 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 765 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 766 pfie |= PFIE_SWAPPED; 767 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 768 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 769 pfie |= PFIE_UNSIGNED; 770 771 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 772 773 sc->sc_prate = param->sample_rate; 774 cs4280_set_dac_rate(sc, param->sample_rate); 775 776 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 777 pctl |= sc->pctl; 778 BA1WRITE4(sc, CS4280_PCTL, pctl); 779 return 0; 780 } 781 782 int 783 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 784 void *addr; 785 void *start, *end; 786 int blksize; 787 void (*intr) __P((void *)); 788 void *arg; 789 struct audio_params *param; 790 { 791 struct cs428x_softc *sc = addr; 792 u_int32_t cctl, cie; 793 struct cs428x_dma *p; 794 795 #ifdef DIAGNOSTIC 796 if (sc->sc_rrun) 797 printf("cs4280_trigger_input: already running\n"); 798 #endif 799 sc->sc_rrun = 1; 800 801 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 802 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 803 sc->sc_rintr = intr; 804 sc->sc_rarg = arg; 805 806 /* stop capture DMA */ 807 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 808 809 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 810 ; 811 if (p == NULL) { 812 printf("cs4280_trigger_input: bad addr %p\n", start); 813 return EINVAL; 814 } 815 if (DMAADDR(p) % sc->dma_align != 0) { 816 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 817 "4kB align\n", DMAADDR(p)); 818 return EINVAL; 819 } 820 821 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 822 sc->sc_rs = (char *)start; 823 sc->sc_re = (char *)end; 824 sc->sc_rdma = p; 825 sc->sc_rbuf = KERNADDR(p); 826 sc->sc_ri = 0; 827 sc->sc_rn = sc->sc_rs; 828 829 /* initiate capture dma */ 830 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 831 832 /* setup format information for internal converter */ 833 sc->sc_rparam = 0; 834 if (param->precision == 8) { 835 sc->sc_rparam += CF_8BIT; 836 sc->sc_rcount <<= 1; 837 } 838 if (param->channels == 1) { 839 sc->sc_rparam += CF_MONO; 840 sc->sc_rcount <<= 1; 841 } 842 843 /* set CIE */ 844 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 845 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 846 847 sc->sc_rrate = param->sample_rate; 848 cs4280_set_adc_rate(sc, param->sample_rate); 849 850 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 851 cctl |= sc->cctl; 852 BA1WRITE4(sc, CS4280_CCTL, cctl); 853 return 0; 854 } 855 856 /* Power Hook */ 857 void 858 cs4280_power(why, v) 859 int why; 860 void *v; 861 { 862 struct cs428x_softc *sc = (struct cs428x_softc *)v; 863 static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 864 static u_int32_t cctl = 0, cba = 0, cie = 0; 865 866 DPRINTF(("%s: cs4280_power why=%d\n", 867 sc->sc_dev.dv_xname, why)); 868 switch (why) { 869 case PWR_SUSPEND: 870 case PWR_STANDBY: 871 sc->sc_suspend = why; 872 873 /* save current playback status */ 874 if ( sc->sc_prun ) { 875 pctl = BA1READ4(sc, CS4280_PCTL); 876 pfie = BA1READ4(sc, CS4280_PFIE); 877 pba = BA1READ4(sc, CS4280_PBA); 878 pdtc = BA1READ4(sc, CS4280_PDTC); 879 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 880 pctl, pfie, pba, pdtc)); 881 } 882 883 /* save current capture status */ 884 if ( sc->sc_rrun ) { 885 cctl = BA1READ4(sc, CS4280_CCTL); 886 cie = BA1READ4(sc, CS4280_CIE); 887 cba = BA1READ4(sc, CS4280_CBA); 888 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 889 cctl, cie, cba)); 890 } 891 892 /* Stop DMA */ 893 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 894 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 895 break; 896 case PWR_RESUME: 897 if (sc->sc_suspend == PWR_RESUME) { 898 printf("cs4280_power: odd, resume without suspend.\n"); 899 sc->sc_suspend = why; 900 return; 901 } 902 sc->sc_suspend = why; 903 cs4280_init(sc, 0); 904 cs4280_reset_codec(sc); 905 906 /* restore ac97 registers */ 907 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 908 909 /* restore DMA related status */ 910 if(sc->sc_prun) { 911 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 912 pctl, pfie, pba, pdtc)); 913 cs4280_set_dac_rate(sc, sc->sc_prate); 914 BA1WRITE4(sc, CS4280_PDTC, pdtc); 915 BA1WRITE4(sc, CS4280_PBA, pba); 916 BA1WRITE4(sc, CS4280_PFIE, pfie); 917 BA1WRITE4(sc, CS4280_PCTL, pctl); 918 } 919 920 if (sc->sc_rrun) { 921 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 922 cctl, cie, cba)); 923 cs4280_set_adc_rate(sc, sc->sc_rrate); 924 BA1WRITE4(sc, CS4280_CBA, cba); 925 BA1WRITE4(sc, CS4280_CIE, cie); 926 BA1WRITE4(sc, CS4280_CCTL, cctl); 927 } 928 break; 929 case PWR_SOFTSUSPEND: 930 case PWR_SOFTSTANDBY: 931 case PWR_SOFTRESUME: 932 break; 933 } 934 } 935 936 /* control AC97 codec */ 937 void 938 cs4280_reset_codec(void *addr) 939 { 940 struct cs428x_softc *sc; 941 int n; 942 943 sc = addr; 944 945 /* Reset codec */ 946 BA0WRITE4(sc, CS428X_ACCTL, 0); 947 delay(100); /* delay 100us */ 948 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 949 950 /* 951 * It looks like we do the following procedure, too 952 */ 953 954 /* Enable AC-link sync generation */ 955 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 956 delay(50*1000); /* XXX delay 50ms */ 957 958 /* Assert valid frame signal */ 959 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 960 961 /* Wait for valid AC97 input slot */ 962 n = 0; 963 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 964 (ACISV_ISV3 | ACISV_ISV4)) { 965 delay(1000); 966 if (++n > 1000) { 967 printf("reset_codec: AC97 inputs slot ready timeout\n"); 968 return; 969 } 970 } 971 } 972 973 974 /* Internal functions */ 975 976 void 977 cs4280_set_adc_rate(sc, rate) 978 struct cs428x_softc *sc; 979 int rate; 980 { 981 /* calculate capture rate: 982 * 983 * capture_coefficient_increment = -round(rate*128*65536/48000; 984 * capture_phase_increment = floor(48000*65536*1024/rate); 985 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 986 * cy = floor(cx/200); 987 * capture_sample_rate_correction = cx - 200*cy; 988 * capture_delay = ceil(24*48000/rate); 989 * capture_num_triplets = floor(65536*rate/24000); 990 * capture_group_length = 24000/GCD(rate, 24000); 991 * where GCD means "Greatest Common Divisor". 992 * 993 * capture_coefficient_increment, capture_phase_increment and 994 * capture_num_triplets are 32-bit signed quantities. 995 * capture_sample_rate_correction and capture_group_length are 996 * 16-bit signed quantities. 997 * capture_delay is a 14-bit unsigned quantity. 998 */ 999 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 1000 u_int16_t csrc, cgl, cdlay; 1001 1002 /* XXX 1003 * Even though, embedded_audio_spec says capture rate range 11025 to 1004 * 48000, dhwiface.cpp says, 1005 * 1006 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1007 * Return an error if an attempt is made to stray outside that limit." 1008 * 1009 * so assume range as 48000/9 to 48000 1010 */ 1011 1012 if (rate < 8000) 1013 rate = 8000; 1014 if (rate > 48000) 1015 rate = 48000; 1016 1017 cx = rate << 16; 1018 cci = cx / 48000; 1019 cx -= cci * 48000; 1020 cx <<= 7; 1021 cci <<= 7; 1022 cci += cx / 48000; 1023 cci = - cci; 1024 1025 cx = 48000 << 16; 1026 cpi = cx / rate; 1027 cx -= cpi * rate; 1028 cx <<= 10; 1029 cpi <<= 10; 1030 cy = cx / rate; 1031 cpi += cy; 1032 cx -= cy * rate; 1033 1034 cy = cx / 200; 1035 csrc = cx - 200*cy; 1036 1037 cdlay = ((48000 * 24) + rate - 1) / rate; 1038 #if 0 1039 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1040 #endif 1041 1042 cnt = rate << 16; 1043 cnt /= 24000; 1044 1045 cgl = 1; 1046 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1047 if (((rate / tmp1) * tmp1) != rate) 1048 cgl *= 2; 1049 } 1050 if (((rate / 3) * 3) != rate) 1051 cgl *= 3; 1052 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1053 if (((rate / tmp1) * tmp1) != rate) 1054 cgl *= 5; 1055 } 1056 #if 0 1057 /* XXX what manual says */ 1058 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1059 tmp1 |= csrc<<16; 1060 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1061 #else 1062 /* suggested by cs461x.c (ALSA driver) */ 1063 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1064 #endif 1065 1066 #if 0 1067 /* I am confused. The sample rate calculation section says 1068 * cci *is* 32-bit signed quantity but in the parameter description 1069 * section, CCI only assigned 16bit. 1070 * I believe size of the variable. 1071 */ 1072 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1073 tmp1 |= cci<<16; 1074 BA1WRITE4(sc, CS4280_CCI, tmp1); 1075 #else 1076 BA1WRITE4(sc, CS4280_CCI, cci); 1077 #endif 1078 1079 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1080 tmp1 |= cdlay <<18; 1081 BA1WRITE4(sc, CS4280_CD, tmp1); 1082 1083 BA1WRITE4(sc, CS4280_CPI, cpi); 1084 1085 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1086 tmp1 |= cgl; 1087 BA1WRITE4(sc, CS4280_CGL, tmp1); 1088 1089 BA1WRITE4(sc, CS4280_CNT, cnt); 1090 1091 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1092 tmp1 |= cgl; 1093 BA1WRITE4(sc, CS4280_CGC, tmp1); 1094 } 1095 1096 void 1097 cs4280_set_dac_rate(sc, rate) 1098 struct cs428x_softc *sc; 1099 int rate; 1100 { 1101 /* 1102 * playback rate may range from 8000Hz to 48000Hz 1103 * 1104 * play_phase_increment = floor(rate*65536*1024/48000) 1105 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1106 * py=floor(px/200) 1107 * play_sample_rate_correction = px - 200*py 1108 * 1109 * play_phase_increment is a 32bit signed quantity. 1110 * play_sample_rate_correction is a 16bit signed quantity. 1111 */ 1112 int32_t ppi; 1113 int16_t psrc; 1114 u_int32_t px, py; 1115 1116 if (rate < 8000) 1117 rate = 8000; 1118 if (rate > 48000) 1119 rate = 48000; 1120 px = rate << 16; 1121 ppi = px/48000; 1122 px -= ppi*48000; 1123 ppi <<= 10; 1124 px <<= 10; 1125 py = px / 48000; 1126 ppi += py; 1127 px -= py*48000; 1128 py = px/200; 1129 px -= py*200; 1130 psrc = px; 1131 #if 0 1132 /* what manual says */ 1133 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1134 BA1WRITE4(sc, CS4280_PSRC, 1135 ( ((psrc<<16) & PSRC_MASK) | px )); 1136 #else 1137 /* suggested by cs461x.c (ALSA driver) */ 1138 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1139 #endif 1140 BA1WRITE4(sc, CS4280_PPI, ppi); 1141 } 1142 1143 /* Download Proceessor Code and Data image */ 1144 int 1145 cs4280_download(sc, src, offset, len) 1146 struct cs428x_softc *sc; 1147 const u_int32_t *src; 1148 u_int32_t offset, len; 1149 { 1150 u_int32_t ctr; 1151 1152 #if CS4280_DEBUG > 10 1153 u_int32_t con, data; 1154 u_int8_t c0,c1,c2,c3; 1155 #endif 1156 if ((offset&3) || (len&3)) 1157 return -1; 1158 1159 len /= sizeof(u_int32_t); 1160 for (ctr = 0; ctr < len; ctr++) { 1161 /* XXX: 1162 * I cannot confirm this is the right thing or not 1163 * on BIG-ENDIAN machines. 1164 */ 1165 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1166 #if CS4280_DEBUG > 10 1167 data = htole32(*(src+ctr)); 1168 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1169 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1170 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1171 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1172 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1173 if (data != con ) { 1174 printf("0x%06x: write=0x%08x read=0x%08x\n", 1175 offset+ctr*4, data, con); 1176 return -1; 1177 } 1178 #endif 1179 } 1180 return 0; 1181 } 1182 1183 int 1184 cs4280_download_image(sc) 1185 struct cs428x_softc *sc; 1186 { 1187 int idx, err; 1188 u_int32_t offset = 0; 1189 1190 err = 0; 1191 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1192 err = cs4280_download(sc, &BA1Struct.map[offset], 1193 BA1Struct.memory[idx].offset, 1194 BA1Struct.memory[idx].size); 1195 if (err != 0) { 1196 printf("%s: load_image failed at %d\n", 1197 sc->sc_dev.dv_xname, idx); 1198 return -1; 1199 } 1200 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1201 } 1202 return err; 1203 } 1204 1205 /* Processor Soft Reset */ 1206 void 1207 cs4280_reset(sc_) 1208 void *sc_; 1209 { 1210 struct cs428x_softc *sc = sc_; 1211 1212 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1213 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1214 delay(100); 1215 /* Clear RSTSP bit in SPCR */ 1216 BA1WRITE4(sc, CS4280_SPCR, 0); 1217 /* enable DMA reqest */ 1218 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1219 } 1220 1221 int 1222 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1223 struct cs428x_softc *sc; 1224 char *class, *device, *qualifier; 1225 { 1226 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1227 device, qualifier)); 1228 } 1229 1230 int 1231 cs4280_init(sc, init) 1232 struct cs428x_softc *sc; 1233 int init; 1234 { 1235 int n; 1236 u_int32_t mem; 1237 1238 /* Start PLL out in known state */ 1239 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1240 /* Start serial ports out in known state */ 1241 BA0WRITE4(sc, CS4280_SERMC1, 0); 1242 1243 /* Specify type of CODEC */ 1244 /* XXX should not be here */ 1245 #define SERACC_CODEC_TYPE_1_03 1246 #ifdef SERACC_CODEC_TYPE_1_03 1247 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1248 #else 1249 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1250 #endif 1251 1252 /* Reset codec */ 1253 BA0WRITE4(sc, CS428X_ACCTL, 0); 1254 delay(100); /* delay 100us */ 1255 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1256 1257 /* Enable AC-link sync generation */ 1258 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1259 delay(50*1000); /* delay 50ms */ 1260 1261 /* Set the serial port timing configuration */ 1262 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1263 1264 /* Setup clock control */ 1265 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1266 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1267 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1268 1269 /* Power up the PLL */ 1270 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1271 delay(50*1000); /* delay 50ms */ 1272 1273 /* Turn on clock */ 1274 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1275 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1276 1277 /* Set the serial port FIFO pointer to the 1278 * first sample in FIFO. (not documented) */ 1279 cs4280_clear_fifos(sc); 1280 1281 #if 0 1282 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1283 BA0WRITE4(sc, CS4280_SERBSP, 0); 1284 #endif 1285 1286 /* Configure the serial port */ 1287 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1288 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1289 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1290 1291 /* Wait for CODEC ready */ 1292 n = 0; 1293 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1294 delay(125); 1295 if (++n > 1000) { 1296 printf("%s: codec ready timeout\n", 1297 sc->sc_dev.dv_xname); 1298 return(1); 1299 } 1300 } 1301 1302 /* Assert valid frame signal */ 1303 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1304 1305 /* Wait for valid AC97 input slot */ 1306 n = 0; 1307 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1308 (ACISV_ISV3 | ACISV_ISV4)) { 1309 delay(1000); 1310 if (++n > 1000) { 1311 printf("AC97 inputs slot ready timeout\n"); 1312 return(1); 1313 } 1314 } 1315 1316 /* Set AC97 output slot valid signals */ 1317 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1318 1319 /* reset the processor */ 1320 cs4280_reset(sc); 1321 1322 /* Download the image to the processor */ 1323 if (cs4280_download_image(sc) != 0) { 1324 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1325 return(1); 1326 } 1327 1328 /* Save playback parameter and then write zero. 1329 * this ensures that DMA doesn't immediately occur upon 1330 * starting the processor core 1331 */ 1332 mem = BA1READ4(sc, CS4280_PCTL); 1333 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1334 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1335 if (init != 0) 1336 sc->sc_prun = 0; 1337 1338 /* Save capture parameter and then write zero. 1339 * this ensures that DMA doesn't immediately occur upon 1340 * starting the processor core 1341 */ 1342 mem = BA1READ4(sc, CS4280_CCTL); 1343 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1344 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1345 if (init != 0) 1346 sc->sc_rrun = 0; 1347 1348 /* Processor Startup Procedure */ 1349 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1350 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1351 1352 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1353 n = 0; 1354 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1355 delay(10); 1356 if (++n > 1000) { 1357 printf("SPCR 1->0 transition timeout\n"); 1358 return(1); 1359 } 1360 } 1361 1362 n = 0; 1363 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1364 delay(10); 1365 if (++n > 1000) { 1366 printf("SPCS 0->1 transition timeout\n"); 1367 return(1); 1368 } 1369 } 1370 /* Processor is now running !!! */ 1371 1372 /* Setup volume */ 1373 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1374 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1375 1376 /* Interrupt enable */ 1377 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1378 1379 /* playback interrupt enable */ 1380 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1381 mem |= PFIE_PI_ENABLE; 1382 BA1WRITE4(sc, CS4280_PFIE, mem); 1383 /* capture interrupt enable */ 1384 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1385 mem |= CIE_CI_ENABLE; 1386 BA1WRITE4(sc, CS4280_CIE, mem); 1387 1388 #if NMIDI > 0 1389 /* Reset midi port */ 1390 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1391 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1392 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1393 /* midi interrupt enable */ 1394 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1395 BA0WRITE4(sc, CS4280_MIDCR, mem); 1396 #endif 1397 return(0); 1398 } 1399 1400 void 1401 cs4280_clear_fifos(sc) 1402 struct cs428x_softc *sc; 1403 { 1404 int pd = 0, cnt, n; 1405 u_int32_t mem; 1406 1407 /* 1408 * If device power down, power up the device and keep power down 1409 * state. 1410 */ 1411 mem = BA0READ4(sc, CS4280_CLKCR1); 1412 if (!(mem & CLKCR1_SWCE)) { 1413 printf("cs4280_clear_fifo: power down found.\n"); 1414 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1415 pd = 1; 1416 } 1417 BA0WRITE4(sc, CS4280_SERBWP, 0); 1418 for (cnt = 0; cnt < 256; cnt++) { 1419 n = 0; 1420 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1421 delay(1000); 1422 if (++n > 1000) { 1423 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1424 break; 1425 } 1426 } 1427 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1428 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1429 } 1430 if (pd) 1431 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1432 } 1433 1434 #if NMIDI > 0 1435 int 1436 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1437 void *addr; 1438 int flags; 1439 void (*iintr)__P((void *, int)); 1440 void (*ointr)__P((void *)); 1441 void *arg; 1442 { 1443 struct cs428x_softc *sc = addr; 1444 u_int32_t mem; 1445 1446 DPRINTF(("midi_open\n")); 1447 sc->sc_iintr = iintr; 1448 sc->sc_ointr = ointr; 1449 sc->sc_arg = arg; 1450 1451 /* midi interrupt enable */ 1452 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1453 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1454 BA0WRITE4(sc, CS4280_MIDCR, mem); 1455 #ifdef CS4280_DEBUG 1456 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1457 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1458 return(EINVAL); 1459 } 1460 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1461 #endif 1462 return 0; 1463 } 1464 1465 void 1466 cs4280_midi_close(addr) 1467 void *addr; 1468 { 1469 struct cs428x_softc *sc = addr; 1470 u_int32_t mem; 1471 1472 DPRINTF(("midi_close\n")); 1473 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1474 mem = BA0READ4(sc, CS4280_MIDCR); 1475 mem &= ~MIDCR_MASK; 1476 BA0WRITE4(sc, CS4280_MIDCR, mem); 1477 1478 sc->sc_iintr = 0; 1479 sc->sc_ointr = 0; 1480 } 1481 1482 int 1483 cs4280_midi_output(addr, d) 1484 void *addr; 1485 int d; 1486 { 1487 struct cs428x_softc *sc = addr; 1488 u_int32_t mem; 1489 int x; 1490 1491 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1492 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1493 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1494 mem |= d & MIDWP_MASK; 1495 DPRINTFN(5,("midi_output d=0x%08x",d)); 1496 BA0WRITE4(sc, CS4280_MIDWP, mem); 1497 #ifdef DIAGNOSTIC 1498 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1499 DPRINTF(("Bad write data: %d %d", 1500 mem, BA0READ4(sc, CS4280_MIDWP))); 1501 return(EIO); 1502 } 1503 #endif 1504 return 0; 1505 } 1506 delay(MIDI_BUSY_DELAY); 1507 } 1508 return (EIO); 1509 } 1510 1511 void 1512 cs4280_midi_getinfo(addr, mi) 1513 void *addr; 1514 struct midi_info *mi; 1515 { 1516 mi->name = "CS4280 MIDI UART"; 1517 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1518 } 1519 1520 #endif 1521 1522 /* DEBUG functions */ 1523 #if CS4280_DEBUG > 10 1524 int 1525 cs4280_checkimage(sc, src, offset, len) 1526 struct cs428x_softc *sc; 1527 u_int32_t *src; 1528 u_int32_t offset, len; 1529 { 1530 u_int32_t ctr, data; 1531 int err = 0; 1532 1533 if ((offset&3) || (len&3)) 1534 return -1; 1535 1536 len /= sizeof(u_int32_t); 1537 for (ctr = 0; ctr < len; ctr++) { 1538 /* I cannot confirm this is the right thing 1539 * on BIG-ENDIAN machines 1540 */ 1541 data = BA1READ4(sc, offset+ctr*4); 1542 if (data != htole32(*(src+ctr))) { 1543 printf("0x%06x: 0x%08x(0x%08x)\n", 1544 offset+ctr*4, data, *(src+ctr)); 1545 *(src+ctr) = data; 1546 ++err; 1547 } 1548 } 1549 return err; 1550 } 1551 1552 int 1553 cs4280_check_images(sc) 1554 struct cs428x_softc *sc; 1555 { 1556 int idx, err; 1557 u_int32_t offset = 0; 1558 1559 err = 0; 1560 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1561 for (idx = 0; idx < 1; ++idx) { 1562 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1563 BA1Struct.memory[idx].offset, 1564 BA1Struct.memory[idx].size); 1565 if (err != 0) { 1566 printf("%s: check_image failed at %d\n", 1567 sc->sc_dev.dv_xname, idx); 1568 } 1569 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1570 } 1571 return err; 1572 } 1573 1574 #endif 1575
Indexes created Thu Oct 02 14:10:14 GMT 2025