cs4280.c revision 1.71
1 /* $NetBSD: cs4280.c,v 1.71 2019/03/16 12:09:58 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.71 2019/03/16 12:09:58 isaki Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/audioio.h> 68 #include <sys/bus.h> 69 #include <sys/bswap.h> 70 71 #include <dev/audio_if.h> 72 #include <dev/midi_if.h> 73 #include <dev/mulaw.h> 74 #include <dev/auconv.h> 75 76 #include <dev/ic/ac97reg.h> 77 #include <dev/ic/ac97var.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/cs4280reg.h> 82 #include <dev/pci/cs4280_image.h> 83 #include <dev/pci/cs428xreg.h> 84 #include <dev/pci/cs428x.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 static int cs4280_match(device_t, cfdata_t, void *); 91 static void cs4280_attach(device_t, device_t, void *); 92 static int cs4280_intr(void *); 93 static int cs4280_query_encoding(void *, struct audio_encoding *); 94 static int cs4280_set_params(void *, int, int, audio_params_t *, 95 audio_params_t *, stream_filter_list_t *, 96 stream_filter_list_t *); 97 static int cs4280_halt_output(void *); 98 static int cs4280_halt_input(void *); 99 static int cs4280_getdev(void *, struct audio_device *); 100 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, const audio_params_t *); 102 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 105 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 106 #if 0 107 static int cs4280_reset_codec(void *); 108 #endif 109 static enum ac97_host_flags cs4280_flags_codec(void *); 110 111 static bool cs4280_resume(device_t, const pmf_qual_t *); 112 static bool cs4280_suspend(device_t, const pmf_qual_t *); 113 114 /* Internal functions */ 115 static const struct cs4280_card_t * cs4280_identify_card( 116 const struct pci_attach_args *); 117 static int cs4280_piix4_match(const struct pci_attach_args *); 118 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 119 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 120 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 121 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 122 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 123 uint32_t); 124 static int cs4280_download_image(struct cs428x_softc *); 125 static void cs4280_reset(void *); 126 static int cs4280_init(struct cs428x_softc *, int); 127 static void cs4280_clear_fifos(struct cs428x_softc *); 128 129 #if CS4280_DEBUG > 10 130 /* Thease two function is only for checking image loading is succeeded or not. */ 131 static int cs4280_check_images(struct cs428x_softc *); 132 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 133 uint32_t); 134 #endif 135 136 /* Special cards */ 137 struct cs4280_card_t 138 { 139 pcireg_t id; 140 enum cs428x_flags flags; 141 }; 142 143 #define _card(vend, prod, flags) \ 144 {PCI_ID_CODE(vend, prod), flags} 145 146 static const struct cs4280_card_t cs4280_cards[] = { 147 #if 0 /* untested, from ALSA driver */ 148 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 149 CS428X_FLAG_INVAC97EAMP), 150 #endif 151 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 152 CS428X_FLAG_INVAC97EAMP), 153 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 154 CS428X_FLAG_CLKRUNHACK) 155 }; 156 157 #undef _card 158 159 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 160 161 static const struct audio_hw_if cs4280_hw_if = { 162 .query_encoding = cs4280_query_encoding, 163 .set_params = cs4280_set_params, 164 .round_blocksize = cs428x_round_blocksize, 165 .halt_output = cs4280_halt_output, 166 .halt_input = cs4280_halt_input, 167 .getdev = cs4280_getdev, 168 .set_port = cs428x_mixer_set_port, 169 .get_port = cs428x_mixer_get_port, 170 .query_devinfo = cs428x_query_devinfo, 171 .allocm = cs428x_malloc, 172 .freem = cs428x_free, 173 .round_buffersize = cs428x_round_buffersize, 174 .mappage = cs428x_mappage, 175 .get_props = cs428x_get_props, 176 .trigger_output = cs4280_trigger_output, 177 .trigger_input = cs4280_trigger_input, 178 .get_locks = cs428x_get_locks, 179 }; 180 181 #if NMIDI > 0 182 /* Midi Interface */ 183 static int cs4280_midi_open(void *, int, void (*)(void *, int), 184 void (*)(void *), void *); 185 static void cs4280_midi_close(void*); 186 static int cs4280_midi_output(void *, int); 187 static void cs4280_midi_getinfo(void *, struct midi_info *); 188 189 static const struct midi_hw_if cs4280_midi_hw_if = { 190 cs4280_midi_open, 191 cs4280_midi_close, 192 cs4280_midi_output, 193 cs4280_midi_getinfo, 194 0, 195 cs428x_get_locks, 196 }; 197 #endif 198 199 CFATTACH_DECL_NEW(clcs, sizeof(struct cs428x_softc), 200 cs4280_match, cs4280_attach, NULL, NULL); 201 202 static struct audio_device cs4280_device = { 203 "CS4280", 204 "", 205 "cs4280" 206 }; 207 208 209 static int 210 cs4280_match(device_t parent, cfdata_t match, void *aux) 211 { 212 struct pci_attach_args *pa; 213 214 pa = (struct pci_attach_args *)aux; 215 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 216 return 0; 217 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 218 #if 0 /* I can't confirm */ 219 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 220 #endif 221 ) 222 return 1; 223 return 0; 224 } 225 226 static void 227 cs4280_attach(device_t parent, device_t self, void *aux) 228 { 229 struct cs428x_softc *sc; 230 struct pci_attach_args *pa; 231 pci_chipset_tag_t pc; 232 const struct cs4280_card_t *cs_card; 233 char const *intrstr; 234 pcireg_t reg; 235 uint32_t mem; 236 int error; 237 char vendor[PCI_VENDORSTR_LEN]; 238 char product[PCI_PRODUCTSTR_LEN]; 239 char intrbuf[PCI_INTRSTR_LEN]; 240 241 sc = device_private(self); 242 sc->sc_dev = self; 243 pa = (struct pci_attach_args *)aux; 244 pc = pa->pa_pc; 245 246 pci_aprint_devinfo(pa, "Audio controller"); 247 248 cs_card = cs4280_identify_card(pa); 249 if (cs_card != NULL) { 250 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(cs_card->id)); 251 pci_findproduct(product, sizeof(product), 252 PCI_VENDOR(cs_card->id), PCI_PRODUCT(cs_card->id)); 253 aprint_normal_dev(sc->sc_dev, "%s %s\n", vendor, product); 254 sc->sc_flags = cs_card->flags; 255 } else { 256 sc->sc_flags = CS428X_FLAG_NONE; 257 } 258 259 sc->sc_pc = pa->pa_pc; 260 sc->sc_pt = pa->pa_tag; 261 262 /* Map I/O register */ 263 if (pci_mapreg_map(pa, PCI_BA0, 264 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 265 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 266 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 267 return; 268 } 269 if (pci_mapreg_map(pa, PCI_BA1, 270 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 271 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 272 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 273 return; 274 } 275 276 sc->sc_dmatag = pa->pa_dmat; 277 278 /* power up chip */ 279 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 280 pci_activate_null)) && error != EOPNOTSUPP) { 281 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 282 return; 283 } 284 285 /* Enable the device (set bus master flag) */ 286 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 287 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 288 reg | PCI_COMMAND_MASTER_ENABLE); 289 290 /* LATENCY_TIMER setting */ 291 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 292 if ( PCI_LATTIMER(mem) < 32 ) { 293 mem &= 0xffff00ff; 294 mem |= 0x00002000; 295 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 296 } 297 298 /* CLKRUN hack initialization */ 299 cs4280_clkrun_hack_init(sc); 300 301 /* Map and establish the interrupt. */ 302 if (pci_intr_map(pa, &sc->intrh)) { 303 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 304 return; 305 } 306 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 307 308 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 309 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 310 311 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->intrh, IPL_AUDIO, 312 cs4280_intr, sc, device_xname(self)); 313 if (sc->sc_ih == NULL) { 314 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 315 if (intrstr != NULL) 316 aprint_error(" at %s", intrstr); 317 aprint_error("\n"); 318 mutex_destroy(&sc->sc_lock); 319 mutex_destroy(&sc->sc_intr_lock); 320 return; 321 } 322 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 323 324 /* Initialization */ 325 if(cs4280_init(sc, 1) != 0) { 326 mutex_destroy(&sc->sc_lock); 327 mutex_destroy(&sc->sc_intr_lock); 328 return; 329 } 330 331 sc->type = TYPE_CS4280; 332 sc->halt_input = cs4280_halt_input; 333 sc->halt_output = cs4280_halt_output; 334 335 /* setup buffer related parameters */ 336 sc->dma_size = CS4280_DCHUNK; 337 sc->dma_align = CS4280_DALIGN; 338 sc->hw_blocksize = CS4280_ICHUNK; 339 340 /* AC 97 attachment */ 341 sc->host_if.arg = sc; 342 sc->host_if.attach = cs428x_attach_codec; 343 sc->host_if.read = cs4280_read_codec; 344 sc->host_if.write = cs4280_write_codec; 345 #if 0 346 sc->host_if.reset = cs4280_reset_codec; 347 #else 348 sc->host_if.reset = NULL; 349 #endif 350 sc->host_if.flags = cs4280_flags_codec; 351 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 352 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 353 return; 354 } 355 356 audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev); 357 358 #if NMIDI > 0 359 midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev); 360 #endif 361 362 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 363 aprint_error_dev(self, "couldn't establish power handler\n"); 364 } 365 366 /* Interrupt handling function */ 367 static int 368 cs4280_intr(void *p) 369 { 370 /* 371 * XXX 372 * 373 * Since CS4280 has only 4kB DMA buffer and 374 * interrupt occurs every 2kB block, I create dummy buffer 375 * which returns to audio driver and actual DMA buffer 376 * using in DMA transfer. 377 * 378 * 379 * ring buffer in audio.c is pointed by BUFADDR 380 * <------ ring buffer size == 64kB ------> 381 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 382 * |= = = =|= = = =|= = = =|= = = =|= = = =| 383 * | | | | | | <- call audio_intp every 384 * sc->sc_[pr]_count time. 385 * 386 * actual DMA buffer is pointed by KERNADDR 387 * <-> DMA buffer size = 4kB 388 * |= =| 389 * 390 * 391 */ 392 struct cs428x_softc *sc; 393 uint32_t intr, mem; 394 char * empty_dma; 395 int handled; 396 397 sc = p; 398 handled = 0; 399 400 mutex_spin_enter(&sc->sc_intr_lock); 401 402 /* grab interrupt register then clear it */ 403 intr = BA0READ4(sc, CS4280_HISR); 404 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 405 406 /* not for us ? */ 407 if ((intr & HISR_INTENA) == 0) { 408 mutex_spin_exit(&sc->sc_intr_lock); 409 return 0; 410 } 411 412 /* Playback Interrupt */ 413 if (intr & HISR_PINT) { 414 handled = 1; 415 mem = BA1READ4(sc, CS4280_PFIE); 416 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 417 if (sc->sc_prun) { 418 if ((sc->sc_pi%sc->sc_pcount) == 0) 419 sc->sc_pintr(sc->sc_parg); 420 /* copy buffer */ 421 ++sc->sc_pi; 422 empty_dma = sc->sc_pdma->addr; 423 if (sc->sc_pi&1) 424 empty_dma += sc->hw_blocksize; 425 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 426 sc->sc_pn += sc->hw_blocksize; 427 if (sc->sc_pn >= sc->sc_pe) 428 sc->sc_pn = sc->sc_ps; 429 } else { 430 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 431 } 432 BA1WRITE4(sc, CS4280_PFIE, mem); 433 } 434 /* Capture Interrupt */ 435 if (intr & HISR_CINT) { 436 int i; 437 int16_t rdata; 438 439 handled = 1; 440 mem = BA1READ4(sc, CS4280_CIE); 441 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 442 443 if (sc->sc_rrun) { 444 ++sc->sc_ri; 445 empty_dma = sc->sc_rdma->addr; 446 if ((sc->sc_ri&1) == 0) 447 empty_dma += sc->hw_blocksize; 448 449 /* 450 * XXX 451 * I think this audio data conversion should be 452 * happend in upper layer, but I put this here 453 * since there is no conversion function available. 454 */ 455 switch(sc->sc_rparam) { 456 case CF_16BIT_STEREO: 457 /* just copy it */ 458 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 459 sc->sc_rn += sc->hw_blocksize; 460 break; 461 case CF_16BIT_MONO: 462 for (i = 0; i < 512; i++) { 463 rdata = *((int16_t *)empty_dma)>>1; 464 empty_dma += 2; 465 rdata += *((int16_t *)empty_dma)>>1; 466 empty_dma += 2; 467 *((int16_t *)sc->sc_rn) = rdata; 468 sc->sc_rn += 2; 469 } 470 break; 471 case CF_8BIT_STEREO: 472 for (i = 0; i < 512; i++) { 473 rdata = *((int16_t*)empty_dma); 474 empty_dma += 2; 475 *sc->sc_rn++ = rdata >> 8; 476 rdata = *((int16_t*)empty_dma); 477 empty_dma += 2; 478 *sc->sc_rn++ = rdata >> 8; 479 } 480 break; 481 case CF_8BIT_MONO: 482 for (i = 0; i < 512; i++) { 483 rdata = *((int16_t*)empty_dma) >>1; 484 empty_dma += 2; 485 rdata += *((int16_t*)empty_dma) >>1; 486 empty_dma += 2; 487 *sc->sc_rn++ = rdata >>8; 488 } 489 break; 490 default: 491 /* Should not reach here */ 492 aprint_error_dev(sc->sc_dev, 493 "unknown sc->sc_rparam: %d\n", 494 sc->sc_rparam); 495 } 496 if (sc->sc_rn >= sc->sc_re) 497 sc->sc_rn = sc->sc_rs; 498 } 499 BA1WRITE4(sc, CS4280_CIE, mem); 500 501 if (sc->sc_rrun) { 502 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 503 sc->sc_rintr(sc->sc_rarg); 504 } else { 505 aprint_error_dev(sc->sc_dev, 506 "unexpected record intr\n"); 507 } 508 } 509 510 #if NMIDI > 0 511 /* Midi port Interrupt */ 512 if (intr & HISR_MIDI) { 513 int data; 514 515 handled = 1; 516 DPRINTF(("i: %d: ", 517 BA0READ4(sc, CS4280_MIDSR))); 518 /* Read the received data */ 519 while ((sc->sc_iintr != NULL) && 520 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 521 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 522 DPRINTF(("r:%x\n",data)); 523 sc->sc_iintr(sc->sc_arg, data); 524 } 525 526 /* Write the data */ 527 #if 1 528 /* XXX: 529 * It seems "Transmit Buffer Full" never activate until EOI 530 * is deliverd. Shall I throw EOI top of this routine ? 531 */ 532 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 533 DPRINTF(("w: ")); 534 if (sc->sc_ointr != NULL) 535 sc->sc_ointr(sc->sc_arg); 536 } 537 #else 538 while ((sc->sc_ointr != NULL) && 539 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 540 DPRINTF(("w: ")); 541 sc->sc_ointr(sc->sc_arg); 542 } 543 #endif 544 DPRINTF(("\n")); 545 } 546 #endif 547 548 mutex_spin_exit(&sc->sc_intr_lock); 549 return handled; 550 } 551 552 static int 553 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 554 { 555 switch (fp->index) { 556 case 0: 557 strcpy(fp->name, AudioEulinear); 558 fp->encoding = AUDIO_ENCODING_ULINEAR; 559 fp->precision = 8; 560 fp->flags = 0; 561 break; 562 case 1: 563 strcpy(fp->name, AudioEmulaw); 564 fp->encoding = AUDIO_ENCODING_ULAW; 565 fp->precision = 8; 566 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 567 break; 568 case 2: 569 strcpy(fp->name, AudioEalaw); 570 fp->encoding = AUDIO_ENCODING_ALAW; 571 fp->precision = 8; 572 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 573 break; 574 case 3: 575 strcpy(fp->name, AudioEslinear); 576 fp->encoding = AUDIO_ENCODING_SLINEAR; 577 fp->precision = 8; 578 fp->flags = 0; 579 break; 580 case 4: 581 strcpy(fp->name, AudioEslinear_le); 582 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 583 fp->precision = 16; 584 fp->flags = 0; 585 break; 586 case 5: 587 strcpy(fp->name, AudioEulinear_le); 588 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 589 fp->precision = 16; 590 fp->flags = 0; 591 break; 592 case 6: 593 strcpy(fp->name, AudioEslinear_be); 594 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 595 fp->precision = 16; 596 fp->flags = 0; 597 break; 598 case 7: 599 strcpy(fp->name, AudioEulinear_be); 600 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 601 fp->precision = 16; 602 fp->flags = 0; 603 break; 604 default: 605 return EINVAL; 606 } 607 return 0; 608 } 609 610 static int 611 cs4280_set_params(void *addr, int setmode, int usemode, 612 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 613 stream_filter_list_t *rfil) 614 { 615 audio_params_t hw; 616 struct cs428x_softc *sc; 617 struct audio_params *p; 618 stream_filter_list_t *fil; 619 int mode; 620 621 sc = addr; 622 for (mode = AUMODE_RECORD; mode != -1; 623 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 624 if ((setmode & mode) == 0) 625 continue; 626 627 p = mode == AUMODE_PLAY ? play : rec; 628 629 if (p == play) { 630 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 631 p->sample_rate, p->precision, p->channels)); 632 /* play back data format may be 8- or 16-bit and 633 * either stereo or mono. 634 * playback rate may range from 8000Hz to 48000Hz 635 */ 636 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 637 (p->precision != 8 && p->precision != 16) || 638 (p->channels != 1 && p->channels != 2) ) { 639 return EINVAL; 640 } 641 } else { 642 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 643 p->sample_rate, p->precision, p->channels)); 644 /* capture data format must be 16bit stereo 645 * and sample rate range from 11025Hz to 48000Hz. 646 * 647 * XXX: it looks like to work with 8000Hz, 648 * although data sheets say lower limit is 649 * 11025 Hz. 650 */ 651 652 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 653 (p->precision != 8 && p->precision != 16) || 654 (p->channels != 1 && p->channels != 2) ) { 655 return EINVAL; 656 } 657 } 658 fil = mode == AUMODE_PLAY ? pfil : rfil; 659 hw = *p; 660 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 661 662 /* capturing data is slinear */ 663 switch (p->encoding) { 664 case AUDIO_ENCODING_SLINEAR_BE: 665 if (mode == AUMODE_RECORD && p->precision == 16) { 666 fil->append(fil, swap_bytes, &hw); 667 } 668 break; 669 case AUDIO_ENCODING_SLINEAR_LE: 670 break; 671 case AUDIO_ENCODING_ULINEAR_BE: 672 if (mode == AUMODE_RECORD) { 673 fil->append(fil, p->precision == 16 674 ? swap_bytes_change_sign16 675 : change_sign8, &hw); 676 } 677 break; 678 case AUDIO_ENCODING_ULINEAR_LE: 679 if (mode == AUMODE_RECORD) { 680 fil->append(fil, p->precision == 16 681 ? change_sign16 : change_sign8, 682 &hw); 683 } 684 break; 685 case AUDIO_ENCODING_ULAW: 686 if (mode == AUMODE_PLAY) { 687 hw.precision = 16; 688 hw.validbits = 16; 689 fil->append(fil, mulaw_to_linear16, &hw); 690 } else { 691 fil->append(fil, linear8_to_mulaw, &hw); 692 } 693 break; 694 case AUDIO_ENCODING_ALAW: 695 if (mode == AUMODE_PLAY) { 696 hw.precision = 16; 697 hw.validbits = 16; 698 fil->append(fil, alaw_to_linear16, &hw); 699 } else { 700 fil->append(fil, linear8_to_alaw, &hw); 701 } 702 break; 703 default: 704 return EINVAL; 705 } 706 } 707 708 /* set sample rate */ 709 cs4280_set_dac_rate(sc, play->sample_rate); 710 cs4280_set_adc_rate(sc, rec->sample_rate); 711 return 0; 712 } 713 714 static int 715 cs4280_halt_output(void *addr) 716 { 717 struct cs428x_softc *sc; 718 uint32_t mem; 719 720 sc = addr; 721 mem = BA1READ4(sc, CS4280_PCTL); 722 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 723 sc->sc_prun = 0; 724 cs4280_clkrun_hack(sc, -1); 725 726 return 0; 727 } 728 729 static int 730 cs4280_halt_input(void *addr) 731 { 732 struct cs428x_softc *sc; 733 uint32_t mem; 734 735 sc = addr; 736 mem = BA1READ4(sc, CS4280_CCTL); 737 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 738 sc->sc_rrun = 0; 739 cs4280_clkrun_hack(sc, -1); 740 741 return 0; 742 } 743 744 static int 745 cs4280_getdev(void *addr, struct audio_device *retp) 746 { 747 748 *retp = cs4280_device; 749 return 0; 750 } 751 752 static int 753 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 754 void (*intr)(void *), void *arg, 755 const audio_params_t *param) 756 { 757 struct cs428x_softc *sc; 758 uint32_t pfie, pctl, pdtc; 759 struct cs428x_dma *p; 760 761 sc = addr; 762 #ifdef DIAGNOSTIC 763 if (sc->sc_prun) 764 printf("cs4280_trigger_output: already running\n"); 765 #endif 766 sc->sc_prun = 1; 767 cs4280_clkrun_hack(sc, 1); 768 769 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 770 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 771 sc->sc_pintr = intr; 772 sc->sc_parg = arg; 773 774 /* stop playback DMA */ 775 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 776 777 /* setup PDTC */ 778 pdtc = BA1READ4(sc, CS4280_PDTC); 779 pdtc &= ~PDTC_MASK; 780 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 781 BA1WRITE4(sc, CS4280_PDTC, pdtc); 782 783 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 784 param->precision, param->channels, param->encoding)); 785 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 786 continue; 787 if (p == NULL) { 788 printf("cs4280_trigger_output: bad addr %p\n", start); 789 return EINVAL; 790 } 791 if (DMAADDR(p) % sc->dma_align != 0 ) { 792 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 793 "4kB align\n", (ulong)DMAADDR(p)); 794 return EINVAL; 795 } 796 797 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 798 sc->sc_ps = (char *)start; 799 sc->sc_pe = (char *)end; 800 sc->sc_pdma = p; 801 sc->sc_pbuf = KERNADDR(p); 802 sc->sc_pi = 0; 803 sc->sc_pn = sc->sc_ps; 804 if (blksize >= sc->dma_size) { 805 sc->sc_pn = sc->sc_ps + sc->dma_size; 806 memcpy(sc->sc_pbuf, start, sc->dma_size); 807 ++sc->sc_pi; 808 } else { 809 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 810 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 811 } 812 813 /* initiate playback DMA */ 814 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 815 816 /* set PFIE */ 817 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 818 819 if (param->precision == 8) 820 pfie |= PFIE_8BIT; 821 if (param->channels == 1) 822 pfie |= PFIE_MONO; 823 824 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 825 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 826 pfie |= PFIE_SWAPPED; 827 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 828 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 829 pfie |= PFIE_UNSIGNED; 830 831 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 832 833 sc->sc_prate = param->sample_rate; 834 cs4280_set_dac_rate(sc, param->sample_rate); 835 836 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 837 pctl |= sc->pctl; 838 BA1WRITE4(sc, CS4280_PCTL, pctl); 839 return 0; 840 } 841 842 static int 843 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 844 void (*intr)(void *), void *arg, 845 const audio_params_t *param) 846 { 847 struct cs428x_softc *sc; 848 uint32_t cctl, cie; 849 struct cs428x_dma *p; 850 851 sc = addr; 852 #ifdef DIAGNOSTIC 853 if (sc->sc_rrun) 854 printf("cs4280_trigger_input: already running\n"); 855 #endif 856 sc->sc_rrun = 1; 857 cs4280_clkrun_hack(sc, 1); 858 859 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 860 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 861 sc->sc_rintr = intr; 862 sc->sc_rarg = arg; 863 864 /* stop capture DMA */ 865 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 866 867 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 868 continue; 869 if (p == NULL) { 870 printf("cs4280_trigger_input: bad addr %p\n", start); 871 return EINVAL; 872 } 873 if (DMAADDR(p) % sc->dma_align != 0) { 874 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 875 "4kB align\n", (ulong)DMAADDR(p)); 876 return EINVAL; 877 } 878 879 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 880 sc->sc_rs = (char *)start; 881 sc->sc_re = (char *)end; 882 sc->sc_rdma = p; 883 sc->sc_rbuf = KERNADDR(p); 884 sc->sc_ri = 0; 885 sc->sc_rn = sc->sc_rs; 886 887 /* initiate capture DMA */ 888 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 889 890 /* setup format information for internal converter */ 891 sc->sc_rparam = 0; 892 if (param->precision == 8) { 893 sc->sc_rparam += CF_8BIT; 894 sc->sc_rcount <<= 1; 895 } 896 if (param->channels == 1) { 897 sc->sc_rparam += CF_MONO; 898 sc->sc_rcount <<= 1; 899 } 900 901 /* set CIE */ 902 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 903 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 904 905 sc->sc_rrate = param->sample_rate; 906 cs4280_set_adc_rate(sc, param->sample_rate); 907 908 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 909 cctl |= sc->cctl; 910 BA1WRITE4(sc, CS4280_CCTL, cctl); 911 return 0; 912 } 913 914 static bool 915 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 916 { 917 struct cs428x_softc *sc = device_private(dv); 918 919 mutex_exit(&sc->sc_lock); 920 mutex_spin_enter(&sc->sc_intr_lock); 921 922 if (sc->sc_prun) { 923 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 924 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 925 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 926 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 927 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 928 sc->sc_suspend_state.cs4280.pctl, 929 sc->sc_suspend_state.cs4280.pfie, 930 sc->sc_suspend_state.cs4280.pba, 931 sc->sc_suspend_state.cs4280.pdtc)); 932 } 933 934 /* save current capture status */ 935 if (sc->sc_rrun) { 936 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 937 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 938 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 939 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 940 sc->sc_suspend_state.cs4280.cctl, 941 sc->sc_suspend_state.cs4280.cie, 942 sc->sc_suspend_state.cs4280.cba)); 943 } 944 945 /* Stop DMA */ 946 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 947 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 948 949 mutex_spin_exit(&sc->sc_intr_lock); 950 mutex_exit(&sc->sc_lock); 951 952 return true; 953 } 954 955 static bool 956 cs4280_resume(device_t dv, const pmf_qual_t *qual) 957 { 958 struct cs428x_softc *sc = device_private(dv); 959 960 mutex_exit(&sc->sc_lock); 961 mutex_spin_enter(&sc->sc_intr_lock); 962 cs4280_init(sc, 0); 963 #if 0 964 cs4280_reset_codec(sc); 965 #endif 966 967 /* restore DMA related status */ 968 if(sc->sc_prun) { 969 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 970 sc->sc_suspend_state.cs4280.pctl, 971 sc->sc_suspend_state.cs4280.pfie, 972 sc->sc_suspend_state.cs4280.pba, 973 sc->sc_suspend_state.cs4280.pdtc)); 974 cs4280_set_dac_rate(sc, sc->sc_prate); 975 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 976 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 977 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 978 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 979 } 980 981 if (sc->sc_rrun) { 982 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 983 sc->sc_suspend_state.cs4280.cctl, 984 sc->sc_suspend_state.cs4280.cie, 985 sc->sc_suspend_state.cs4280.cba)); 986 cs4280_set_adc_rate(sc, sc->sc_rrate); 987 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 988 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 989 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 990 } 991 992 mutex_spin_exit(&sc->sc_intr_lock); 993 994 /* restore ac97 registers */ 995 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 996 997 mutex_exit(&sc->sc_lock); 998 999 return true; 1000 } 1001 1002 static int 1003 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 1004 { 1005 struct cs428x_softc *sc = addr; 1006 int rv; 1007 1008 cs4280_clkrun_hack(sc, 1); 1009 rv = cs428x_read_codec(addr, reg, result); 1010 cs4280_clkrun_hack(sc, -1); 1011 1012 return rv; 1013 } 1014 1015 static int 1016 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1017 { 1018 struct cs428x_softc *sc = addr; 1019 int rv; 1020 1021 cs4280_clkrun_hack(sc, 1); 1022 rv = cs428x_write_codec(addr, reg, data); 1023 cs4280_clkrun_hack(sc, -1); 1024 1025 return rv; 1026 } 1027 1028 #if 0 /* XXX buggy and not required */ 1029 /* control AC97 codec */ 1030 static int 1031 cs4280_reset_codec(void *addr) 1032 { 1033 struct cs428x_softc *sc; 1034 int n; 1035 1036 sc = addr; 1037 1038 /* Reset codec */ 1039 BA0WRITE4(sc, CS428X_ACCTL, 0); 1040 delay(100); /* delay 100us */ 1041 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1042 1043 /* 1044 * It looks like we do the following procedure, too 1045 */ 1046 1047 /* Enable AC-link sync generation */ 1048 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1049 delay(50*1000); /* XXX delay 50ms */ 1050 1051 /* Assert valid frame signal */ 1052 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1053 1054 /* Wait for valid AC97 input slot */ 1055 n = 0; 1056 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1057 (ACISV_ISV3 | ACISV_ISV4)) { 1058 delay(1000); 1059 if (++n > 1000) { 1060 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1061 return ETIMEDOUT; 1062 } 1063 } 1064 1065 return 0; 1066 } 1067 #endif 1068 1069 static enum ac97_host_flags 1070 cs4280_flags_codec(void *addr) 1071 { 1072 struct cs428x_softc *sc; 1073 1074 sc = addr; 1075 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1076 return AC97_HOST_INVERTED_EAMP; 1077 1078 return 0; 1079 } 1080 1081 /* Internal functions */ 1082 1083 static const struct cs4280_card_t * 1084 cs4280_identify_card(const struct pci_attach_args *pa) 1085 { 1086 pcireg_t idreg; 1087 u_int16_t i; 1088 1089 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1090 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1091 if (idreg == cs4280_cards[i].id) 1092 return &cs4280_cards[i]; 1093 } 1094 1095 return NULL; 1096 } 1097 1098 static int 1099 cs4280_piix4_match(const struct pci_attach_args *pa) 1100 { 1101 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1102 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1103 return 1; 1104 } 1105 1106 return 0; 1107 } 1108 1109 static void 1110 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1111 { 1112 uint16_t control, val; 1113 1114 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1115 return; 1116 1117 sc->sc_active += change; 1118 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1119 if (!sc->sc_active) 1120 val |= 0x2000; 1121 else 1122 val &= ~0x2000; 1123 if (val != control) 1124 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1125 } 1126 1127 static void 1128 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1129 { 1130 struct pci_attach_args smbuspa; 1131 uint16_t reg; 1132 pcireg_t port; 1133 1134 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1135 return; 1136 1137 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1138 sc->sc_active = 0; 1139 aprint_normal_dev(sc->sc_dev, "enabling CLKRUN hack\n"); 1140 1141 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1142 port = reg & 0xffc0; 1143 aprint_normal_dev(sc->sc_dev, "power management port 0x%x\n", 1144 port); 1145 1146 sc->sc_pm_iot = smbuspa.pa_iot; 1147 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1148 &sc->sc_pm_ioh) == 0) 1149 return; 1150 } 1151 1152 /* handle error */ 1153 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1154 aprint_normal_dev(sc->sc_dev, "disabling CLKRUN hack\n"); 1155 } 1156 1157 static void 1158 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1159 { 1160 /* calculate capture rate: 1161 * 1162 * capture_coefficient_increment = -round(rate*128*65536/48000; 1163 * capture_phase_increment = floor(48000*65536*1024/rate); 1164 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1165 * cy = floor(cx/200); 1166 * capture_sample_rate_correction = cx - 200*cy; 1167 * capture_delay = ceil(24*48000/rate); 1168 * capture_num_triplets = floor(65536*rate/24000); 1169 * capture_group_length = 24000/GCD(rate, 24000); 1170 * where GCD means "Greatest Common Divisor". 1171 * 1172 * capture_coefficient_increment, capture_phase_increment and 1173 * capture_num_triplets are 32-bit signed quantities. 1174 * capture_sample_rate_correction and capture_group_length are 1175 * 16-bit signed quantities. 1176 * capture_delay is a 14-bit unsigned quantity. 1177 */ 1178 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1179 uint16_t csrc, cgl, cdlay; 1180 1181 /* XXX 1182 * Even though, embedded_audio_spec says capture rate range 11025 to 1183 * 48000, dhwiface.cpp says, 1184 * 1185 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1186 * Return an error if an attempt is made to stray outside that limit." 1187 * 1188 * so assume range as 48000/9 to 48000 1189 */ 1190 1191 if (rate < 8000) 1192 rate = 8000; 1193 if (rate > 48000) 1194 rate = 48000; 1195 1196 cx = rate << 16; 1197 cci = cx / 48000; 1198 cx -= cci * 48000; 1199 cx <<= 7; 1200 cci <<= 7; 1201 cci += cx / 48000; 1202 cci = - cci; 1203 1204 cx = 48000 << 16; 1205 cpi = cx / rate; 1206 cx -= cpi * rate; 1207 cx <<= 10; 1208 cpi <<= 10; 1209 cy = cx / rate; 1210 cpi += cy; 1211 cx -= cy * rate; 1212 1213 cy = cx / 200; 1214 csrc = cx - 200*cy; 1215 1216 cdlay = ((48000 * 24) + rate - 1) / rate; 1217 #if 0 1218 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1219 #endif 1220 1221 cnt = rate << 16; 1222 cnt /= 24000; 1223 1224 cgl = 1; 1225 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1226 if (((rate / tmp1) * tmp1) != rate) 1227 cgl *= 2; 1228 } 1229 if (((rate / 3) * 3) != rate) 1230 cgl *= 3; 1231 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1232 if (((rate / tmp1) * tmp1) != rate) 1233 cgl *= 5; 1234 } 1235 #if 0 1236 /* XXX what manual says */ 1237 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1238 tmp1 |= csrc<<16; 1239 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1240 #else 1241 /* suggested by cs461x.c (ALSA driver) */ 1242 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1243 #endif 1244 1245 #if 0 1246 /* I am confused. The sample rate calculation section says 1247 * cci *is* 32-bit signed quantity but in the parameter description 1248 * section, CCI only assigned 16bit. 1249 * I believe size of the variable. 1250 */ 1251 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1252 tmp1 |= cci<<16; 1253 BA1WRITE4(sc, CS4280_CCI, tmp1); 1254 #else 1255 BA1WRITE4(sc, CS4280_CCI, cci); 1256 #endif 1257 1258 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1259 tmp1 |= cdlay <<18; 1260 BA1WRITE4(sc, CS4280_CD, tmp1); 1261 1262 BA1WRITE4(sc, CS4280_CPI, cpi); 1263 1264 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1265 tmp1 |= cgl; 1266 BA1WRITE4(sc, CS4280_CGL, tmp1); 1267 1268 BA1WRITE4(sc, CS4280_CNT, cnt); 1269 1270 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1271 tmp1 |= cgl; 1272 BA1WRITE4(sc, CS4280_CGC, tmp1); 1273 } 1274 1275 static void 1276 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1277 { 1278 /* 1279 * playback rate may range from 8000Hz to 48000Hz 1280 * 1281 * play_phase_increment = floor(rate*65536*1024/48000) 1282 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1283 * py=floor(px/200) 1284 * play_sample_rate_correction = px - 200*py 1285 * 1286 * play_phase_increment is a 32bit signed quantity. 1287 * play_sample_rate_correction is a 16bit signed quantity. 1288 */ 1289 int32_t ppi; 1290 int16_t psrc; 1291 uint32_t px, py; 1292 1293 if (rate < 8000) 1294 rate = 8000; 1295 if (rate > 48000) 1296 rate = 48000; 1297 px = rate << 16; 1298 ppi = px/48000; 1299 px -= ppi*48000; 1300 ppi <<= 10; 1301 px <<= 10; 1302 py = px / 48000; 1303 ppi += py; 1304 px -= py*48000; 1305 py = px/200; 1306 px -= py*200; 1307 psrc = px; 1308 #if 0 1309 /* what manual says */ 1310 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1311 BA1WRITE4(sc, CS4280_PSRC, 1312 ( ((psrc<<16) & PSRC_MASK) | px )); 1313 #else 1314 /* suggested by cs461x.c (ALSA driver) */ 1315 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1316 #endif 1317 BA1WRITE4(sc, CS4280_PPI, ppi); 1318 } 1319 1320 /* Download Processor Code and Data image */ 1321 static int 1322 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1323 uint32_t offset, uint32_t len) 1324 { 1325 uint32_t ctr; 1326 #if CS4280_DEBUG > 10 1327 uint32_t con, data; 1328 uint8_t c0, c1, c2, c3; 1329 #endif 1330 if ((offset & 3) || (len & 3)) 1331 return -1; 1332 1333 len /= sizeof(uint32_t); 1334 for (ctr = 0; ctr < len; ctr++) { 1335 /* XXX: 1336 * I cannot confirm this is the right thing or not 1337 * on BIG-ENDIAN machines. 1338 */ 1339 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1340 #if CS4280_DEBUG > 10 1341 data = htole32(*(src+ctr)); 1342 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1343 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1344 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1345 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1346 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1347 if (data != con ) { 1348 printf("0x%06x: write=0x%08x read=0x%08x\n", 1349 offset+ctr*4, data, con); 1350 return -1; 1351 } 1352 #endif 1353 } 1354 return 0; 1355 } 1356 1357 static int 1358 cs4280_download_image(struct cs428x_softc *sc) 1359 { 1360 int idx, err; 1361 uint32_t offset = 0; 1362 1363 err = 0; 1364 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1365 err = cs4280_download(sc, &BA1Struct.map[offset], 1366 BA1Struct.memory[idx].offset, 1367 BA1Struct.memory[idx].size); 1368 if (err != 0) { 1369 aprint_error_dev(sc->sc_dev, 1370 "load_image failed at %d\n", idx); 1371 return -1; 1372 } 1373 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1374 } 1375 return err; 1376 } 1377 1378 /* Processor Soft Reset */ 1379 static void 1380 cs4280_reset(void *sc_) 1381 { 1382 struct cs428x_softc *sc; 1383 1384 sc = sc_; 1385 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1386 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1387 delay(100); 1388 /* Clear RSTSP bit in SPCR */ 1389 BA1WRITE4(sc, CS4280_SPCR, 0); 1390 /* enable DMA reqest */ 1391 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1392 } 1393 1394 static int 1395 cs4280_init(struct cs428x_softc *sc, int init) 1396 { 1397 int n; 1398 uint32_t mem; 1399 int rv; 1400 1401 rv = 1; 1402 cs4280_clkrun_hack(sc, 1); 1403 1404 /* Start PLL out in known state */ 1405 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1406 /* Start serial ports out in known state */ 1407 BA0WRITE4(sc, CS4280_SERMC1, 0); 1408 1409 /* Specify type of CODEC */ 1410 /* XXX should not be here */ 1411 #define SERACC_CODEC_TYPE_1_03 1412 #ifdef SERACC_CODEC_TYPE_1_03 1413 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1414 #else 1415 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1416 #endif 1417 1418 /* Reset codec */ 1419 BA0WRITE4(sc, CS428X_ACCTL, 0); 1420 delay(100); /* delay 100us */ 1421 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1422 1423 /* Enable AC-link sync generation */ 1424 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1425 delay(50*1000); /* delay 50ms */ 1426 1427 /* Set the serial port timing configuration */ 1428 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1429 1430 /* Setup clock control */ 1431 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1432 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1433 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1434 1435 /* Power up the PLL */ 1436 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1437 delay(50*1000); /* delay 50ms */ 1438 1439 /* Turn on clock */ 1440 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1441 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1442 1443 /* Set the serial port FIFO pointer to the 1444 * first sample in FIFO. (not documented) */ 1445 cs4280_clear_fifos(sc); 1446 1447 #if 0 1448 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1449 BA0WRITE4(sc, CS4280_SERBSP, 0); 1450 #endif 1451 1452 /* Configure the serial port */ 1453 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1454 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1455 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1456 1457 /* Wait for CODEC ready */ 1458 n = 0; 1459 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1460 delay(125); 1461 if (++n > 1000) { 1462 aprint_error_dev(sc->sc_dev, "codec ready timeout\n"); 1463 goto exit; 1464 } 1465 } 1466 1467 /* Assert valid frame signal */ 1468 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1469 1470 /* Wait for valid AC97 input slot */ 1471 n = 0; 1472 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1473 (ACISV_ISV3 | ACISV_ISV4)) { 1474 delay(1000); 1475 if (++n > 1000) { 1476 printf("AC97 inputs slot ready timeout\n"); 1477 goto exit; 1478 } 1479 } 1480 1481 /* Set AC97 output slot valid signals */ 1482 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1483 1484 /* reset the processor */ 1485 cs4280_reset(sc); 1486 1487 /* Download the image to the processor */ 1488 if (cs4280_download_image(sc) != 0) { 1489 aprint_error_dev(sc->sc_dev, "image download error\n"); 1490 goto exit; 1491 } 1492 1493 /* Save playback parameter and then write zero. 1494 * this ensures that DMA doesn't immediately occur upon 1495 * starting the processor core 1496 */ 1497 mem = BA1READ4(sc, CS4280_PCTL); 1498 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1499 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1500 if (init != 0) 1501 sc->sc_prun = 0; 1502 1503 /* Save capture parameter and then write zero. 1504 * this ensures that DMA doesn't immediately occur upon 1505 * starting the processor core 1506 */ 1507 mem = BA1READ4(sc, CS4280_CCTL); 1508 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1509 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1510 if (init != 0) 1511 sc->sc_rrun = 0; 1512 1513 /* Processor Startup Procedure */ 1514 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1515 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1516 1517 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1518 n = 0; 1519 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1520 delay(10); 1521 if (++n > 1000) { 1522 printf("SPCR 1->0 transition timeout\n"); 1523 goto exit; 1524 } 1525 } 1526 1527 n = 0; 1528 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1529 delay(10); 1530 if (++n > 1000) { 1531 printf("SPCS 0->1 transition timeout\n"); 1532 goto exit; 1533 } 1534 } 1535 /* Processor is now running !!! */ 1536 1537 /* Setup volume */ 1538 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1539 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1540 1541 /* Interrupt enable */ 1542 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1543 1544 /* playback interrupt enable */ 1545 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1546 mem |= PFIE_PI_ENABLE; 1547 BA1WRITE4(sc, CS4280_PFIE, mem); 1548 /* capture interrupt enable */ 1549 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1550 mem |= CIE_CI_ENABLE; 1551 BA1WRITE4(sc, CS4280_CIE, mem); 1552 1553 #if NMIDI > 0 1554 /* Reset midi port */ 1555 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1556 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1557 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1558 /* midi interrupt enable */ 1559 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1560 BA0WRITE4(sc, CS4280_MIDCR, mem); 1561 #endif 1562 1563 rv = 0; 1564 1565 exit: 1566 cs4280_clkrun_hack(sc, -1); 1567 return rv; 1568 } 1569 1570 static void 1571 cs4280_clear_fifos(struct cs428x_softc *sc) 1572 { 1573 int pd, cnt, n; 1574 uint32_t mem; 1575 1576 pd = 0; 1577 /* 1578 * If device power down, power up the device and keep power down 1579 * state. 1580 */ 1581 mem = BA0READ4(sc, CS4280_CLKCR1); 1582 if (!(mem & CLKCR1_SWCE)) { 1583 printf("cs4280_clear_fifo: power down found.\n"); 1584 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1585 pd = 1; 1586 } 1587 BA0WRITE4(sc, CS4280_SERBWP, 0); 1588 for (cnt = 0; cnt < 256; cnt++) { 1589 n = 0; 1590 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1591 delay(1000); 1592 if (++n > 1000) { 1593 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1594 break; 1595 } 1596 } 1597 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1598 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1599 } 1600 if (pd) 1601 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1602 } 1603 1604 #if NMIDI > 0 1605 static int 1606 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1607 void (*ointr)(void *), void *arg) 1608 { 1609 struct cs428x_softc *sc; 1610 uint32_t mem; 1611 1612 DPRINTF(("midi_open\n")); 1613 sc = addr; 1614 sc->sc_iintr = iintr; 1615 sc->sc_ointr = ointr; 1616 sc->sc_arg = arg; 1617 1618 /* midi interrupt enable */ 1619 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1620 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1621 BA0WRITE4(sc, CS4280_MIDCR, mem); 1622 #ifdef CS4280_DEBUG 1623 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1624 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1625 return(EINVAL); 1626 } 1627 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1628 #endif 1629 return 0; 1630 } 1631 1632 static void 1633 cs4280_midi_close(void *addr) 1634 { 1635 struct cs428x_softc *sc; 1636 uint32_t mem; 1637 1638 DPRINTF(("midi_close\n")); 1639 sc = addr; 1640 /* give uart a chance to drain */ 1641 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1642 mem = BA0READ4(sc, CS4280_MIDCR); 1643 mem &= ~MIDCR_MASK; 1644 BA0WRITE4(sc, CS4280_MIDCR, mem); 1645 1646 sc->sc_iintr = 0; 1647 sc->sc_ointr = 0; 1648 } 1649 1650 static int 1651 cs4280_midi_output(void *addr, int d) 1652 { 1653 struct cs428x_softc *sc; 1654 uint32_t mem; 1655 int x; 1656 1657 sc = addr; 1658 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1659 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1660 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1661 mem |= d & MIDWP_MASK; 1662 DPRINTFN(5,("midi_output d=0x%08x",d)); 1663 BA0WRITE4(sc, CS4280_MIDWP, mem); 1664 #ifdef DIAGNOSTIC 1665 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1666 DPRINTF(("Bad write data: %d %d", 1667 mem, BA0READ4(sc, CS4280_MIDWP))); 1668 return EIO; 1669 } 1670 #endif 1671 return 0; 1672 } 1673 delay(MIDI_BUSY_DELAY); 1674 } 1675 return EIO; 1676 } 1677 1678 static void 1679 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1680 { 1681 1682 mi->name = "CS4280 MIDI UART"; 1683 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1684 } 1685 1686 #endif /* NMIDI */ 1687 1688 /* DEBUG functions */ 1689 #if CS4280_DEBUG > 10 1690 static int 1691 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1692 uint32_t offset, uint32_t len) 1693 { 1694 uint32_t ctr, data; 1695 int err; 1696 1697 if ((offset & 3) || (len & 3)) 1698 return -1; 1699 1700 err = 0; 1701 len /= sizeof(uint32_t); 1702 for (ctr = 0; ctr < len; ctr++) { 1703 /* I cannot confirm this is the right thing 1704 * on BIG-ENDIAN machines 1705 */ 1706 data = BA1READ4(sc, offset+ctr*4); 1707 if (data != htole32(*(src+ctr))) { 1708 printf("0x%06x: 0x%08x(0x%08x)\n", 1709 offset+ctr*4, data, *(src+ctr)); 1710 *(src+ctr) = data; 1711 ++err; 1712 } 1713 } 1714 return err; 1715 } 1716 1717 static int 1718 cs4280_check_images(struct cs428x_softc *sc) 1719 { 1720 int idx, err; 1721 uint32_t offset; 1722 1723 offset = 0; 1724 err = 0; 1725 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1726 for (idx = 0; idx < 1; ++idx) { 1727 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1728 BA1Struct.memory[idx].offset, 1729 BA1Struct.memory[idx].size); 1730 if (err != 0) { 1731 aprint_error_dev(sc->sc_dev, 1732 "check_image failed at %d\n", idx); 1733 } 1734 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1735 } 1736 return err; 1737 } 1738 1739 #endif /* CS4280_DEBUG */ 1740
Indexes created Thu Oct 02 14:10:14 GMT 2025