cs4280.c revision 1.71.2.2
1 /* $NetBSD: cs4280.c,v 1.71.2.2 2019/05/04 07:20:10 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.71.2.2 2019/05/04 07:20:10 isaki Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/audioio.h> 68 #include <sys/bus.h> 69 #include <sys/bswap.h> 70 71 #include <dev/audio/audio_if.h> 72 #include <dev/midi_if.h> 73 74 #include <dev/ic/ac97reg.h> 75 #include <dev/ic/ac97var.h> 76 77 #include <dev/pci/pcidevs.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/cs4280reg.h> 80 #include <dev/pci/cs4280_image.h> 81 #include <dev/pci/cs428xreg.h> 82 #include <dev/pci/cs428x.h> 83 84 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 85 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 86 87 /* IF functions for audio driver */ 88 static int cs4280_match(device_t, cfdata_t, void *); 89 static void cs4280_attach(device_t, device_t, void *); 90 static int cs4280_intr(void *); 91 static int cs4280_query_format(void *, audio_format_query_t *); 92 static int cs4280_set_format(void *, int, 93 const audio_params_t *, const audio_params_t *, 94 audio_filter_reg_t *, audio_filter_reg_t *); 95 static int cs4280_halt_output(void *); 96 static int cs4280_halt_input(void *); 97 static int cs4280_getdev(void *, struct audio_device *); 98 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 99 void *, const audio_params_t *); 100 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 101 void *, const audio_params_t *); 102 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 103 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 104 #if 0 105 static int cs4280_reset_codec(void *); 106 #endif 107 static enum ac97_host_flags cs4280_flags_codec(void *); 108 109 static bool cs4280_resume(device_t, const pmf_qual_t *); 110 static bool cs4280_suspend(device_t, const pmf_qual_t *); 111 112 /* Internal functions */ 113 static const struct cs4280_card_t * cs4280_identify_card( 114 const struct pci_attach_args *); 115 static int cs4280_piix4_match(const struct pci_attach_args *); 116 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 117 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 118 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 119 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 120 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 121 uint32_t); 122 static int cs4280_download_image(struct cs428x_softc *); 123 static void cs4280_reset(void *); 124 static int cs4280_init(struct cs428x_softc *, int); 125 static void cs4280_clear_fifos(struct cs428x_softc *); 126 127 #if CS4280_DEBUG > 10 128 /* Thease two function is only for checking image loading is succeeded or not. */ 129 static int cs4280_check_images(struct cs428x_softc *); 130 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 131 uint32_t); 132 #endif 133 134 /* Special cards */ 135 struct cs4280_card_t 136 { 137 pcireg_t id; 138 enum cs428x_flags flags; 139 }; 140 141 #define _card(vend, prod, flags) \ 142 {PCI_ID_CODE(vend, prod), flags} 143 144 static const struct cs4280_card_t cs4280_cards[] = { 145 #if 0 /* untested, from ALSA driver */ 146 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 147 CS428X_FLAG_INVAC97EAMP), 148 #endif 149 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 150 CS428X_FLAG_INVAC97EAMP), 151 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 152 CS428X_FLAG_CLKRUNHACK) 153 }; 154 155 #undef _card 156 157 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 158 159 static const struct audio_hw_if cs4280_hw_if = { 160 .query_format = cs4280_query_format, 161 .set_format = cs4280_set_format, 162 .round_blocksize = cs428x_round_blocksize, 163 .halt_output = cs4280_halt_output, 164 .halt_input = cs4280_halt_input, 165 .getdev = cs4280_getdev, 166 .set_port = cs428x_mixer_set_port, 167 .get_port = cs428x_mixer_get_port, 168 .query_devinfo = cs428x_query_devinfo, 169 .allocm = cs428x_malloc, 170 .freem = cs428x_free, 171 .round_buffersize = cs428x_round_buffersize, 172 .get_props = cs428x_get_props, 173 .trigger_output = cs4280_trigger_output, 174 .trigger_input = cs4280_trigger_input, 175 .get_locks = cs428x_get_locks, 176 }; 177 178 #if NMIDI > 0 179 /* Midi Interface */ 180 static int cs4280_midi_open(void *, int, void (*)(void *, int), 181 void (*)(void *), void *); 182 static void cs4280_midi_close(void*); 183 static int cs4280_midi_output(void *, int); 184 static void cs4280_midi_getinfo(void *, struct midi_info *); 185 186 static const struct midi_hw_if cs4280_midi_hw_if = { 187 cs4280_midi_open, 188 cs4280_midi_close, 189 cs4280_midi_output, 190 cs4280_midi_getinfo, 191 0, 192 cs428x_get_locks, 193 }; 194 #endif 195 196 CFATTACH_DECL_NEW(clcs, sizeof(struct cs428x_softc), 197 cs4280_match, cs4280_attach, NULL, NULL); 198 199 static struct audio_device cs4280_device = { 200 "CS4280", 201 "", 202 "cs4280" 203 }; 204 205 /* 206 * XXX recording must be 16bit stereo and sample rate range from 207 * 11025Hz to 48000Hz. However, it looks like to work with 8000Hz, 208 * although data sheets say lower limit is 11025Hz. 209 * XXX The combination of available formats is complicated, so I use 210 * a common format only. Please fix it if not suitable. 211 */ 212 static const struct audio_format cs4280_formats[] = { 213 { 214 .mode = AUMODE_PLAY | AUMODE_RECORD, 215 .encoding = AUDIO_ENCODING_SLINEAR_LE, 216 .validbits = 16, 217 .precision = 16, 218 .channels = 2, 219 .channel_mask = AUFMT_STEREO, 220 .frequency_type = 0, 221 .frequency = { 8000, 48000 }, 222 } 223 }; 224 #define CS4280_NFORMATS __arraycount(cs4280_formats) 225 226 static int 227 cs4280_match(device_t parent, cfdata_t match, void *aux) 228 { 229 struct pci_attach_args *pa; 230 231 pa = (struct pci_attach_args *)aux; 232 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 233 return 0; 234 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 235 #if 0 /* I can't confirm */ 236 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 237 #endif 238 ) 239 return 1; 240 return 0; 241 } 242 243 static void 244 cs4280_attach(device_t parent, device_t self, void *aux) 245 { 246 struct cs428x_softc *sc; 247 struct pci_attach_args *pa; 248 pci_chipset_tag_t pc; 249 const struct cs4280_card_t *cs_card; 250 char const *intrstr; 251 pcireg_t reg; 252 uint32_t mem; 253 int error; 254 char vendor[PCI_VENDORSTR_LEN]; 255 char product[PCI_PRODUCTSTR_LEN]; 256 char intrbuf[PCI_INTRSTR_LEN]; 257 258 sc = device_private(self); 259 sc->sc_dev = self; 260 pa = (struct pci_attach_args *)aux; 261 pc = pa->pa_pc; 262 263 pci_aprint_devinfo(pa, "Audio controller"); 264 265 cs_card = cs4280_identify_card(pa); 266 if (cs_card != NULL) { 267 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(cs_card->id)); 268 pci_findproduct(product, sizeof(product), 269 PCI_VENDOR(cs_card->id), PCI_PRODUCT(cs_card->id)); 270 aprint_normal_dev(sc->sc_dev, "%s %s\n", vendor, product); 271 sc->sc_flags = cs_card->flags; 272 } else { 273 sc->sc_flags = CS428X_FLAG_NONE; 274 } 275 276 sc->sc_pc = pa->pa_pc; 277 sc->sc_pt = pa->pa_tag; 278 279 /* Map I/O register */ 280 if (pci_mapreg_map(pa, PCI_BA0, 281 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 282 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 283 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 284 return; 285 } 286 if (pci_mapreg_map(pa, PCI_BA1, 287 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 288 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 289 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 290 return; 291 } 292 293 sc->sc_dmatag = pa->pa_dmat; 294 295 /* power up chip */ 296 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 297 pci_activate_null)) && error != EOPNOTSUPP) { 298 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 299 return; 300 } 301 302 /* Enable the device (set bus master flag) */ 303 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 304 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 305 reg | PCI_COMMAND_MASTER_ENABLE); 306 307 /* LATENCY_TIMER setting */ 308 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 309 if ( PCI_LATTIMER(mem) < 32 ) { 310 mem &= 0xffff00ff; 311 mem |= 0x00002000; 312 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 313 } 314 315 /* CLKRUN hack initialization */ 316 cs4280_clkrun_hack_init(sc); 317 318 /* Map and establish the interrupt. */ 319 if (pci_intr_map(pa, &sc->intrh)) { 320 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 321 return; 322 } 323 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 324 325 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 326 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 327 328 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->intrh, IPL_AUDIO, 329 cs4280_intr, sc, device_xname(self)); 330 if (sc->sc_ih == NULL) { 331 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 332 if (intrstr != NULL) 333 aprint_error(" at %s", intrstr); 334 aprint_error("\n"); 335 mutex_destroy(&sc->sc_lock); 336 mutex_destroy(&sc->sc_intr_lock); 337 return; 338 } 339 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 340 341 /* Initialization */ 342 if(cs4280_init(sc, 1) != 0) { 343 mutex_destroy(&sc->sc_lock); 344 mutex_destroy(&sc->sc_intr_lock); 345 return; 346 } 347 348 sc->type = TYPE_CS4280; 349 sc->halt_input = cs4280_halt_input; 350 sc->halt_output = cs4280_halt_output; 351 352 /* setup buffer related parameters */ 353 sc->dma_size = CS4280_DCHUNK; 354 sc->dma_align = CS4280_DALIGN; 355 sc->hw_blocksize = CS4280_ICHUNK; 356 357 /* AC 97 attachment */ 358 sc->host_if.arg = sc; 359 sc->host_if.attach = cs428x_attach_codec; 360 sc->host_if.read = cs4280_read_codec; 361 sc->host_if.write = cs4280_write_codec; 362 #if 0 363 sc->host_if.reset = cs4280_reset_codec; 364 #else 365 sc->host_if.reset = NULL; 366 #endif 367 sc->host_if.flags = cs4280_flags_codec; 368 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 369 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 370 return; 371 } 372 373 audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev); 374 375 #if NMIDI > 0 376 midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev); 377 #endif 378 379 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 380 aprint_error_dev(self, "couldn't establish power handler\n"); 381 } 382 383 /* Interrupt handling function */ 384 static int 385 cs4280_intr(void *p) 386 { 387 /* 388 * XXX 389 * 390 * Since CS4280 has only 4kB DMA buffer and 391 * interrupt occurs every 2kB block, I create dummy buffer 392 * which returns to audio driver and actual DMA buffer 393 * using in DMA transfer. 394 * 395 * 396 * ring buffer in audio.c is pointed by BUFADDR 397 * <------ ring buffer size == 64kB ------> 398 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 399 * |= = = =|= = = =|= = = =|= = = =|= = = =| 400 * | | | | | | <- call audio_intp every 401 * sc->sc_[pr]_count time. 402 * 403 * actual DMA buffer is pointed by KERNADDR 404 * <-> DMA buffer size = 4kB 405 * |= =| 406 * 407 * 408 */ 409 struct cs428x_softc *sc; 410 uint32_t intr, mem; 411 char * empty_dma; 412 int handled; 413 414 sc = p; 415 handled = 0; 416 417 mutex_spin_enter(&sc->sc_intr_lock); 418 419 /* grab interrupt register then clear it */ 420 intr = BA0READ4(sc, CS4280_HISR); 421 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 422 423 /* not for us ? */ 424 if ((intr & HISR_INTENA) == 0) { 425 mutex_spin_exit(&sc->sc_intr_lock); 426 return 0; 427 } 428 429 /* Playback Interrupt */ 430 if (intr & HISR_PINT) { 431 handled = 1; 432 mem = BA1READ4(sc, CS4280_PFIE); 433 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 434 if (sc->sc_prun) { 435 if ((sc->sc_pi%sc->sc_pcount) == 0) 436 sc->sc_pintr(sc->sc_parg); 437 /* copy buffer */ 438 ++sc->sc_pi; 439 empty_dma = sc->sc_pdma->addr; 440 if (sc->sc_pi&1) 441 empty_dma += sc->hw_blocksize; 442 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 443 sc->sc_pn += sc->hw_blocksize; 444 if (sc->sc_pn >= sc->sc_pe) 445 sc->sc_pn = sc->sc_ps; 446 } else { 447 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 448 } 449 BA1WRITE4(sc, CS4280_PFIE, mem); 450 } 451 /* Capture Interrupt */ 452 if (intr & HISR_CINT) { 453 int i; 454 int16_t rdata; 455 456 handled = 1; 457 mem = BA1READ4(sc, CS4280_CIE); 458 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 459 460 if (sc->sc_rrun) { 461 ++sc->sc_ri; 462 empty_dma = sc->sc_rdma->addr; 463 if ((sc->sc_ri&1) == 0) 464 empty_dma += sc->hw_blocksize; 465 466 /* 467 * XXX 468 * I think this audio data conversion should be 469 * happend in upper layer, but I put this here 470 * since there is no conversion function available. 471 */ 472 switch(sc->sc_rparam) { 473 case CF_16BIT_STEREO: 474 /* just copy it */ 475 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 476 sc->sc_rn += sc->hw_blocksize; 477 break; 478 case CF_16BIT_MONO: 479 for (i = 0; i < 512; i++) { 480 rdata = *((int16_t *)empty_dma)>>1; 481 empty_dma += 2; 482 rdata += *((int16_t *)empty_dma)>>1; 483 empty_dma += 2; 484 *((int16_t *)sc->sc_rn) = rdata; 485 sc->sc_rn += 2; 486 } 487 break; 488 case CF_8BIT_STEREO: 489 for (i = 0; i < 512; i++) { 490 rdata = *((int16_t*)empty_dma); 491 empty_dma += 2; 492 *sc->sc_rn++ = rdata >> 8; 493 rdata = *((int16_t*)empty_dma); 494 empty_dma += 2; 495 *sc->sc_rn++ = rdata >> 8; 496 } 497 break; 498 case CF_8BIT_MONO: 499 for (i = 0; i < 512; i++) { 500 rdata = *((int16_t*)empty_dma) >>1; 501 empty_dma += 2; 502 rdata += *((int16_t*)empty_dma) >>1; 503 empty_dma += 2; 504 *sc->sc_rn++ = rdata >>8; 505 } 506 break; 507 default: 508 /* Should not reach here */ 509 aprint_error_dev(sc->sc_dev, 510 "unknown sc->sc_rparam: %d\n", 511 sc->sc_rparam); 512 } 513 if (sc->sc_rn >= sc->sc_re) 514 sc->sc_rn = sc->sc_rs; 515 } 516 BA1WRITE4(sc, CS4280_CIE, mem); 517 518 if (sc->sc_rrun) { 519 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 520 sc->sc_rintr(sc->sc_rarg); 521 } else { 522 aprint_error_dev(sc->sc_dev, 523 "unexpected record intr\n"); 524 } 525 } 526 527 #if NMIDI > 0 528 /* Midi port Interrupt */ 529 if (intr & HISR_MIDI) { 530 int data; 531 532 handled = 1; 533 DPRINTF(("i: %d: ", 534 BA0READ4(sc, CS4280_MIDSR))); 535 /* Read the received data */ 536 while ((sc->sc_iintr != NULL) && 537 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 538 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 539 DPRINTF(("r:%x\n",data)); 540 sc->sc_iintr(sc->sc_arg, data); 541 } 542 543 /* Write the data */ 544 #if 1 545 /* XXX: 546 * It seems "Transmit Buffer Full" never activate until EOI 547 * is deliverd. Shall I throw EOI top of this routine ? 548 */ 549 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 550 DPRINTF(("w: ")); 551 if (sc->sc_ointr != NULL) 552 sc->sc_ointr(sc->sc_arg); 553 } 554 #else 555 while ((sc->sc_ointr != NULL) && 556 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 557 DPRINTF(("w: ")); 558 sc->sc_ointr(sc->sc_arg); 559 } 560 #endif 561 DPRINTF(("\n")); 562 } 563 #endif 564 565 mutex_spin_exit(&sc->sc_intr_lock); 566 return handled; 567 } 568 569 static int 570 cs4280_query_format(void *addr, audio_format_query_t *afp) 571 { 572 573 return audio_query_format(cs4280_formats, CS4280_NFORMATS, afp); 574 } 575 576 static int 577 cs4280_set_format(void *addr, int setmode, 578 const audio_params_t *play, const audio_params_t *rec, 579 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 580 { 581 struct cs428x_softc *sc; 582 583 sc = addr; 584 /* set sample rate */ 585 cs4280_set_dac_rate(sc, play->sample_rate); 586 cs4280_set_adc_rate(sc, rec->sample_rate); 587 return 0; 588 } 589 590 static int 591 cs4280_halt_output(void *addr) 592 { 593 struct cs428x_softc *sc; 594 uint32_t mem; 595 596 sc = addr; 597 mem = BA1READ4(sc, CS4280_PCTL); 598 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 599 sc->sc_prun = 0; 600 cs4280_clkrun_hack(sc, -1); 601 602 return 0; 603 } 604 605 static int 606 cs4280_halt_input(void *addr) 607 { 608 struct cs428x_softc *sc; 609 uint32_t mem; 610 611 sc = addr; 612 mem = BA1READ4(sc, CS4280_CCTL); 613 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 614 sc->sc_rrun = 0; 615 cs4280_clkrun_hack(sc, -1); 616 617 return 0; 618 } 619 620 static int 621 cs4280_getdev(void *addr, struct audio_device *retp) 622 { 623 624 *retp = cs4280_device; 625 return 0; 626 } 627 628 static int 629 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 630 void (*intr)(void *), void *arg, 631 const audio_params_t *param) 632 { 633 struct cs428x_softc *sc; 634 uint32_t pfie, pctl, pdtc; 635 struct cs428x_dma *p; 636 637 sc = addr; 638 #ifdef DIAGNOSTIC 639 if (sc->sc_prun) 640 printf("cs4280_trigger_output: already running\n"); 641 #endif 642 sc->sc_prun = 1; 643 cs4280_clkrun_hack(sc, 1); 644 645 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 646 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 647 sc->sc_pintr = intr; 648 sc->sc_parg = arg; 649 650 /* stop playback DMA */ 651 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 652 653 /* setup PDTC */ 654 pdtc = BA1READ4(sc, CS4280_PDTC); 655 pdtc &= ~PDTC_MASK; 656 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 657 BA1WRITE4(sc, CS4280_PDTC, pdtc); 658 659 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 660 param->precision, param->channels, param->encoding)); 661 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 662 continue; 663 if (p == NULL) { 664 printf("cs4280_trigger_output: bad addr %p\n", start); 665 return EINVAL; 666 } 667 if (DMAADDR(p) % sc->dma_align != 0 ) { 668 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 669 "4kB align\n", (ulong)DMAADDR(p)); 670 return EINVAL; 671 } 672 673 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 674 sc->sc_ps = (char *)start; 675 sc->sc_pe = (char *)end; 676 sc->sc_pdma = p; 677 sc->sc_pbuf = KERNADDR(p); 678 sc->sc_pi = 0; 679 sc->sc_pn = sc->sc_ps; 680 if (blksize >= sc->dma_size) { 681 sc->sc_pn = sc->sc_ps + sc->dma_size; 682 memcpy(sc->sc_pbuf, start, sc->dma_size); 683 ++sc->sc_pi; 684 } else { 685 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 686 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 687 } 688 689 /* initiate playback DMA */ 690 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 691 692 /* set PFIE */ 693 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 694 if (param->encoding == AUDIO_ENCODING_SLINEAR_BE) 695 pfie |= PFIE_SWAPPED; 696 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 697 698 sc->sc_prate = param->sample_rate; 699 cs4280_set_dac_rate(sc, param->sample_rate); 700 701 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 702 pctl |= sc->pctl; 703 BA1WRITE4(sc, CS4280_PCTL, pctl); 704 return 0; 705 } 706 707 static int 708 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 709 void (*intr)(void *), void *arg, 710 const audio_params_t *param) 711 { 712 struct cs428x_softc *sc; 713 uint32_t cctl, cie; 714 struct cs428x_dma *p; 715 716 sc = addr; 717 #ifdef DIAGNOSTIC 718 if (sc->sc_rrun) 719 printf("cs4280_trigger_input: already running\n"); 720 #endif 721 sc->sc_rrun = 1; 722 cs4280_clkrun_hack(sc, 1); 723 724 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 725 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 726 sc->sc_rintr = intr; 727 sc->sc_rarg = arg; 728 729 /* stop capture DMA */ 730 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 731 732 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 733 continue; 734 if (p == NULL) { 735 printf("cs4280_trigger_input: bad addr %p\n", start); 736 return EINVAL; 737 } 738 if (DMAADDR(p) % sc->dma_align != 0) { 739 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 740 "4kB align\n", (ulong)DMAADDR(p)); 741 return EINVAL; 742 } 743 744 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 745 sc->sc_rs = (char *)start; 746 sc->sc_re = (char *)end; 747 sc->sc_rdma = p; 748 sc->sc_rbuf = KERNADDR(p); 749 sc->sc_ri = 0; 750 sc->sc_rn = sc->sc_rs; 751 752 /* initiate capture DMA */ 753 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 754 755 /* setup format information for internal converter */ 756 sc->sc_rparam = 0; 757 if (param->precision == 8) { 758 sc->sc_rparam += CF_8BIT; 759 sc->sc_rcount <<= 1; 760 } 761 if (param->channels == 1) { 762 sc->sc_rparam += CF_MONO; 763 sc->sc_rcount <<= 1; 764 } 765 766 /* set CIE */ 767 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 768 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 769 770 sc->sc_rrate = param->sample_rate; 771 cs4280_set_adc_rate(sc, param->sample_rate); 772 773 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 774 cctl |= sc->cctl; 775 BA1WRITE4(sc, CS4280_CCTL, cctl); 776 return 0; 777 } 778 779 static bool 780 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 781 { 782 struct cs428x_softc *sc = device_private(dv); 783 784 mutex_exit(&sc->sc_lock); 785 mutex_spin_enter(&sc->sc_intr_lock); 786 787 if (sc->sc_prun) { 788 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 789 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 790 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 791 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 792 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 793 sc->sc_suspend_state.cs4280.pctl, 794 sc->sc_suspend_state.cs4280.pfie, 795 sc->sc_suspend_state.cs4280.pba, 796 sc->sc_suspend_state.cs4280.pdtc)); 797 } 798 799 /* save current capture status */ 800 if (sc->sc_rrun) { 801 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 802 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 803 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 804 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 805 sc->sc_suspend_state.cs4280.cctl, 806 sc->sc_suspend_state.cs4280.cie, 807 sc->sc_suspend_state.cs4280.cba)); 808 } 809 810 /* Stop DMA */ 811 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 812 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 813 814 mutex_spin_exit(&sc->sc_intr_lock); 815 mutex_exit(&sc->sc_lock); 816 817 return true; 818 } 819 820 static bool 821 cs4280_resume(device_t dv, const pmf_qual_t *qual) 822 { 823 struct cs428x_softc *sc = device_private(dv); 824 825 mutex_exit(&sc->sc_lock); 826 mutex_spin_enter(&sc->sc_intr_lock); 827 cs4280_init(sc, 0); 828 #if 0 829 cs4280_reset_codec(sc); 830 #endif 831 832 /* restore DMA related status */ 833 if(sc->sc_prun) { 834 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 835 sc->sc_suspend_state.cs4280.pctl, 836 sc->sc_suspend_state.cs4280.pfie, 837 sc->sc_suspend_state.cs4280.pba, 838 sc->sc_suspend_state.cs4280.pdtc)); 839 cs4280_set_dac_rate(sc, sc->sc_prate); 840 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 841 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 842 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 843 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 844 } 845 846 if (sc->sc_rrun) { 847 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 848 sc->sc_suspend_state.cs4280.cctl, 849 sc->sc_suspend_state.cs4280.cie, 850 sc->sc_suspend_state.cs4280.cba)); 851 cs4280_set_adc_rate(sc, sc->sc_rrate); 852 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 853 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 854 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 855 } 856 857 mutex_spin_exit(&sc->sc_intr_lock); 858 859 /* restore ac97 registers */ 860 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 861 862 mutex_exit(&sc->sc_lock); 863 864 return true; 865 } 866 867 static int 868 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 869 { 870 struct cs428x_softc *sc = addr; 871 int rv; 872 873 cs4280_clkrun_hack(sc, 1); 874 rv = cs428x_read_codec(addr, reg, result); 875 cs4280_clkrun_hack(sc, -1); 876 877 return rv; 878 } 879 880 static int 881 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 882 { 883 struct cs428x_softc *sc = addr; 884 int rv; 885 886 cs4280_clkrun_hack(sc, 1); 887 rv = cs428x_write_codec(addr, reg, data); 888 cs4280_clkrun_hack(sc, -1); 889 890 return rv; 891 } 892 893 #if 0 /* XXX buggy and not required */ 894 /* control AC97 codec */ 895 static int 896 cs4280_reset_codec(void *addr) 897 { 898 struct cs428x_softc *sc; 899 int n; 900 901 sc = addr; 902 903 /* Reset codec */ 904 BA0WRITE4(sc, CS428X_ACCTL, 0); 905 delay(100); /* delay 100us */ 906 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 907 908 /* 909 * It looks like we do the following procedure, too 910 */ 911 912 /* Enable AC-link sync generation */ 913 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 914 delay(50*1000); /* XXX delay 50ms */ 915 916 /* Assert valid frame signal */ 917 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 918 919 /* Wait for valid AC97 input slot */ 920 n = 0; 921 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 922 (ACISV_ISV3 | ACISV_ISV4)) { 923 delay(1000); 924 if (++n > 1000) { 925 printf("reset_codec: AC97 inputs slot ready timeout\n"); 926 return ETIMEDOUT; 927 } 928 } 929 930 return 0; 931 } 932 #endif 933 934 static enum ac97_host_flags 935 cs4280_flags_codec(void *addr) 936 { 937 struct cs428x_softc *sc; 938 939 sc = addr; 940 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 941 return AC97_HOST_INVERTED_EAMP; 942 943 return 0; 944 } 945 946 /* Internal functions */ 947 948 static const struct cs4280_card_t * 949 cs4280_identify_card(const struct pci_attach_args *pa) 950 { 951 pcireg_t idreg; 952 u_int16_t i; 953 954 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 955 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 956 if (idreg == cs4280_cards[i].id) 957 return &cs4280_cards[i]; 958 } 959 960 return NULL; 961 } 962 963 static int 964 cs4280_piix4_match(const struct pci_attach_args *pa) 965 { 966 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 967 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 968 return 1; 969 } 970 971 return 0; 972 } 973 974 static void 975 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 976 { 977 uint16_t control, val; 978 979 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 980 return; 981 982 sc->sc_active += change; 983 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 984 if (!sc->sc_active) 985 val |= 0x2000; 986 else 987 val &= ~0x2000; 988 if (val != control) 989 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 990 } 991 992 static void 993 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 994 { 995 struct pci_attach_args smbuspa; 996 uint16_t reg; 997 pcireg_t port; 998 999 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1000 return; 1001 1002 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1003 sc->sc_active = 0; 1004 aprint_normal_dev(sc->sc_dev, "enabling CLKRUN hack\n"); 1005 1006 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1007 port = reg & 0xffc0; 1008 aprint_normal_dev(sc->sc_dev, "power management port 0x%x\n", 1009 port); 1010 1011 sc->sc_pm_iot = smbuspa.pa_iot; 1012 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1013 &sc->sc_pm_ioh) == 0) 1014 return; 1015 } 1016 1017 /* handle error */ 1018 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1019 aprint_normal_dev(sc->sc_dev, "disabling CLKRUN hack\n"); 1020 } 1021 1022 static void 1023 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1024 { 1025 /* calculate capture rate: 1026 * 1027 * capture_coefficient_increment = -round(rate*128*65536/48000; 1028 * capture_phase_increment = floor(48000*65536*1024/rate); 1029 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1030 * cy = floor(cx/200); 1031 * capture_sample_rate_correction = cx - 200*cy; 1032 * capture_delay = ceil(24*48000/rate); 1033 * capture_num_triplets = floor(65536*rate/24000); 1034 * capture_group_length = 24000/GCD(rate, 24000); 1035 * where GCD means "Greatest Common Divisor". 1036 * 1037 * capture_coefficient_increment, capture_phase_increment and 1038 * capture_num_triplets are 32-bit signed quantities. 1039 * capture_sample_rate_correction and capture_group_length are 1040 * 16-bit signed quantities. 1041 * capture_delay is a 14-bit unsigned quantity. 1042 */ 1043 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1044 uint16_t csrc, cgl, cdlay; 1045 1046 /* XXX 1047 * Even though, embedded_audio_spec says capture rate range 11025 to 1048 * 48000, dhwiface.cpp says, 1049 * 1050 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1051 * Return an error if an attempt is made to stray outside that limit." 1052 * 1053 * so assume range as 48000/9 to 48000 1054 */ 1055 1056 if (rate < 8000) 1057 rate = 8000; 1058 if (rate > 48000) 1059 rate = 48000; 1060 1061 cx = rate << 16; 1062 cci = cx / 48000; 1063 cx -= cci * 48000; 1064 cx <<= 7; 1065 cci <<= 7; 1066 cci += cx / 48000; 1067 cci = - cci; 1068 1069 cx = 48000 << 16; 1070 cpi = cx / rate; 1071 cx -= cpi * rate; 1072 cx <<= 10; 1073 cpi <<= 10; 1074 cy = cx / rate; 1075 cpi += cy; 1076 cx -= cy * rate; 1077 1078 cy = cx / 200; 1079 csrc = cx - 200*cy; 1080 1081 cdlay = ((48000 * 24) + rate - 1) / rate; 1082 #if 0 1083 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1084 #endif 1085 1086 cnt = rate << 16; 1087 cnt /= 24000; 1088 1089 cgl = 1; 1090 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1091 if (((rate / tmp1) * tmp1) != rate) 1092 cgl *= 2; 1093 } 1094 if (((rate / 3) * 3) != rate) 1095 cgl *= 3; 1096 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1097 if (((rate / tmp1) * tmp1) != rate) 1098 cgl *= 5; 1099 } 1100 #if 0 1101 /* XXX what manual says */ 1102 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1103 tmp1 |= csrc<<16; 1104 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1105 #else 1106 /* suggested by cs461x.c (ALSA driver) */ 1107 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1108 #endif 1109 1110 #if 0 1111 /* I am confused. The sample rate calculation section says 1112 * cci *is* 32-bit signed quantity but in the parameter description 1113 * section, CCI only assigned 16bit. 1114 * I believe size of the variable. 1115 */ 1116 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1117 tmp1 |= cci<<16; 1118 BA1WRITE4(sc, CS4280_CCI, tmp1); 1119 #else 1120 BA1WRITE4(sc, CS4280_CCI, cci); 1121 #endif 1122 1123 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1124 tmp1 |= cdlay <<18; 1125 BA1WRITE4(sc, CS4280_CD, tmp1); 1126 1127 BA1WRITE4(sc, CS4280_CPI, cpi); 1128 1129 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1130 tmp1 |= cgl; 1131 BA1WRITE4(sc, CS4280_CGL, tmp1); 1132 1133 BA1WRITE4(sc, CS4280_CNT, cnt); 1134 1135 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1136 tmp1 |= cgl; 1137 BA1WRITE4(sc, CS4280_CGC, tmp1); 1138 } 1139 1140 static void 1141 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1142 { 1143 /* 1144 * playback rate may range from 8000Hz to 48000Hz 1145 * 1146 * play_phase_increment = floor(rate*65536*1024/48000) 1147 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1148 * py=floor(px/200) 1149 * play_sample_rate_correction = px - 200*py 1150 * 1151 * play_phase_increment is a 32bit signed quantity. 1152 * play_sample_rate_correction is a 16bit signed quantity. 1153 */ 1154 int32_t ppi; 1155 int16_t psrc; 1156 uint32_t px, py; 1157 1158 if (rate < 8000) 1159 rate = 8000; 1160 if (rate > 48000) 1161 rate = 48000; 1162 px = rate << 16; 1163 ppi = px/48000; 1164 px -= ppi*48000; 1165 ppi <<= 10; 1166 px <<= 10; 1167 py = px / 48000; 1168 ppi += py; 1169 px -= py*48000; 1170 py = px/200; 1171 px -= py*200; 1172 psrc = px; 1173 #if 0 1174 /* what manual says */ 1175 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1176 BA1WRITE4(sc, CS4280_PSRC, 1177 ( ((psrc<<16) & PSRC_MASK) | px )); 1178 #else 1179 /* suggested by cs461x.c (ALSA driver) */ 1180 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1181 #endif 1182 BA1WRITE4(sc, CS4280_PPI, ppi); 1183 } 1184 1185 /* Download Processor Code and Data image */ 1186 static int 1187 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1188 uint32_t offset, uint32_t len) 1189 { 1190 uint32_t ctr; 1191 #if CS4280_DEBUG > 10 1192 uint32_t con, data; 1193 uint8_t c0, c1, c2, c3; 1194 #endif 1195 if ((offset & 3) || (len & 3)) 1196 return -1; 1197 1198 len /= sizeof(uint32_t); 1199 for (ctr = 0; ctr < len; ctr++) { 1200 /* XXX: 1201 * I cannot confirm this is the right thing or not 1202 * on BIG-ENDIAN machines. 1203 */ 1204 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1205 #if CS4280_DEBUG > 10 1206 data = htole32(*(src+ctr)); 1207 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1208 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1209 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1210 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1211 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1212 if (data != con ) { 1213 printf("0x%06x: write=0x%08x read=0x%08x\n", 1214 offset+ctr*4, data, con); 1215 return -1; 1216 } 1217 #endif 1218 } 1219 return 0; 1220 } 1221 1222 static int 1223 cs4280_download_image(struct cs428x_softc *sc) 1224 { 1225 int idx, err; 1226 uint32_t offset = 0; 1227 1228 err = 0; 1229 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1230 err = cs4280_download(sc, &BA1Struct.map[offset], 1231 BA1Struct.memory[idx].offset, 1232 BA1Struct.memory[idx].size); 1233 if (err != 0) { 1234 aprint_error_dev(sc->sc_dev, 1235 "load_image failed at %d\n", idx); 1236 return -1; 1237 } 1238 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1239 } 1240 return err; 1241 } 1242 1243 /* Processor Soft Reset */ 1244 static void 1245 cs4280_reset(void *sc_) 1246 { 1247 struct cs428x_softc *sc; 1248 1249 sc = sc_; 1250 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1251 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1252 delay(100); 1253 /* Clear RSTSP bit in SPCR */ 1254 BA1WRITE4(sc, CS4280_SPCR, 0); 1255 /* enable DMA reqest */ 1256 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1257 } 1258 1259 static int 1260 cs4280_init(struct cs428x_softc *sc, int init) 1261 { 1262 int n; 1263 uint32_t mem; 1264 int rv; 1265 1266 rv = 1; 1267 cs4280_clkrun_hack(sc, 1); 1268 1269 /* Start PLL out in known state */ 1270 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1271 /* Start serial ports out in known state */ 1272 BA0WRITE4(sc, CS4280_SERMC1, 0); 1273 1274 /* Specify type of CODEC */ 1275 /* XXX should not be here */ 1276 #define SERACC_CODEC_TYPE_1_03 1277 #ifdef SERACC_CODEC_TYPE_1_03 1278 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1279 #else 1280 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1281 #endif 1282 1283 /* Reset codec */ 1284 BA0WRITE4(sc, CS428X_ACCTL, 0); 1285 delay(100); /* delay 100us */ 1286 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1287 1288 /* Enable AC-link sync generation */ 1289 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1290 delay(50*1000); /* delay 50ms */ 1291 1292 /* Set the serial port timing configuration */ 1293 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1294 1295 /* Setup clock control */ 1296 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1297 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1298 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1299 1300 /* Power up the PLL */ 1301 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1302 delay(50*1000); /* delay 50ms */ 1303 1304 /* Turn on clock */ 1305 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1306 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1307 1308 /* Set the serial port FIFO pointer to the 1309 * first sample in FIFO. (not documented) */ 1310 cs4280_clear_fifos(sc); 1311 1312 #if 0 1313 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1314 BA0WRITE4(sc, CS4280_SERBSP, 0); 1315 #endif 1316 1317 /* Configure the serial port */ 1318 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1319 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1320 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1321 1322 /* Wait for CODEC ready */ 1323 n = 0; 1324 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1325 delay(125); 1326 if (++n > 1000) { 1327 aprint_error_dev(sc->sc_dev, "codec ready timeout\n"); 1328 goto exit; 1329 } 1330 } 1331 1332 /* Assert valid frame signal */ 1333 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1334 1335 /* Wait for valid AC97 input slot */ 1336 n = 0; 1337 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1338 (ACISV_ISV3 | ACISV_ISV4)) { 1339 delay(1000); 1340 if (++n > 1000) { 1341 printf("AC97 inputs slot ready timeout\n"); 1342 goto exit; 1343 } 1344 } 1345 1346 /* Set AC97 output slot valid signals */ 1347 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1348 1349 /* reset the processor */ 1350 cs4280_reset(sc); 1351 1352 /* Download the image to the processor */ 1353 if (cs4280_download_image(sc) != 0) { 1354 aprint_error_dev(sc->sc_dev, "image download error\n"); 1355 goto exit; 1356 } 1357 1358 /* Save playback parameter and then write zero. 1359 * this ensures that DMA doesn't immediately occur upon 1360 * starting the processor core 1361 */ 1362 mem = BA1READ4(sc, CS4280_PCTL); 1363 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1364 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1365 if (init != 0) 1366 sc->sc_prun = 0; 1367 1368 /* Save capture parameter and then write zero. 1369 * this ensures that DMA doesn't immediately occur upon 1370 * starting the processor core 1371 */ 1372 mem = BA1READ4(sc, CS4280_CCTL); 1373 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1374 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1375 if (init != 0) 1376 sc->sc_rrun = 0; 1377 1378 /* Processor Startup Procedure */ 1379 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1380 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1381 1382 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1383 n = 0; 1384 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1385 delay(10); 1386 if (++n > 1000) { 1387 printf("SPCR 1->0 transition timeout\n"); 1388 goto exit; 1389 } 1390 } 1391 1392 n = 0; 1393 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1394 delay(10); 1395 if (++n > 1000) { 1396 printf("SPCS 0->1 transition timeout\n"); 1397 goto exit; 1398 } 1399 } 1400 /* Processor is now running !!! */ 1401 1402 /* Setup volume */ 1403 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1404 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1405 1406 /* Interrupt enable */ 1407 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1408 1409 /* playback interrupt enable */ 1410 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1411 mem |= PFIE_PI_ENABLE; 1412 BA1WRITE4(sc, CS4280_PFIE, mem); 1413 /* capture interrupt enable */ 1414 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1415 mem |= CIE_CI_ENABLE; 1416 BA1WRITE4(sc, CS4280_CIE, mem); 1417 1418 #if NMIDI > 0 1419 /* Reset midi port */ 1420 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1421 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1422 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1423 /* midi interrupt enable */ 1424 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1425 BA0WRITE4(sc, CS4280_MIDCR, mem); 1426 #endif 1427 1428 rv = 0; 1429 1430 exit: 1431 cs4280_clkrun_hack(sc, -1); 1432 return rv; 1433 } 1434 1435 static void 1436 cs4280_clear_fifos(struct cs428x_softc *sc) 1437 { 1438 int pd, cnt, n; 1439 uint32_t mem; 1440 1441 pd = 0; 1442 /* 1443 * If device power down, power up the device and keep power down 1444 * state. 1445 */ 1446 mem = BA0READ4(sc, CS4280_CLKCR1); 1447 if (!(mem & CLKCR1_SWCE)) { 1448 printf("cs4280_clear_fifo: power down found.\n"); 1449 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1450 pd = 1; 1451 } 1452 BA0WRITE4(sc, CS4280_SERBWP, 0); 1453 for (cnt = 0; cnt < 256; cnt++) { 1454 n = 0; 1455 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1456 delay(1000); 1457 if (++n > 1000) { 1458 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1459 break; 1460 } 1461 } 1462 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1463 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1464 } 1465 if (pd) 1466 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1467 } 1468 1469 #if NMIDI > 0 1470 static int 1471 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1472 void (*ointr)(void *), void *arg) 1473 { 1474 struct cs428x_softc *sc; 1475 uint32_t mem; 1476 1477 DPRINTF(("midi_open\n")); 1478 sc = addr; 1479 sc->sc_iintr = iintr; 1480 sc->sc_ointr = ointr; 1481 sc->sc_arg = arg; 1482 1483 /* midi interrupt enable */ 1484 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1485 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1486 BA0WRITE4(sc, CS4280_MIDCR, mem); 1487 #ifdef CS4280_DEBUG 1488 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1489 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1490 return(EINVAL); 1491 } 1492 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1493 #endif 1494 return 0; 1495 } 1496 1497 static void 1498 cs4280_midi_close(void *addr) 1499 { 1500 struct cs428x_softc *sc; 1501 uint32_t mem; 1502 1503 DPRINTF(("midi_close\n")); 1504 sc = addr; 1505 /* give uart a chance to drain */ 1506 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1507 mem = BA0READ4(sc, CS4280_MIDCR); 1508 mem &= ~MIDCR_MASK; 1509 BA0WRITE4(sc, CS4280_MIDCR, mem); 1510 1511 sc->sc_iintr = 0; 1512 sc->sc_ointr = 0; 1513 } 1514 1515 static int 1516 cs4280_midi_output(void *addr, int d) 1517 { 1518 struct cs428x_softc *sc; 1519 uint32_t mem; 1520 int x; 1521 1522 sc = addr; 1523 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1524 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1525 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1526 mem |= d & MIDWP_MASK; 1527 DPRINTFN(5,("midi_output d=0x%08x",d)); 1528 BA0WRITE4(sc, CS4280_MIDWP, mem); 1529 #ifdef DIAGNOSTIC 1530 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1531 DPRINTF(("Bad write data: %d %d", 1532 mem, BA0READ4(sc, CS4280_MIDWP))); 1533 return EIO; 1534 } 1535 #endif 1536 return 0; 1537 } 1538 delay(MIDI_BUSY_DELAY); 1539 } 1540 return EIO; 1541 } 1542 1543 static void 1544 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1545 { 1546 1547 mi->name = "CS4280 MIDI UART"; 1548 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1549 } 1550 1551 #endif /* NMIDI */ 1552 1553 /* DEBUG functions */ 1554 #if CS4280_DEBUG > 10 1555 static int 1556 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1557 uint32_t offset, uint32_t len) 1558 { 1559 uint32_t ctr, data; 1560 int err; 1561 1562 if ((offset & 3) || (len & 3)) 1563 return -1; 1564 1565 err = 0; 1566 len /= sizeof(uint32_t); 1567 for (ctr = 0; ctr < len; ctr++) { 1568 /* I cannot confirm this is the right thing 1569 * on BIG-ENDIAN machines 1570 */ 1571 data = BA1READ4(sc, offset+ctr*4); 1572 if (data != htole32(*(src+ctr))) { 1573 printf("0x%06x: 0x%08x(0x%08x)\n", 1574 offset+ctr*4, data, *(src+ctr)); 1575 *(src+ctr) = data; 1576 ++err; 1577 } 1578 } 1579 return err; 1580 } 1581 1582 static int 1583 cs4280_check_images(struct cs428x_softc *sc) 1584 { 1585 int idx, err; 1586 uint32_t offset; 1587 1588 offset = 0; 1589 err = 0; 1590 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1591 for (idx = 0; idx < 1; ++idx) { 1592 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1593 BA1Struct.memory[idx].offset, 1594 BA1Struct.memory[idx].size); 1595 if (err != 0) { 1596 aprint_error_dev(sc->sc_dev, 1597 "check_image failed at %d\n", idx); 1598 } 1599 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1600 } 1601 return err; 1602 } 1603 1604 #endif /* CS4280_DEBUG */ 1605
Indexes created Thu Oct 02 14:10:14 GMT 2025