cs4280.c revision 1.72
1 /* $NetBSD: cs4280.c,v 1.72 2019/05/08 13:40:18 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.72 2019/05/08 13:40:18 isaki Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/audioio.h> 68 #include <sys/bus.h> 69 #include <sys/bswap.h> 70 71 #include <dev/audio/audio_if.h> 72 #include <dev/midi_if.h> 73 74 #include <dev/ic/ac97reg.h> 75 #include <dev/ic/ac97var.h> 76 77 #include <dev/pci/pcidevs.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/cs4280reg.h> 80 #include <dev/pci/cs4280_image.h> 81 #include <dev/pci/cs428xreg.h> 82 #include <dev/pci/cs428x.h> 83 84 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 85 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 86 87 /* IF functions for audio driver */ 88 static int cs4280_match(device_t, cfdata_t, void *); 89 static void cs4280_attach(device_t, device_t, void *); 90 static int cs4280_intr(void *); 91 static int cs4280_query_format(void *, audio_format_query_t *); 92 static int cs4280_set_format(void *, int, 93 const audio_params_t *, const audio_params_t *, 94 audio_filter_reg_t *, audio_filter_reg_t *); 95 static int cs4280_halt_output(void *); 96 static int cs4280_halt_input(void *); 97 static int cs4280_getdev(void *, struct audio_device *); 98 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 99 void *, const audio_params_t *); 100 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 101 void *, const audio_params_t *); 102 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 103 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 104 #if 0 105 static int cs4280_reset_codec(void *); 106 #endif 107 static enum ac97_host_flags cs4280_flags_codec(void *); 108 109 static bool cs4280_resume(device_t, const pmf_qual_t *); 110 static bool cs4280_suspend(device_t, const pmf_qual_t *); 111 112 /* Internal functions */ 113 static const struct cs4280_card_t * cs4280_identify_card( 114 const struct pci_attach_args *); 115 static int cs4280_piix4_match(const struct pci_attach_args *); 116 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 117 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 118 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 119 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 120 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 121 uint32_t); 122 static int cs4280_download_image(struct cs428x_softc *); 123 static void cs4280_reset(void *); 124 static int cs4280_init(struct cs428x_softc *, int); 125 static void cs4280_clear_fifos(struct cs428x_softc *); 126 127 #if CS4280_DEBUG > 10 128 /* Thease two function is only for checking image loading is succeeded or not. */ 129 static int cs4280_check_images(struct cs428x_softc *); 130 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 131 uint32_t); 132 #endif 133 134 /* Special cards */ 135 struct cs4280_card_t 136 { 137 pcireg_t id; 138 enum cs428x_flags flags; 139 }; 140 141 #define _card(vend, prod, flags) \ 142 {PCI_ID_CODE(vend, prod), flags} 143 144 static const struct cs4280_card_t cs4280_cards[] = { 145 #if 0 /* untested, from ALSA driver */ 146 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 147 CS428X_FLAG_INVAC97EAMP), 148 #endif 149 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 150 CS428X_FLAG_INVAC97EAMP), 151 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 152 CS428X_FLAG_CLKRUNHACK) 153 }; 154 155 #undef _card 156 157 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 158 159 static const struct audio_hw_if cs4280_hw_if = { 160 .query_format = cs4280_query_format, 161 .set_format = cs4280_set_format, 162 .round_blocksize = cs428x_round_blocksize, 163 .halt_output = cs4280_halt_output, 164 .halt_input = cs4280_halt_input, 165 .getdev = cs4280_getdev, 166 .set_port = cs428x_mixer_set_port, 167 .get_port = cs428x_mixer_get_port, 168 .query_devinfo = cs428x_query_devinfo, 169 .allocm = cs428x_malloc, 170 .freem = cs428x_free, 171 .round_buffersize = cs428x_round_buffersize, 172 .get_props = cs428x_get_props, 173 .trigger_output = cs4280_trigger_output, 174 .trigger_input = cs4280_trigger_input, 175 .get_locks = cs428x_get_locks, 176 }; 177 178 #if NMIDI > 0 179 /* Midi Interface */ 180 static int cs4280_midi_open(void *, int, void (*)(void *, int), 181 void (*)(void *), void *); 182 static void cs4280_midi_close(void*); 183 static int cs4280_midi_output(void *, int); 184 static void cs4280_midi_getinfo(void *, struct midi_info *); 185 186 static const struct midi_hw_if cs4280_midi_hw_if = { 187 cs4280_midi_open, 188 cs4280_midi_close, 189 cs4280_midi_output, 190 cs4280_midi_getinfo, 191 0, 192 cs428x_get_locks, 193 }; 194 #endif 195 196 CFATTACH_DECL_NEW(clcs, sizeof(struct cs428x_softc), 197 cs4280_match, cs4280_attach, NULL, NULL); 198 199 static struct audio_device cs4280_device = { 200 "CS4280", 201 "", 202 "cs4280" 203 }; 204 205 /* 206 * XXX recording must be 16bit stereo and sample rate range from 207 * 11025Hz to 48000Hz. However, it looks like to work with 8000Hz, 208 * although data sheets say lower limit is 11025Hz. 209 * XXX The combination of available formats is complicated, so I use 210 * a common format only. Please fix it if not suitable. 211 */ 212 static const struct audio_format cs4280_formats[] = { 213 { 214 .mode = AUMODE_PLAY | AUMODE_RECORD, 215 .encoding = AUDIO_ENCODING_SLINEAR_LE, 216 .validbits = 16, 217 .precision = 16, 218 .channels = 2, 219 .channel_mask = AUFMT_STEREO, 220 .frequency_type = 0, 221 .frequency = { 8000, 48000 }, 222 } 223 }; 224 #define CS4280_NFORMATS __arraycount(cs4280_formats) 225 226 static int 227 cs4280_match(device_t parent, cfdata_t match, void *aux) 228 { 229 struct pci_attach_args *pa; 230 231 pa = (struct pci_attach_args *)aux; 232 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 233 return 0; 234 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 235 #if 0 /* I can't confirm */ 236 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 237 #endif 238 ) 239 return 1; 240 return 0; 241 } 242 243 static void 244 cs4280_attach(device_t parent, device_t self, void *aux) 245 { 246 struct cs428x_softc *sc; 247 struct pci_attach_args *pa; 248 pci_chipset_tag_t pc; 249 const struct cs4280_card_t *cs_card; 250 char const *intrstr; 251 pcireg_t reg; 252 uint32_t mem; 253 int error; 254 char vendor[PCI_VENDORSTR_LEN]; 255 char product[PCI_PRODUCTSTR_LEN]; 256 char intrbuf[PCI_INTRSTR_LEN]; 257 258 sc = device_private(self); 259 sc->sc_dev = self; 260 pa = (struct pci_attach_args *)aux; 261 pc = pa->pa_pc; 262 263 pci_aprint_devinfo(pa, "Audio controller"); 264 265 cs_card = cs4280_identify_card(pa); 266 if (cs_card != NULL) { 267 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(cs_card->id)); 268 pci_findproduct(product, sizeof(product), 269 PCI_VENDOR(cs_card->id), PCI_PRODUCT(cs_card->id)); 270 aprint_normal_dev(sc->sc_dev, "%s %s\n", vendor, product); 271 sc->sc_flags = cs_card->flags; 272 } else { 273 sc->sc_flags = CS428X_FLAG_NONE; 274 } 275 276 sc->sc_pc = pa->pa_pc; 277 sc->sc_pt = pa->pa_tag; 278 279 /* Map I/O register */ 280 if (pci_mapreg_map(pa, PCI_BA0, 281 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 282 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 283 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 284 return; 285 } 286 if (pci_mapreg_map(pa, PCI_BA1, 287 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 288 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 289 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 290 return; 291 } 292 293 sc->sc_dmatag = pa->pa_dmat; 294 295 /* power up chip */ 296 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 297 pci_activate_null)) && error != EOPNOTSUPP) { 298 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 299 return; 300 } 301 302 /* Enable the device (set bus master flag) */ 303 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 304 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 305 reg | PCI_COMMAND_MASTER_ENABLE); 306 307 /* LATENCY_TIMER setting */ 308 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 309 if ( PCI_LATTIMER(mem) < 32 ) { 310 mem &= 0xffff00ff; 311 mem |= 0x00002000; 312 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 313 } 314 315 /* CLKRUN hack initialization */ 316 cs4280_clkrun_hack_init(sc); 317 318 /* Map and establish the interrupt. */ 319 if (pci_intr_map(pa, &sc->intrh)) { 320 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 321 return; 322 } 323 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 324 325 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 326 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 327 328 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->intrh, IPL_AUDIO, 329 cs4280_intr, sc, device_xname(self)); 330 if (sc->sc_ih == NULL) { 331 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 332 if (intrstr != NULL) 333 aprint_error(" at %s", intrstr); 334 aprint_error("\n"); 335 mutex_destroy(&sc->sc_lock); 336 mutex_destroy(&sc->sc_intr_lock); 337 return; 338 } 339 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 340 341 /* Initialization */ 342 if(cs4280_init(sc, 1) != 0) { 343 mutex_destroy(&sc->sc_lock); 344 mutex_destroy(&sc->sc_intr_lock); 345 return; 346 } 347 348 sc->type = TYPE_CS4280; 349 sc->halt_input = cs4280_halt_input; 350 sc->halt_output = cs4280_halt_output; 351 352 /* setup buffer related parameters */ 353 sc->dma_size = CS4280_DCHUNK; 354 sc->dma_align = CS4280_DALIGN; 355 sc->hw_blocksize = CS4280_ICHUNK; 356 357 /* AC 97 attachment */ 358 sc->host_if.arg = sc; 359 sc->host_if.attach = cs428x_attach_codec; 360 sc->host_if.read = cs4280_read_codec; 361 sc->host_if.write = cs4280_write_codec; 362 #if 0 363 sc->host_if.reset = cs4280_reset_codec; 364 #else 365 sc->host_if.reset = NULL; 366 #endif 367 sc->host_if.flags = cs4280_flags_codec; 368 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 369 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 370 return; 371 } 372 373 audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev); 374 375 #if NMIDI > 0 376 midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev); 377 #endif 378 379 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 380 aprint_error_dev(self, "couldn't establish power handler\n"); 381 } 382 383 /* Interrupt handling function */ 384 static int 385 cs4280_intr(void *p) 386 { 387 /* 388 * XXX 389 * 390 * Since CS4280 has only 4kB DMA buffer and 391 * interrupt occurs every 2kB block, I create dummy buffer 392 * which returns to audio driver and actual DMA buffer 393 * using in DMA transfer. 394 * 395 * 396 * ring buffer in audio.c is pointed by BUFADDR 397 * <------ ring buffer size == 64kB ------> 398 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 399 * |= = = =|= = = =|= = = =|= = = =|= = = =| 400 * | | | | | | <- call audio_intp every 401 * sc->sc_[pr]_count time. 402 * 403 * actual DMA buffer is pointed by KERNADDR 404 * <-> DMA buffer size = 4kB 405 * |= =| 406 * 407 * 408 */ 409 struct cs428x_softc *sc; 410 uint32_t intr, mem; 411 char * empty_dma; 412 int handled; 413 414 sc = p; 415 handled = 0; 416 417 mutex_spin_enter(&sc->sc_intr_lock); 418 419 /* grab interrupt register then clear it */ 420 intr = BA0READ4(sc, CS4280_HISR); 421 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 422 423 /* not for us ? */ 424 if ((intr & HISR_INTENA) == 0) { 425 mutex_spin_exit(&sc->sc_intr_lock); 426 return 0; 427 } 428 429 /* Playback Interrupt */ 430 if (intr & HISR_PINT) { 431 handled = 1; 432 mem = BA1READ4(sc, CS4280_PFIE); 433 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 434 if (sc->sc_prun) { 435 if ((sc->sc_pi%sc->sc_pcount) == 0) 436 sc->sc_pintr(sc->sc_parg); 437 /* copy buffer */ 438 ++sc->sc_pi; 439 empty_dma = sc->sc_pdma->addr; 440 if (sc->sc_pi&1) 441 empty_dma += sc->hw_blocksize; 442 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 443 sc->sc_pn += sc->hw_blocksize; 444 if (sc->sc_pn >= sc->sc_pe) 445 sc->sc_pn = sc->sc_ps; 446 } else { 447 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 448 } 449 BA1WRITE4(sc, CS4280_PFIE, mem); 450 } 451 /* Capture Interrupt */ 452 if (intr & HISR_CINT) { 453 handled = 1; 454 mem = BA1READ4(sc, CS4280_CIE); 455 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 456 457 if (sc->sc_rrun) { 458 ++sc->sc_ri; 459 empty_dma = sc->sc_rdma->addr; 460 if ((sc->sc_ri&1) == 0) 461 empty_dma += sc->hw_blocksize; 462 463 /* just copy it */ 464 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 465 sc->sc_rn += sc->hw_blocksize; 466 if (sc->sc_rn >= sc->sc_re) 467 sc->sc_rn = sc->sc_rs; 468 } 469 BA1WRITE4(sc, CS4280_CIE, mem); 470 471 if (sc->sc_rrun) { 472 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 473 sc->sc_rintr(sc->sc_rarg); 474 } else { 475 aprint_error_dev(sc->sc_dev, 476 "unexpected record intr\n"); 477 } 478 } 479 480 #if NMIDI > 0 481 /* Midi port Interrupt */ 482 if (intr & HISR_MIDI) { 483 int data; 484 485 handled = 1; 486 DPRINTF(("i: %d: ", 487 BA0READ4(sc, CS4280_MIDSR))); 488 /* Read the received data */ 489 while ((sc->sc_iintr != NULL) && 490 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 491 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 492 DPRINTF(("r:%x\n",data)); 493 sc->sc_iintr(sc->sc_arg, data); 494 } 495 496 /* Write the data */ 497 #if 1 498 /* XXX: 499 * It seems "Transmit Buffer Full" never activate until EOI 500 * is deliverd. Shall I throw EOI top of this routine ? 501 */ 502 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 503 DPRINTF(("w: ")); 504 if (sc->sc_ointr != NULL) 505 sc->sc_ointr(sc->sc_arg); 506 } 507 #else 508 while ((sc->sc_ointr != NULL) && 509 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 510 DPRINTF(("w: ")); 511 sc->sc_ointr(sc->sc_arg); 512 } 513 #endif 514 DPRINTF(("\n")); 515 } 516 #endif 517 518 mutex_spin_exit(&sc->sc_intr_lock); 519 return handled; 520 } 521 522 static int 523 cs4280_query_format(void *addr, audio_format_query_t *afp) 524 { 525 526 return audio_query_format(cs4280_formats, CS4280_NFORMATS, afp); 527 } 528 529 static int 530 cs4280_set_format(void *addr, int setmode, 531 const audio_params_t *play, const audio_params_t *rec, 532 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 533 { 534 struct cs428x_softc *sc; 535 536 sc = addr; 537 /* set sample rate */ 538 cs4280_set_dac_rate(sc, play->sample_rate); 539 cs4280_set_adc_rate(sc, rec->sample_rate); 540 return 0; 541 } 542 543 static int 544 cs4280_halt_output(void *addr) 545 { 546 struct cs428x_softc *sc; 547 uint32_t mem; 548 549 sc = addr; 550 mem = BA1READ4(sc, CS4280_PCTL); 551 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 552 sc->sc_prun = 0; 553 cs4280_clkrun_hack(sc, -1); 554 555 return 0; 556 } 557 558 static int 559 cs4280_halt_input(void *addr) 560 { 561 struct cs428x_softc *sc; 562 uint32_t mem; 563 564 sc = addr; 565 mem = BA1READ4(sc, CS4280_CCTL); 566 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 567 sc->sc_rrun = 0; 568 cs4280_clkrun_hack(sc, -1); 569 570 return 0; 571 } 572 573 static int 574 cs4280_getdev(void *addr, struct audio_device *retp) 575 { 576 577 *retp = cs4280_device; 578 return 0; 579 } 580 581 static int 582 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 583 void (*intr)(void *), void *arg, 584 const audio_params_t *param) 585 { 586 struct cs428x_softc *sc; 587 uint32_t pfie, pctl, pdtc; 588 struct cs428x_dma *p; 589 590 sc = addr; 591 #ifdef DIAGNOSTIC 592 if (sc->sc_prun) 593 printf("cs4280_trigger_output: already running\n"); 594 #endif 595 sc->sc_prun = 1; 596 cs4280_clkrun_hack(sc, 1); 597 598 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 599 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 600 sc->sc_pintr = intr; 601 sc->sc_parg = arg; 602 603 /* stop playback DMA */ 604 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 605 606 /* setup PDTC */ 607 pdtc = BA1READ4(sc, CS4280_PDTC); 608 pdtc &= ~PDTC_MASK; 609 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 610 BA1WRITE4(sc, CS4280_PDTC, pdtc); 611 612 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 613 param->precision, param->channels, param->encoding)); 614 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 615 continue; 616 if (p == NULL) { 617 printf("cs4280_trigger_output: bad addr %p\n", start); 618 return EINVAL; 619 } 620 if (DMAADDR(p) % sc->dma_align != 0 ) { 621 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 622 "4kB align\n", (ulong)DMAADDR(p)); 623 return EINVAL; 624 } 625 626 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 627 sc->sc_ps = (char *)start; 628 sc->sc_pe = (char *)end; 629 sc->sc_pdma = p; 630 sc->sc_pbuf = KERNADDR(p); 631 sc->sc_pi = 0; 632 sc->sc_pn = sc->sc_ps; 633 if (blksize >= sc->dma_size) { 634 sc->sc_pn = sc->sc_ps + sc->dma_size; 635 memcpy(sc->sc_pbuf, start, sc->dma_size); 636 ++sc->sc_pi; 637 } else { 638 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 639 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 640 } 641 642 /* initiate playback DMA */ 643 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 644 645 /* set PFIE */ 646 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 647 if (param->encoding == AUDIO_ENCODING_SLINEAR_BE) 648 pfie |= PFIE_SWAPPED; 649 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 650 651 sc->sc_prate = param->sample_rate; 652 cs4280_set_dac_rate(sc, param->sample_rate); 653 654 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 655 pctl |= sc->pctl; 656 BA1WRITE4(sc, CS4280_PCTL, pctl); 657 return 0; 658 } 659 660 static int 661 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 662 void (*intr)(void *), void *arg, 663 const audio_params_t *param) 664 { 665 struct cs428x_softc *sc; 666 uint32_t cctl, cie; 667 struct cs428x_dma *p; 668 669 sc = addr; 670 #ifdef DIAGNOSTIC 671 if (sc->sc_rrun) 672 printf("cs4280_trigger_input: already running\n"); 673 #endif 674 sc->sc_rrun = 1; 675 cs4280_clkrun_hack(sc, 1); 676 677 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 678 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 679 sc->sc_rintr = intr; 680 sc->sc_rarg = arg; 681 682 /* stop capture DMA */ 683 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 684 685 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 686 continue; 687 if (p == NULL) { 688 printf("cs4280_trigger_input: bad addr %p\n", start); 689 return EINVAL; 690 } 691 if (DMAADDR(p) % sc->dma_align != 0) { 692 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 693 "4kB align\n", (ulong)DMAADDR(p)); 694 return EINVAL; 695 } 696 697 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 698 sc->sc_rs = (char *)start; 699 sc->sc_re = (char *)end; 700 sc->sc_rdma = p; 701 sc->sc_rbuf = KERNADDR(p); 702 sc->sc_ri = 0; 703 sc->sc_rn = sc->sc_rs; 704 705 /* initiate capture DMA */ 706 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 707 708 /* set CIE */ 709 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 710 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 711 712 sc->sc_rrate = param->sample_rate; 713 cs4280_set_adc_rate(sc, param->sample_rate); 714 715 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 716 cctl |= sc->cctl; 717 BA1WRITE4(sc, CS4280_CCTL, cctl); 718 return 0; 719 } 720 721 static bool 722 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 723 { 724 struct cs428x_softc *sc = device_private(dv); 725 726 mutex_exit(&sc->sc_lock); 727 mutex_spin_enter(&sc->sc_intr_lock); 728 729 if (sc->sc_prun) { 730 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 731 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 732 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 733 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 734 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 735 sc->sc_suspend_state.cs4280.pctl, 736 sc->sc_suspend_state.cs4280.pfie, 737 sc->sc_suspend_state.cs4280.pba, 738 sc->sc_suspend_state.cs4280.pdtc)); 739 } 740 741 /* save current capture status */ 742 if (sc->sc_rrun) { 743 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 744 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 745 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 746 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 747 sc->sc_suspend_state.cs4280.cctl, 748 sc->sc_suspend_state.cs4280.cie, 749 sc->sc_suspend_state.cs4280.cba)); 750 } 751 752 /* Stop DMA */ 753 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 754 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 755 756 mutex_spin_exit(&sc->sc_intr_lock); 757 mutex_exit(&sc->sc_lock); 758 759 return true; 760 } 761 762 static bool 763 cs4280_resume(device_t dv, const pmf_qual_t *qual) 764 { 765 struct cs428x_softc *sc = device_private(dv); 766 767 mutex_exit(&sc->sc_lock); 768 mutex_spin_enter(&sc->sc_intr_lock); 769 cs4280_init(sc, 0); 770 #if 0 771 cs4280_reset_codec(sc); 772 #endif 773 774 /* restore DMA related status */ 775 if(sc->sc_prun) { 776 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 777 sc->sc_suspend_state.cs4280.pctl, 778 sc->sc_suspend_state.cs4280.pfie, 779 sc->sc_suspend_state.cs4280.pba, 780 sc->sc_suspend_state.cs4280.pdtc)); 781 cs4280_set_dac_rate(sc, sc->sc_prate); 782 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 783 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 784 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 785 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 786 } 787 788 if (sc->sc_rrun) { 789 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 790 sc->sc_suspend_state.cs4280.cctl, 791 sc->sc_suspend_state.cs4280.cie, 792 sc->sc_suspend_state.cs4280.cba)); 793 cs4280_set_adc_rate(sc, sc->sc_rrate); 794 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 795 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 796 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 797 } 798 799 mutex_spin_exit(&sc->sc_intr_lock); 800 801 /* restore ac97 registers */ 802 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 803 804 mutex_exit(&sc->sc_lock); 805 806 return true; 807 } 808 809 static int 810 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 811 { 812 struct cs428x_softc *sc = addr; 813 int rv; 814 815 cs4280_clkrun_hack(sc, 1); 816 rv = cs428x_read_codec(addr, reg, result); 817 cs4280_clkrun_hack(sc, -1); 818 819 return rv; 820 } 821 822 static int 823 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 824 { 825 struct cs428x_softc *sc = addr; 826 int rv; 827 828 cs4280_clkrun_hack(sc, 1); 829 rv = cs428x_write_codec(addr, reg, data); 830 cs4280_clkrun_hack(sc, -1); 831 832 return rv; 833 } 834 835 #if 0 /* XXX buggy and not required */ 836 /* control AC97 codec */ 837 static int 838 cs4280_reset_codec(void *addr) 839 { 840 struct cs428x_softc *sc; 841 int n; 842 843 sc = addr; 844 845 /* Reset codec */ 846 BA0WRITE4(sc, CS428X_ACCTL, 0); 847 delay(100); /* delay 100us */ 848 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 849 850 /* 851 * It looks like we do the following procedure, too 852 */ 853 854 /* Enable AC-link sync generation */ 855 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 856 delay(50*1000); /* XXX delay 50ms */ 857 858 /* Assert valid frame signal */ 859 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 860 861 /* Wait for valid AC97 input slot */ 862 n = 0; 863 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 864 (ACISV_ISV3 | ACISV_ISV4)) { 865 delay(1000); 866 if (++n > 1000) { 867 printf("reset_codec: AC97 inputs slot ready timeout\n"); 868 return ETIMEDOUT; 869 } 870 } 871 872 return 0; 873 } 874 #endif 875 876 static enum ac97_host_flags 877 cs4280_flags_codec(void *addr) 878 { 879 struct cs428x_softc *sc; 880 881 sc = addr; 882 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 883 return AC97_HOST_INVERTED_EAMP; 884 885 return 0; 886 } 887 888 /* Internal functions */ 889 890 static const struct cs4280_card_t * 891 cs4280_identify_card(const struct pci_attach_args *pa) 892 { 893 pcireg_t idreg; 894 u_int16_t i; 895 896 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 897 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 898 if (idreg == cs4280_cards[i].id) 899 return &cs4280_cards[i]; 900 } 901 902 return NULL; 903 } 904 905 static int 906 cs4280_piix4_match(const struct pci_attach_args *pa) 907 { 908 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 909 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 910 return 1; 911 } 912 913 return 0; 914 } 915 916 static void 917 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 918 { 919 uint16_t control, val; 920 921 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 922 return; 923 924 sc->sc_active += change; 925 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 926 if (!sc->sc_active) 927 val |= 0x2000; 928 else 929 val &= ~0x2000; 930 if (val != control) 931 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 932 } 933 934 static void 935 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 936 { 937 struct pci_attach_args smbuspa; 938 uint16_t reg; 939 pcireg_t port; 940 941 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 942 return; 943 944 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 945 sc->sc_active = 0; 946 aprint_normal_dev(sc->sc_dev, "enabling CLKRUN hack\n"); 947 948 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 949 port = reg & 0xffc0; 950 aprint_normal_dev(sc->sc_dev, "power management port 0x%x\n", 951 port); 952 953 sc->sc_pm_iot = smbuspa.pa_iot; 954 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 955 &sc->sc_pm_ioh) == 0) 956 return; 957 } 958 959 /* handle error */ 960 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 961 aprint_normal_dev(sc->sc_dev, "disabling CLKRUN hack\n"); 962 } 963 964 static void 965 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 966 { 967 /* calculate capture rate: 968 * 969 * capture_coefficient_increment = -round(rate*128*65536/48000; 970 * capture_phase_increment = floor(48000*65536*1024/rate); 971 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 972 * cy = floor(cx/200); 973 * capture_sample_rate_correction = cx - 200*cy; 974 * capture_delay = ceil(24*48000/rate); 975 * capture_num_triplets = floor(65536*rate/24000); 976 * capture_group_length = 24000/GCD(rate, 24000); 977 * where GCD means "Greatest Common Divisor". 978 * 979 * capture_coefficient_increment, capture_phase_increment and 980 * capture_num_triplets are 32-bit signed quantities. 981 * capture_sample_rate_correction and capture_group_length are 982 * 16-bit signed quantities. 983 * capture_delay is a 14-bit unsigned quantity. 984 */ 985 uint32_t cci, cpi, cnt, cx, cy, tmp1; 986 uint16_t csrc, cgl, cdlay; 987 988 /* XXX 989 * Even though, embedded_audio_spec says capture rate range 11025 to 990 * 48000, dhwiface.cpp says, 991 * 992 * "We can only decimate by up to a factor of 1/9th the hardware rate. 993 * Return an error if an attempt is made to stray outside that limit." 994 * 995 * so assume range as 48000/9 to 48000 996 */ 997 998 if (rate < 8000) 999 rate = 8000; 1000 if (rate > 48000) 1001 rate = 48000; 1002 1003 cx = rate << 16; 1004 cci = cx / 48000; 1005 cx -= cci * 48000; 1006 cx <<= 7; 1007 cci <<= 7; 1008 cci += cx / 48000; 1009 cci = - cci; 1010 1011 cx = 48000 << 16; 1012 cpi = cx / rate; 1013 cx -= cpi * rate; 1014 cx <<= 10; 1015 cpi <<= 10; 1016 cy = cx / rate; 1017 cpi += cy; 1018 cx -= cy * rate; 1019 1020 cy = cx / 200; 1021 csrc = cx - 200*cy; 1022 1023 cdlay = ((48000 * 24) + rate - 1) / rate; 1024 #if 0 1025 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1026 #endif 1027 1028 cnt = rate << 16; 1029 cnt /= 24000; 1030 1031 cgl = 1; 1032 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1033 if (((rate / tmp1) * tmp1) != rate) 1034 cgl *= 2; 1035 } 1036 if (((rate / 3) * 3) != rate) 1037 cgl *= 3; 1038 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1039 if (((rate / tmp1) * tmp1) != rate) 1040 cgl *= 5; 1041 } 1042 #if 0 1043 /* XXX what manual says */ 1044 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1045 tmp1 |= csrc<<16; 1046 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1047 #else 1048 /* suggested by cs461x.c (ALSA driver) */ 1049 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1050 #endif 1051 1052 #if 0 1053 /* I am confused. The sample rate calculation section says 1054 * cci *is* 32-bit signed quantity but in the parameter description 1055 * section, CCI only assigned 16bit. 1056 * I believe size of the variable. 1057 */ 1058 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1059 tmp1 |= cci<<16; 1060 BA1WRITE4(sc, CS4280_CCI, tmp1); 1061 #else 1062 BA1WRITE4(sc, CS4280_CCI, cci); 1063 #endif 1064 1065 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1066 tmp1 |= cdlay <<18; 1067 BA1WRITE4(sc, CS4280_CD, tmp1); 1068 1069 BA1WRITE4(sc, CS4280_CPI, cpi); 1070 1071 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1072 tmp1 |= cgl; 1073 BA1WRITE4(sc, CS4280_CGL, tmp1); 1074 1075 BA1WRITE4(sc, CS4280_CNT, cnt); 1076 1077 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1078 tmp1 |= cgl; 1079 BA1WRITE4(sc, CS4280_CGC, tmp1); 1080 } 1081 1082 static void 1083 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1084 { 1085 /* 1086 * playback rate may range from 8000Hz to 48000Hz 1087 * 1088 * play_phase_increment = floor(rate*65536*1024/48000) 1089 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1090 * py=floor(px/200) 1091 * play_sample_rate_correction = px - 200*py 1092 * 1093 * play_phase_increment is a 32bit signed quantity. 1094 * play_sample_rate_correction is a 16bit signed quantity. 1095 */ 1096 int32_t ppi; 1097 int16_t psrc; 1098 uint32_t px, py; 1099 1100 if (rate < 8000) 1101 rate = 8000; 1102 if (rate > 48000) 1103 rate = 48000; 1104 px = rate << 16; 1105 ppi = px/48000; 1106 px -= ppi*48000; 1107 ppi <<= 10; 1108 px <<= 10; 1109 py = px / 48000; 1110 ppi += py; 1111 px -= py*48000; 1112 py = px/200; 1113 px -= py*200; 1114 psrc = px; 1115 #if 0 1116 /* what manual says */ 1117 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1118 BA1WRITE4(sc, CS4280_PSRC, 1119 ( ((psrc<<16) & PSRC_MASK) | px )); 1120 #else 1121 /* suggested by cs461x.c (ALSA driver) */ 1122 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1123 #endif 1124 BA1WRITE4(sc, CS4280_PPI, ppi); 1125 } 1126 1127 /* Download Processor Code and Data image */ 1128 static int 1129 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1130 uint32_t offset, uint32_t len) 1131 { 1132 uint32_t ctr; 1133 #if CS4280_DEBUG > 10 1134 uint32_t con, data; 1135 uint8_t c0, c1, c2, c3; 1136 #endif 1137 if ((offset & 3) || (len & 3)) 1138 return -1; 1139 1140 len /= sizeof(uint32_t); 1141 for (ctr = 0; ctr < len; ctr++) { 1142 /* XXX: 1143 * I cannot confirm this is the right thing or not 1144 * on BIG-ENDIAN machines. 1145 */ 1146 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1147 #if CS4280_DEBUG > 10 1148 data = htole32(*(src+ctr)); 1149 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1150 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1151 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1152 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1153 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1154 if (data != con ) { 1155 printf("0x%06x: write=0x%08x read=0x%08x\n", 1156 offset+ctr*4, data, con); 1157 return -1; 1158 } 1159 #endif 1160 } 1161 return 0; 1162 } 1163 1164 static int 1165 cs4280_download_image(struct cs428x_softc *sc) 1166 { 1167 int idx, err; 1168 uint32_t offset = 0; 1169 1170 err = 0; 1171 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1172 err = cs4280_download(sc, &BA1Struct.map[offset], 1173 BA1Struct.memory[idx].offset, 1174 BA1Struct.memory[idx].size); 1175 if (err != 0) { 1176 aprint_error_dev(sc->sc_dev, 1177 "load_image failed at %d\n", idx); 1178 return -1; 1179 } 1180 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1181 } 1182 return err; 1183 } 1184 1185 /* Processor Soft Reset */ 1186 static void 1187 cs4280_reset(void *sc_) 1188 { 1189 struct cs428x_softc *sc; 1190 1191 sc = sc_; 1192 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1193 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1194 delay(100); 1195 /* Clear RSTSP bit in SPCR */ 1196 BA1WRITE4(sc, CS4280_SPCR, 0); 1197 /* enable DMA reqest */ 1198 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1199 } 1200 1201 static int 1202 cs4280_init(struct cs428x_softc *sc, int init) 1203 { 1204 int n; 1205 uint32_t mem; 1206 int rv; 1207 1208 rv = 1; 1209 cs4280_clkrun_hack(sc, 1); 1210 1211 /* Start PLL out in known state */ 1212 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1213 /* Start serial ports out in known state */ 1214 BA0WRITE4(sc, CS4280_SERMC1, 0); 1215 1216 /* Specify type of CODEC */ 1217 /* XXX should not be here */ 1218 #define SERACC_CODEC_TYPE_1_03 1219 #ifdef SERACC_CODEC_TYPE_1_03 1220 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1221 #else 1222 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1223 #endif 1224 1225 /* Reset codec */ 1226 BA0WRITE4(sc, CS428X_ACCTL, 0); 1227 delay(100); /* delay 100us */ 1228 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1229 1230 /* Enable AC-link sync generation */ 1231 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1232 delay(50*1000); /* delay 50ms */ 1233 1234 /* Set the serial port timing configuration */ 1235 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1236 1237 /* Setup clock control */ 1238 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1239 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1240 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1241 1242 /* Power up the PLL */ 1243 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1244 delay(50*1000); /* delay 50ms */ 1245 1246 /* Turn on clock */ 1247 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1248 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1249 1250 /* Set the serial port FIFO pointer to the 1251 * first sample in FIFO. (not documented) */ 1252 cs4280_clear_fifos(sc); 1253 1254 #if 0 1255 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1256 BA0WRITE4(sc, CS4280_SERBSP, 0); 1257 #endif 1258 1259 /* Configure the serial port */ 1260 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1261 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1262 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1263 1264 /* Wait for CODEC ready */ 1265 n = 0; 1266 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1267 delay(125); 1268 if (++n > 1000) { 1269 aprint_error_dev(sc->sc_dev, "codec ready timeout\n"); 1270 goto exit; 1271 } 1272 } 1273 1274 /* Assert valid frame signal */ 1275 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1276 1277 /* Wait for valid AC97 input slot */ 1278 n = 0; 1279 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1280 (ACISV_ISV3 | ACISV_ISV4)) { 1281 delay(1000); 1282 if (++n > 1000) { 1283 printf("AC97 inputs slot ready timeout\n"); 1284 goto exit; 1285 } 1286 } 1287 1288 /* Set AC97 output slot valid signals */ 1289 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1290 1291 /* reset the processor */ 1292 cs4280_reset(sc); 1293 1294 /* Download the image to the processor */ 1295 if (cs4280_download_image(sc) != 0) { 1296 aprint_error_dev(sc->sc_dev, "image download error\n"); 1297 goto exit; 1298 } 1299 1300 /* Save playback parameter and then write zero. 1301 * this ensures that DMA doesn't immediately occur upon 1302 * starting the processor core 1303 */ 1304 mem = BA1READ4(sc, CS4280_PCTL); 1305 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1306 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1307 if (init != 0) 1308 sc->sc_prun = 0; 1309 1310 /* Save capture parameter and then write zero. 1311 * this ensures that DMA doesn't immediately occur upon 1312 * starting the processor core 1313 */ 1314 mem = BA1READ4(sc, CS4280_CCTL); 1315 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1316 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1317 if (init != 0) 1318 sc->sc_rrun = 0; 1319 1320 /* Processor Startup Procedure */ 1321 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1322 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1323 1324 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1325 n = 0; 1326 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1327 delay(10); 1328 if (++n > 1000) { 1329 printf("SPCR 1->0 transition timeout\n"); 1330 goto exit; 1331 } 1332 } 1333 1334 n = 0; 1335 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1336 delay(10); 1337 if (++n > 1000) { 1338 printf("SPCS 0->1 transition timeout\n"); 1339 goto exit; 1340 } 1341 } 1342 /* Processor is now running !!! */ 1343 1344 /* Setup volume */ 1345 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1346 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1347 1348 /* Interrupt enable */ 1349 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1350 1351 /* playback interrupt enable */ 1352 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1353 mem |= PFIE_PI_ENABLE; 1354 BA1WRITE4(sc, CS4280_PFIE, mem); 1355 /* capture interrupt enable */ 1356 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1357 mem |= CIE_CI_ENABLE; 1358 BA1WRITE4(sc, CS4280_CIE, mem); 1359 1360 #if NMIDI > 0 1361 /* Reset midi port */ 1362 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1363 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1364 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1365 /* midi interrupt enable */ 1366 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1367 BA0WRITE4(sc, CS4280_MIDCR, mem); 1368 #endif 1369 1370 rv = 0; 1371 1372 exit: 1373 cs4280_clkrun_hack(sc, -1); 1374 return rv; 1375 } 1376 1377 static void 1378 cs4280_clear_fifos(struct cs428x_softc *sc) 1379 { 1380 int pd, cnt, n; 1381 uint32_t mem; 1382 1383 pd = 0; 1384 /* 1385 * If device power down, power up the device and keep power down 1386 * state. 1387 */ 1388 mem = BA0READ4(sc, CS4280_CLKCR1); 1389 if (!(mem & CLKCR1_SWCE)) { 1390 printf("cs4280_clear_fifo: power down found.\n"); 1391 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1392 pd = 1; 1393 } 1394 BA0WRITE4(sc, CS4280_SERBWP, 0); 1395 for (cnt = 0; cnt < 256; cnt++) { 1396 n = 0; 1397 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1398 delay(1000); 1399 if (++n > 1000) { 1400 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1401 break; 1402 } 1403 } 1404 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1405 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1406 } 1407 if (pd) 1408 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1409 } 1410 1411 #if NMIDI > 0 1412 static int 1413 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1414 void (*ointr)(void *), void *arg) 1415 { 1416 struct cs428x_softc *sc; 1417 uint32_t mem; 1418 1419 DPRINTF(("midi_open\n")); 1420 sc = addr; 1421 sc->sc_iintr = iintr; 1422 sc->sc_ointr = ointr; 1423 sc->sc_arg = arg; 1424 1425 /* midi interrupt enable */ 1426 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1427 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1428 BA0WRITE4(sc, CS4280_MIDCR, mem); 1429 #ifdef CS4280_DEBUG 1430 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1431 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1432 return(EINVAL); 1433 } 1434 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1435 #endif 1436 return 0; 1437 } 1438 1439 static void 1440 cs4280_midi_close(void *addr) 1441 { 1442 struct cs428x_softc *sc; 1443 uint32_t mem; 1444 1445 DPRINTF(("midi_close\n")); 1446 sc = addr; 1447 /* give uart a chance to drain */ 1448 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1449 mem = BA0READ4(sc, CS4280_MIDCR); 1450 mem &= ~MIDCR_MASK; 1451 BA0WRITE4(sc, CS4280_MIDCR, mem); 1452 1453 sc->sc_iintr = 0; 1454 sc->sc_ointr = 0; 1455 } 1456 1457 static int 1458 cs4280_midi_output(void *addr, int d) 1459 { 1460 struct cs428x_softc *sc; 1461 uint32_t mem; 1462 int x; 1463 1464 sc = addr; 1465 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1466 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1467 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1468 mem |= d & MIDWP_MASK; 1469 DPRINTFN(5,("midi_output d=0x%08x",d)); 1470 BA0WRITE4(sc, CS4280_MIDWP, mem); 1471 #ifdef DIAGNOSTIC 1472 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1473 DPRINTF(("Bad write data: %d %d", 1474 mem, BA0READ4(sc, CS4280_MIDWP))); 1475 return EIO; 1476 } 1477 #endif 1478 return 0; 1479 } 1480 delay(MIDI_BUSY_DELAY); 1481 } 1482 return EIO; 1483 } 1484 1485 static void 1486 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1487 { 1488 1489 mi->name = "CS4280 MIDI UART"; 1490 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1491 } 1492 1493 #endif /* NMIDI */ 1494 1495 /* DEBUG functions */ 1496 #if CS4280_DEBUG > 10 1497 static int 1498 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1499 uint32_t offset, uint32_t len) 1500 { 1501 uint32_t ctr, data; 1502 int err; 1503 1504 if ((offset & 3) || (len & 3)) 1505 return -1; 1506 1507 err = 0; 1508 len /= sizeof(uint32_t); 1509 for (ctr = 0; ctr < len; ctr++) { 1510 /* I cannot confirm this is the right thing 1511 * on BIG-ENDIAN machines 1512 */ 1513 data = BA1READ4(sc, offset+ctr*4); 1514 if (data != htole32(*(src+ctr))) { 1515 printf("0x%06x: 0x%08x(0x%08x)\n", 1516 offset+ctr*4, data, *(src+ctr)); 1517 *(src+ctr) = data; 1518 ++err; 1519 } 1520 } 1521 return err; 1522 } 1523 1524 static int 1525 cs4280_check_images(struct cs428x_softc *sc) 1526 { 1527 int idx, err; 1528 uint32_t offset; 1529 1530 offset = 0; 1531 err = 0; 1532 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1533 for (idx = 0; idx < 1; ++idx) { 1534 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1535 BA1Struct.memory[idx].offset, 1536 BA1Struct.memory[idx].size); 1537 if (err != 0) { 1538 aprint_error_dev(sc->sc_dev, 1539 "check_image failed at %d\n", idx); 1540 } 1541 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1542 } 1543 return err; 1544 } 1545 1546 #endif /* CS4280_DEBUG */ 1547
Indexes created Thu Oct 02 14:10:14 GMT 2025