cs4280.c revision 1.72.10.1
1 /* $NetBSD: cs4280.c,v 1.72.10.1 2021/04/03 22:28:46 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.72.10.1 2021/04/03 22:28:46 thorpej Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/audioio.h> 68 #include <sys/bus.h> 69 #include <sys/bswap.h> 70 71 #include <dev/audio/audio_if.h> 72 #include <dev/midi_if.h> 73 74 #include <dev/ic/ac97reg.h> 75 #include <dev/ic/ac97var.h> 76 77 #include <dev/pci/pcidevs.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/cs4280reg.h> 80 #include <dev/pci/cs4280_image.h> 81 #include <dev/pci/cs428xreg.h> 82 #include <dev/pci/cs428x.h> 83 84 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 85 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 86 87 /* IF functions for audio driver */ 88 static int cs4280_match(device_t, cfdata_t, void *); 89 static void cs4280_attach(device_t, device_t, void *); 90 static int cs4280_intr(void *); 91 static int cs4280_query_format(void *, audio_format_query_t *); 92 static int cs4280_set_format(void *, int, 93 const audio_params_t *, const audio_params_t *, 94 audio_filter_reg_t *, audio_filter_reg_t *); 95 static int cs4280_halt_output(void *); 96 static int cs4280_halt_input(void *); 97 static int cs4280_getdev(void *, struct audio_device *); 98 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 99 void *, const audio_params_t *); 100 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 101 void *, const audio_params_t *); 102 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 103 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 104 #if 0 105 static int cs4280_reset_codec(void *); 106 #endif 107 static enum ac97_host_flags cs4280_flags_codec(void *); 108 109 static bool cs4280_resume(device_t, const pmf_qual_t *); 110 static bool cs4280_suspend(device_t, const pmf_qual_t *); 111 112 /* Internal functions */ 113 static const struct cs4280_card_t * cs4280_identify_card( 114 const struct pci_attach_args *); 115 static int cs4280_piix4_match(const struct pci_attach_args *); 116 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 117 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 118 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 119 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 120 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 121 uint32_t); 122 static int cs4280_download_image(struct cs428x_softc *); 123 static void cs4280_reset(void *); 124 static int cs4280_init(struct cs428x_softc *, int); 125 static void cs4280_clear_fifos(struct cs428x_softc *); 126 127 #if CS4280_DEBUG > 10 128 /* Thease two function is only for checking image loading is succeeded or not. */ 129 static int cs4280_check_images(struct cs428x_softc *); 130 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 131 uint32_t); 132 #endif 133 134 /* Special cards */ 135 struct cs4280_card_t 136 { 137 pcireg_t id; 138 enum cs428x_flags flags; 139 }; 140 141 #define _card(vend, prod, flags) \ 142 {PCI_ID_CODE(vend, prod), flags} 143 144 static const struct cs4280_card_t cs4280_cards[] = { 145 #if 0 /* untested, from ALSA driver */ 146 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 147 CS428X_FLAG_INVAC97EAMP), 148 #endif 149 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 150 CS428X_FLAG_INVAC97EAMP), 151 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 152 CS428X_FLAG_CLKRUNHACK) 153 }; 154 155 #undef _card 156 157 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 158 159 static const struct audio_hw_if cs4280_hw_if = { 160 .query_format = cs4280_query_format, 161 .set_format = cs4280_set_format, 162 .round_blocksize = cs428x_round_blocksize, 163 .halt_output = cs4280_halt_output, 164 .halt_input = cs4280_halt_input, 165 .getdev = cs4280_getdev, 166 .set_port = cs428x_mixer_set_port, 167 .get_port = cs428x_mixer_get_port, 168 .query_devinfo = cs428x_query_devinfo, 169 .allocm = cs428x_malloc, 170 .freem = cs428x_free, 171 .round_buffersize = cs428x_round_buffersize, 172 .get_props = cs428x_get_props, 173 .trigger_output = cs4280_trigger_output, 174 .trigger_input = cs4280_trigger_input, 175 .get_locks = cs428x_get_locks, 176 }; 177 178 #if NMIDI > 0 179 /* Midi Interface */ 180 static int cs4280_midi_open(void *, int, void (*)(void *, int), 181 void (*)(void *), void *); 182 static void cs4280_midi_close(void*); 183 static int cs4280_midi_output(void *, int); 184 static void cs4280_midi_getinfo(void *, struct midi_info *); 185 186 static const struct midi_hw_if cs4280_midi_hw_if = { 187 cs4280_midi_open, 188 cs4280_midi_close, 189 cs4280_midi_output, 190 cs4280_midi_getinfo, 191 0, 192 cs428x_get_locks, 193 }; 194 #endif 195 196 CFATTACH_DECL_NEW(clcs, sizeof(struct cs428x_softc), 197 cs4280_match, cs4280_attach, NULL, NULL); 198 199 static struct audio_device cs4280_device = { 200 "CS4280", 201 "", 202 "cs4280" 203 }; 204 205 /* 206 * XXX recording must be 16bit stereo and sample rate range from 207 * 11025Hz to 48000Hz. However, it looks like to work with 8000Hz, 208 * although data sheets say lower limit is 11025Hz. 209 * XXX The combination of available formats is complicated, so I use 210 * a common format only. Please fix it if not suitable. 211 */ 212 static const struct audio_format cs4280_formats[] = { 213 { 214 .mode = AUMODE_PLAY | AUMODE_RECORD, 215 .encoding = AUDIO_ENCODING_SLINEAR_LE, 216 .validbits = 16, 217 .precision = 16, 218 .channels = 2, 219 .channel_mask = AUFMT_STEREO, 220 .frequency_type = 0, 221 .frequency = { 8000, 48000 }, 222 } 223 }; 224 #define CS4280_NFORMATS __arraycount(cs4280_formats) 225 226 static int 227 cs4280_match(device_t parent, cfdata_t match, void *aux) 228 { 229 struct pci_attach_args *pa; 230 231 pa = (struct pci_attach_args *)aux; 232 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 233 return 0; 234 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 235 #if 0 /* I can't confirm */ 236 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 237 #endif 238 ) 239 return 1; 240 return 0; 241 } 242 243 static void 244 cs4280_attach(device_t parent, device_t self, void *aux) 245 { 246 struct cs428x_softc *sc; 247 struct pci_attach_args *pa; 248 pci_chipset_tag_t pc; 249 const struct cs4280_card_t *cs_card; 250 char const *intrstr; 251 pcireg_t reg; 252 uint32_t mem; 253 int error; 254 char vendor[PCI_VENDORSTR_LEN]; 255 char product[PCI_PRODUCTSTR_LEN]; 256 char intrbuf[PCI_INTRSTR_LEN]; 257 258 sc = device_private(self); 259 sc->sc_dev = self; 260 pa = (struct pci_attach_args *)aux; 261 pc = pa->pa_pc; 262 263 pci_aprint_devinfo(pa, "Audio controller"); 264 265 cs_card = cs4280_identify_card(pa); 266 if (cs_card != NULL) { 267 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(cs_card->id)); 268 pci_findproduct(product, sizeof(product), 269 PCI_VENDOR(cs_card->id), PCI_PRODUCT(cs_card->id)); 270 aprint_normal_dev(sc->sc_dev, "%s %s\n", vendor, product); 271 sc->sc_flags = cs_card->flags; 272 } else { 273 sc->sc_flags = CS428X_FLAG_NONE; 274 } 275 276 sc->sc_pc = pa->pa_pc; 277 sc->sc_pt = pa->pa_tag; 278 279 /* Map I/O register */ 280 if (pci_mapreg_map(pa, PCI_BA0, 281 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 282 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 283 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 284 return; 285 } 286 if (pci_mapreg_map(pa, PCI_BA1, 287 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 288 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 289 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 290 return; 291 } 292 293 sc->sc_dmatag = pa->pa_dmat; 294 295 /* power up chip */ 296 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 297 pci_activate_null)) && error != EOPNOTSUPP) { 298 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 299 return; 300 } 301 302 /* Enable the device (set bus master flag) */ 303 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 304 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 305 reg | PCI_COMMAND_MASTER_ENABLE); 306 307 /* LATENCY_TIMER setting */ 308 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 309 if ( PCI_LATTIMER(mem) < 32 ) { 310 mem &= 0xffff00ff; 311 mem |= 0x00002000; 312 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 313 } 314 315 /* CLKRUN hack initialization */ 316 cs4280_clkrun_hack_init(sc); 317 318 /* Map and establish the interrupt. */ 319 if (pci_intr_map(pa, &sc->intrh)) { 320 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 321 return; 322 } 323 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 324 325 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 326 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 327 328 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->intrh, IPL_AUDIO, 329 cs4280_intr, sc, device_xname(self)); 330 if (sc->sc_ih == NULL) { 331 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 332 if (intrstr != NULL) 333 aprint_error(" at %s", intrstr); 334 aprint_error("\n"); 335 mutex_destroy(&sc->sc_lock); 336 mutex_destroy(&sc->sc_intr_lock); 337 return; 338 } 339 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 340 341 /* Initialization */ 342 if(cs4280_init(sc, 1) != 0) { 343 mutex_destroy(&sc->sc_lock); 344 mutex_destroy(&sc->sc_intr_lock); 345 return; 346 } 347 348 sc->type = TYPE_CS4280; 349 350 /* setup buffer related parameters */ 351 sc->dma_size = CS4280_DCHUNK; 352 sc->dma_align = CS4280_DALIGN; 353 sc->hw_blocksize = CS4280_ICHUNK; 354 355 /* AC 97 attachment */ 356 sc->host_if.arg = sc; 357 sc->host_if.attach = cs428x_attach_codec; 358 sc->host_if.read = cs4280_read_codec; 359 sc->host_if.write = cs4280_write_codec; 360 #if 0 361 sc->host_if.reset = cs4280_reset_codec; 362 #else 363 sc->host_if.reset = NULL; 364 #endif 365 sc->host_if.flags = cs4280_flags_codec; 366 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 367 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 368 return; 369 } 370 371 audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev); 372 373 #if NMIDI > 0 374 midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev); 375 #endif 376 377 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 378 aprint_error_dev(self, "couldn't establish power handler\n"); 379 } 380 381 /* Interrupt handling function */ 382 static int 383 cs4280_intr(void *p) 384 { 385 /* 386 * XXX 387 * 388 * Since CS4280 has only 4kB DMA buffer and 389 * interrupt occurs every 2kB block, I create dummy buffer 390 * which returns to audio driver and actual DMA buffer 391 * using in DMA transfer. 392 * 393 * 394 * ring buffer in audio.c is pointed by BUFADDR 395 * <------ ring buffer size == 64kB ------> 396 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 397 * |= = = =|= = = =|= = = =|= = = =|= = = =| 398 * | | | | | | <- call audio_intp every 399 * sc->sc_[pr]_count time. 400 * 401 * actual DMA buffer is pointed by KERNADDR 402 * <-> DMA buffer size = 4kB 403 * |= =| 404 * 405 * 406 */ 407 struct cs428x_softc *sc; 408 uint32_t intr, mem; 409 char * empty_dma; 410 int handled; 411 412 sc = p; 413 handled = 0; 414 415 mutex_spin_enter(&sc->sc_intr_lock); 416 417 /* grab interrupt register then clear it */ 418 intr = BA0READ4(sc, CS4280_HISR); 419 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 420 421 /* not for us ? */ 422 if ((intr & HISR_INTENA) == 0) { 423 mutex_spin_exit(&sc->sc_intr_lock); 424 return 0; 425 } 426 427 /* Playback Interrupt */ 428 if (intr & HISR_PINT) { 429 handled = 1; 430 mem = BA1READ4(sc, CS4280_PFIE); 431 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 432 if (sc->sc_prun) { 433 if ((sc->sc_pi%sc->sc_pcount) == 0) 434 sc->sc_pintr(sc->sc_parg); 435 /* copy buffer */ 436 ++sc->sc_pi; 437 empty_dma = sc->sc_pdma->addr; 438 if (sc->sc_pi&1) 439 empty_dma += sc->hw_blocksize; 440 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 441 sc->sc_pn += sc->hw_blocksize; 442 if (sc->sc_pn >= sc->sc_pe) 443 sc->sc_pn = sc->sc_ps; 444 } else { 445 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 446 } 447 BA1WRITE4(sc, CS4280_PFIE, mem); 448 } 449 /* Capture Interrupt */ 450 if (intr & HISR_CINT) { 451 handled = 1; 452 mem = BA1READ4(sc, CS4280_CIE); 453 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 454 455 if (sc->sc_rrun) { 456 ++sc->sc_ri; 457 empty_dma = sc->sc_rdma->addr; 458 if ((sc->sc_ri&1) == 0) 459 empty_dma += sc->hw_blocksize; 460 461 /* just copy it */ 462 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 463 sc->sc_rn += sc->hw_blocksize; 464 if (sc->sc_rn >= sc->sc_re) 465 sc->sc_rn = sc->sc_rs; 466 } 467 BA1WRITE4(sc, CS4280_CIE, mem); 468 469 if (sc->sc_rrun) { 470 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 471 sc->sc_rintr(sc->sc_rarg); 472 } else { 473 aprint_error_dev(sc->sc_dev, 474 "unexpected record intr\n"); 475 } 476 } 477 478 #if NMIDI > 0 479 /* Midi port Interrupt */ 480 if (intr & HISR_MIDI) { 481 int data; 482 483 handled = 1; 484 DPRINTF(("i: %d: ", 485 BA0READ4(sc, CS4280_MIDSR))); 486 /* Read the received data */ 487 while ((sc->sc_iintr != NULL) && 488 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 489 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 490 DPRINTF(("r:%x\n",data)); 491 sc->sc_iintr(sc->sc_arg, data); 492 } 493 494 /* Write the data */ 495 #if 1 496 /* XXX: 497 * It seems "Transmit Buffer Full" never activate until EOI 498 * is deliverd. Shall I throw EOI top of this routine ? 499 */ 500 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 501 DPRINTF(("w: ")); 502 if (sc->sc_ointr != NULL) 503 sc->sc_ointr(sc->sc_arg); 504 } 505 #else 506 while ((sc->sc_ointr != NULL) && 507 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 508 DPRINTF(("w: ")); 509 sc->sc_ointr(sc->sc_arg); 510 } 511 #endif 512 DPRINTF(("\n")); 513 } 514 #endif 515 516 mutex_spin_exit(&sc->sc_intr_lock); 517 return handled; 518 } 519 520 static int 521 cs4280_query_format(void *addr, audio_format_query_t *afp) 522 { 523 524 return audio_query_format(cs4280_formats, CS4280_NFORMATS, afp); 525 } 526 527 static int 528 cs4280_set_format(void *addr, int setmode, 529 const audio_params_t *play, const audio_params_t *rec, 530 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 531 { 532 struct cs428x_softc *sc; 533 534 sc = addr; 535 /* set sample rate */ 536 cs4280_set_dac_rate(sc, play->sample_rate); 537 cs4280_set_adc_rate(sc, rec->sample_rate); 538 return 0; 539 } 540 541 static int 542 cs4280_halt_output(void *addr) 543 { 544 struct cs428x_softc *sc; 545 uint32_t mem; 546 547 sc = addr; 548 mem = BA1READ4(sc, CS4280_PCTL); 549 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 550 sc->sc_prun = 0; 551 cs4280_clkrun_hack(sc, -1); 552 553 return 0; 554 } 555 556 static int 557 cs4280_halt_input(void *addr) 558 { 559 struct cs428x_softc *sc; 560 uint32_t mem; 561 562 sc = addr; 563 mem = BA1READ4(sc, CS4280_CCTL); 564 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 565 sc->sc_rrun = 0; 566 cs4280_clkrun_hack(sc, -1); 567 568 return 0; 569 } 570 571 static int 572 cs4280_getdev(void *addr, struct audio_device *retp) 573 { 574 575 *retp = cs4280_device; 576 return 0; 577 } 578 579 static int 580 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 581 void (*intr)(void *), void *arg, 582 const audio_params_t *param) 583 { 584 struct cs428x_softc *sc; 585 uint32_t pfie, pctl, pdtc; 586 struct cs428x_dma *p; 587 588 sc = addr; 589 #ifdef DIAGNOSTIC 590 if (sc->sc_prun) 591 printf("cs4280_trigger_output: already running\n"); 592 #endif 593 sc->sc_prun = 1; 594 cs4280_clkrun_hack(sc, 1); 595 596 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 597 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 598 sc->sc_pintr = intr; 599 sc->sc_parg = arg; 600 601 /* stop playback DMA */ 602 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 603 604 /* setup PDTC */ 605 pdtc = BA1READ4(sc, CS4280_PDTC); 606 pdtc &= ~PDTC_MASK; 607 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 608 BA1WRITE4(sc, CS4280_PDTC, pdtc); 609 610 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 611 param->precision, param->channels, param->encoding)); 612 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 613 continue; 614 if (p == NULL) { 615 printf("cs4280_trigger_output: bad addr %p\n", start); 616 return EINVAL; 617 } 618 if (DMAADDR(p) % sc->dma_align != 0 ) { 619 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 620 "4kB align\n", (ulong)DMAADDR(p)); 621 return EINVAL; 622 } 623 624 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 625 sc->sc_ps = (char *)start; 626 sc->sc_pe = (char *)end; 627 sc->sc_pdma = p; 628 sc->sc_pbuf = KERNADDR(p); 629 sc->sc_pi = 0; 630 sc->sc_pn = sc->sc_ps; 631 if (blksize >= sc->dma_size) { 632 sc->sc_pn = sc->sc_ps + sc->dma_size; 633 memcpy(sc->sc_pbuf, start, sc->dma_size); 634 ++sc->sc_pi; 635 } else { 636 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 637 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 638 } 639 640 /* initiate playback DMA */ 641 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 642 643 /* set PFIE */ 644 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 645 if (param->encoding == AUDIO_ENCODING_SLINEAR_BE) 646 pfie |= PFIE_SWAPPED; 647 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 648 649 sc->sc_prate = param->sample_rate; 650 cs4280_set_dac_rate(sc, param->sample_rate); 651 652 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 653 pctl |= sc->pctl; 654 BA1WRITE4(sc, CS4280_PCTL, pctl); 655 return 0; 656 } 657 658 static int 659 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 660 void (*intr)(void *), void *arg, 661 const audio_params_t *param) 662 { 663 struct cs428x_softc *sc; 664 uint32_t cctl, cie; 665 struct cs428x_dma *p; 666 667 sc = addr; 668 #ifdef DIAGNOSTIC 669 if (sc->sc_rrun) 670 printf("cs4280_trigger_input: already running\n"); 671 #endif 672 sc->sc_rrun = 1; 673 cs4280_clkrun_hack(sc, 1); 674 675 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 676 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 677 sc->sc_rintr = intr; 678 sc->sc_rarg = arg; 679 680 /* stop capture DMA */ 681 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 682 683 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 684 continue; 685 if (p == NULL) { 686 printf("cs4280_trigger_input: bad addr %p\n", start); 687 return EINVAL; 688 } 689 if (DMAADDR(p) % sc->dma_align != 0) { 690 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 691 "4kB align\n", (ulong)DMAADDR(p)); 692 return EINVAL; 693 } 694 695 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 696 sc->sc_rs = (char *)start; 697 sc->sc_re = (char *)end; 698 sc->sc_rdma = p; 699 sc->sc_rbuf = KERNADDR(p); 700 sc->sc_ri = 0; 701 sc->sc_rn = sc->sc_rs; 702 703 /* initiate capture DMA */ 704 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 705 706 /* set CIE */ 707 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 708 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 709 710 sc->sc_rrate = param->sample_rate; 711 cs4280_set_adc_rate(sc, param->sample_rate); 712 713 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 714 cctl |= sc->cctl; 715 BA1WRITE4(sc, CS4280_CCTL, cctl); 716 return 0; 717 } 718 719 static bool 720 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 721 { 722 struct cs428x_softc *sc = device_private(dv); 723 724 mutex_exit(&sc->sc_lock); 725 mutex_spin_enter(&sc->sc_intr_lock); 726 727 if (sc->sc_prun) { 728 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 729 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 730 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 731 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 732 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 733 sc->sc_suspend_state.cs4280.pctl, 734 sc->sc_suspend_state.cs4280.pfie, 735 sc->sc_suspend_state.cs4280.pba, 736 sc->sc_suspend_state.cs4280.pdtc)); 737 } 738 739 /* save current capture status */ 740 if (sc->sc_rrun) { 741 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 742 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 743 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 744 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 745 sc->sc_suspend_state.cs4280.cctl, 746 sc->sc_suspend_state.cs4280.cie, 747 sc->sc_suspend_state.cs4280.cba)); 748 } 749 750 /* Stop DMA */ 751 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 752 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 753 754 mutex_spin_exit(&sc->sc_intr_lock); 755 mutex_exit(&sc->sc_lock); 756 757 return true; 758 } 759 760 static bool 761 cs4280_resume(device_t dv, const pmf_qual_t *qual) 762 { 763 struct cs428x_softc *sc = device_private(dv); 764 765 mutex_exit(&sc->sc_lock); 766 mutex_spin_enter(&sc->sc_intr_lock); 767 cs4280_init(sc, 0); 768 #if 0 769 cs4280_reset_codec(sc); 770 #endif 771 772 /* restore DMA related status */ 773 if(sc->sc_prun) { 774 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 775 sc->sc_suspend_state.cs4280.pctl, 776 sc->sc_suspend_state.cs4280.pfie, 777 sc->sc_suspend_state.cs4280.pba, 778 sc->sc_suspend_state.cs4280.pdtc)); 779 cs4280_set_dac_rate(sc, sc->sc_prate); 780 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 781 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 782 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 783 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 784 } 785 786 if (sc->sc_rrun) { 787 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 788 sc->sc_suspend_state.cs4280.cctl, 789 sc->sc_suspend_state.cs4280.cie, 790 sc->sc_suspend_state.cs4280.cba)); 791 cs4280_set_adc_rate(sc, sc->sc_rrate); 792 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 793 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 794 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 795 } 796 797 mutex_spin_exit(&sc->sc_intr_lock); 798 799 /* restore ac97 registers */ 800 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 801 802 mutex_exit(&sc->sc_lock); 803 804 return true; 805 } 806 807 static int 808 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 809 { 810 struct cs428x_softc *sc = addr; 811 int rv; 812 813 cs4280_clkrun_hack(sc, 1); 814 rv = cs428x_read_codec(addr, reg, result); 815 cs4280_clkrun_hack(sc, -1); 816 817 return rv; 818 } 819 820 static int 821 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 822 { 823 struct cs428x_softc *sc = addr; 824 int rv; 825 826 cs4280_clkrun_hack(sc, 1); 827 rv = cs428x_write_codec(addr, reg, data); 828 cs4280_clkrun_hack(sc, -1); 829 830 return rv; 831 } 832 833 #if 0 /* XXX buggy and not required */ 834 /* control AC97 codec */ 835 static int 836 cs4280_reset_codec(void *addr) 837 { 838 struct cs428x_softc *sc; 839 int n; 840 841 sc = addr; 842 843 /* Reset codec */ 844 BA0WRITE4(sc, CS428X_ACCTL, 0); 845 delay(100); /* delay 100us */ 846 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 847 848 /* 849 * It looks like we do the following procedure, too 850 */ 851 852 /* Enable AC-link sync generation */ 853 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 854 delay(50*1000); /* XXX delay 50ms */ 855 856 /* Assert valid frame signal */ 857 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 858 859 /* Wait for valid AC97 input slot */ 860 n = 0; 861 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 862 (ACISV_ISV3 | ACISV_ISV4)) { 863 delay(1000); 864 if (++n > 1000) { 865 printf("reset_codec: AC97 inputs slot ready timeout\n"); 866 return ETIMEDOUT; 867 } 868 } 869 870 return 0; 871 } 872 #endif 873 874 static enum ac97_host_flags 875 cs4280_flags_codec(void *addr) 876 { 877 struct cs428x_softc *sc; 878 879 sc = addr; 880 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 881 return AC97_HOST_INVERTED_EAMP; 882 883 return 0; 884 } 885 886 /* Internal functions */ 887 888 static const struct cs4280_card_t * 889 cs4280_identify_card(const struct pci_attach_args *pa) 890 { 891 pcireg_t idreg; 892 u_int16_t i; 893 894 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 895 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 896 if (idreg == cs4280_cards[i].id) 897 return &cs4280_cards[i]; 898 } 899 900 return NULL; 901 } 902 903 static int 904 cs4280_piix4_match(const struct pci_attach_args *pa) 905 { 906 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 907 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 908 return 1; 909 } 910 911 return 0; 912 } 913 914 static void 915 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 916 { 917 uint16_t control, val; 918 919 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 920 return; 921 922 sc->sc_active += change; 923 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 924 if (!sc->sc_active) 925 val |= 0x2000; 926 else 927 val &= ~0x2000; 928 if (val != control) 929 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 930 } 931 932 static void 933 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 934 { 935 struct pci_attach_args smbuspa; 936 uint16_t reg; 937 pcireg_t port; 938 939 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 940 return; 941 942 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 943 sc->sc_active = 0; 944 aprint_normal_dev(sc->sc_dev, "enabling CLKRUN hack\n"); 945 946 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 947 port = reg & 0xffc0; 948 aprint_normal_dev(sc->sc_dev, "power management port 0x%x\n", 949 port); 950 951 sc->sc_pm_iot = smbuspa.pa_iot; 952 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 953 &sc->sc_pm_ioh) == 0) 954 return; 955 } 956 957 /* handle error */ 958 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 959 aprint_normal_dev(sc->sc_dev, "disabling CLKRUN hack\n"); 960 } 961 962 static void 963 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 964 { 965 /* calculate capture rate: 966 * 967 * capture_coefficient_increment = -round(rate*128*65536/48000; 968 * capture_phase_increment = floor(48000*65536*1024/rate); 969 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 970 * cy = floor(cx/200); 971 * capture_sample_rate_correction = cx - 200*cy; 972 * capture_delay = ceil(24*48000/rate); 973 * capture_num_triplets = floor(65536*rate/24000); 974 * capture_group_length = 24000/GCD(rate, 24000); 975 * where GCD means "Greatest Common Divisor". 976 * 977 * capture_coefficient_increment, capture_phase_increment and 978 * capture_num_triplets are 32-bit signed quantities. 979 * capture_sample_rate_correction and capture_group_length are 980 * 16-bit signed quantities. 981 * capture_delay is a 14-bit unsigned quantity. 982 */ 983 uint32_t cci, cpi, cnt, cx, cy, tmp1; 984 uint16_t csrc, cgl, cdlay; 985 986 /* XXX 987 * Even though, embedded_audio_spec says capture rate range 11025 to 988 * 48000, dhwiface.cpp says, 989 * 990 * "We can only decimate by up to a factor of 1/9th the hardware rate. 991 * Return an error if an attempt is made to stray outside that limit." 992 * 993 * so assume range as 48000/9 to 48000 994 */ 995 996 if (rate < 8000) 997 rate = 8000; 998 if (rate > 48000) 999 rate = 48000; 1000 1001 cx = rate << 16; 1002 cci = cx / 48000; 1003 cx -= cci * 48000; 1004 cx <<= 7; 1005 cci <<= 7; 1006 cci += cx / 48000; 1007 cci = - cci; 1008 1009 cx = 48000 << 16; 1010 cpi = cx / rate; 1011 cx -= cpi * rate; 1012 cx <<= 10; 1013 cpi <<= 10; 1014 cy = cx / rate; 1015 cpi += cy; 1016 cx -= cy * rate; 1017 1018 cy = cx / 200; 1019 csrc = cx - 200*cy; 1020 1021 cdlay = ((48000 * 24) + rate - 1) / rate; 1022 #if 0 1023 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1024 #endif 1025 1026 cnt = rate << 16; 1027 cnt /= 24000; 1028 1029 cgl = 1; 1030 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1031 if (((rate / tmp1) * tmp1) != rate) 1032 cgl *= 2; 1033 } 1034 if (((rate / 3) * 3) != rate) 1035 cgl *= 3; 1036 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1037 if (((rate / tmp1) * tmp1) != rate) 1038 cgl *= 5; 1039 } 1040 #if 0 1041 /* XXX what manual says */ 1042 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1043 tmp1 |= csrc<<16; 1044 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1045 #else 1046 /* suggested by cs461x.c (ALSA driver) */ 1047 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1048 #endif 1049 1050 #if 0 1051 /* I am confused. The sample rate calculation section says 1052 * cci *is* 32-bit signed quantity but in the parameter description 1053 * section, CCI only assigned 16bit. 1054 * I believe size of the variable. 1055 */ 1056 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1057 tmp1 |= cci<<16; 1058 BA1WRITE4(sc, CS4280_CCI, tmp1); 1059 #else 1060 BA1WRITE4(sc, CS4280_CCI, cci); 1061 #endif 1062 1063 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1064 tmp1 |= cdlay <<18; 1065 BA1WRITE4(sc, CS4280_CD, tmp1); 1066 1067 BA1WRITE4(sc, CS4280_CPI, cpi); 1068 1069 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1070 tmp1 |= cgl; 1071 BA1WRITE4(sc, CS4280_CGL, tmp1); 1072 1073 BA1WRITE4(sc, CS4280_CNT, cnt); 1074 1075 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1076 tmp1 |= cgl; 1077 BA1WRITE4(sc, CS4280_CGC, tmp1); 1078 } 1079 1080 static void 1081 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1082 { 1083 /* 1084 * playback rate may range from 8000Hz to 48000Hz 1085 * 1086 * play_phase_increment = floor(rate*65536*1024/48000) 1087 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1088 * py=floor(px/200) 1089 * play_sample_rate_correction = px - 200*py 1090 * 1091 * play_phase_increment is a 32bit signed quantity. 1092 * play_sample_rate_correction is a 16bit signed quantity. 1093 */ 1094 int32_t ppi; 1095 int16_t psrc; 1096 uint32_t px, py; 1097 1098 if (rate < 8000) 1099 rate = 8000; 1100 if (rate > 48000) 1101 rate = 48000; 1102 px = rate << 16; 1103 ppi = px/48000; 1104 px -= ppi*48000; 1105 ppi <<= 10; 1106 px <<= 10; 1107 py = px / 48000; 1108 ppi += py; 1109 px -= py*48000; 1110 py = px/200; 1111 px -= py*200; 1112 psrc = px; 1113 #if 0 1114 /* what manual says */ 1115 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1116 BA1WRITE4(sc, CS4280_PSRC, 1117 ( ((psrc<<16) & PSRC_MASK) | px )); 1118 #else 1119 /* suggested by cs461x.c (ALSA driver) */ 1120 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1121 #endif 1122 BA1WRITE4(sc, CS4280_PPI, ppi); 1123 } 1124 1125 /* Download Processor Code and Data image */ 1126 static int 1127 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1128 uint32_t offset, uint32_t len) 1129 { 1130 uint32_t ctr; 1131 #if CS4280_DEBUG > 10 1132 uint32_t con, data; 1133 uint8_t c0, c1, c2, c3; 1134 #endif 1135 if ((offset & 3) || (len & 3)) 1136 return -1; 1137 1138 len /= sizeof(uint32_t); 1139 for (ctr = 0; ctr < len; ctr++) { 1140 /* XXX: 1141 * I cannot confirm this is the right thing or not 1142 * on BIG-ENDIAN machines. 1143 */ 1144 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1145 #if CS4280_DEBUG > 10 1146 data = htole32(*(src+ctr)); 1147 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1148 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1149 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1150 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1151 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1152 if (data != con ) { 1153 printf("0x%06x: write=0x%08x read=0x%08x\n", 1154 offset+ctr*4, data, con); 1155 return -1; 1156 } 1157 #endif 1158 } 1159 return 0; 1160 } 1161 1162 static int 1163 cs4280_download_image(struct cs428x_softc *sc) 1164 { 1165 int idx, err; 1166 uint32_t offset = 0; 1167 1168 err = 0; 1169 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1170 err = cs4280_download(sc, &BA1Struct.map[offset], 1171 BA1Struct.memory[idx].offset, 1172 BA1Struct.memory[idx].size); 1173 if (err != 0) { 1174 aprint_error_dev(sc->sc_dev, 1175 "load_image failed at %d\n", idx); 1176 return -1; 1177 } 1178 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1179 } 1180 return err; 1181 } 1182 1183 /* Processor Soft Reset */ 1184 static void 1185 cs4280_reset(void *sc_) 1186 { 1187 struct cs428x_softc *sc; 1188 1189 sc = sc_; 1190 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1191 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1192 delay(100); 1193 /* Clear RSTSP bit in SPCR */ 1194 BA1WRITE4(sc, CS4280_SPCR, 0); 1195 /* enable DMA reqest */ 1196 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1197 } 1198 1199 static int 1200 cs4280_init(struct cs428x_softc *sc, int init) 1201 { 1202 int n; 1203 uint32_t mem; 1204 int rv; 1205 1206 rv = 1; 1207 cs4280_clkrun_hack(sc, 1); 1208 1209 /* Start PLL out in known state */ 1210 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1211 /* Start serial ports out in known state */ 1212 BA0WRITE4(sc, CS4280_SERMC1, 0); 1213 1214 /* Specify type of CODEC */ 1215 /* XXX should not be here */ 1216 #define SERACC_CODEC_TYPE_1_03 1217 #ifdef SERACC_CODEC_TYPE_1_03 1218 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1219 #else 1220 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1221 #endif 1222 1223 /* Reset codec */ 1224 BA0WRITE4(sc, CS428X_ACCTL, 0); 1225 delay(100); /* delay 100us */ 1226 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1227 1228 /* Enable AC-link sync generation */ 1229 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1230 delay(50*1000); /* delay 50ms */ 1231 1232 /* Set the serial port timing configuration */ 1233 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1234 1235 /* Setup clock control */ 1236 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1237 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1238 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1239 1240 /* Power up the PLL */ 1241 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1242 delay(50*1000); /* delay 50ms */ 1243 1244 /* Turn on clock */ 1245 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1246 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1247 1248 /* Set the serial port FIFO pointer to the 1249 * first sample in FIFO. (not documented) */ 1250 cs4280_clear_fifos(sc); 1251 1252 #if 0 1253 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1254 BA0WRITE4(sc, CS4280_SERBSP, 0); 1255 #endif 1256 1257 /* Configure the serial port */ 1258 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1259 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1260 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1261 1262 /* Wait for CODEC ready */ 1263 n = 0; 1264 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1265 delay(125); 1266 if (++n > 1000) { 1267 aprint_error_dev(sc->sc_dev, "codec ready timeout\n"); 1268 goto exit; 1269 } 1270 } 1271 1272 /* Assert valid frame signal */ 1273 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1274 1275 /* Wait for valid AC97 input slot */ 1276 n = 0; 1277 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1278 (ACISV_ISV3 | ACISV_ISV4)) { 1279 delay(1000); 1280 if (++n > 1000) { 1281 printf("AC97 inputs slot ready timeout\n"); 1282 goto exit; 1283 } 1284 } 1285 1286 /* Set AC97 output slot valid signals */ 1287 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1288 1289 /* reset the processor */ 1290 cs4280_reset(sc); 1291 1292 /* Download the image to the processor */ 1293 if (cs4280_download_image(sc) != 0) { 1294 aprint_error_dev(sc->sc_dev, "image download error\n"); 1295 goto exit; 1296 } 1297 1298 /* Save playback parameter and then write zero. 1299 * this ensures that DMA doesn't immediately occur upon 1300 * starting the processor core 1301 */ 1302 mem = BA1READ4(sc, CS4280_PCTL); 1303 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1304 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1305 if (init != 0) 1306 sc->sc_prun = 0; 1307 1308 /* Save capture parameter and then write zero. 1309 * this ensures that DMA doesn't immediately occur upon 1310 * starting the processor core 1311 */ 1312 mem = BA1READ4(sc, CS4280_CCTL); 1313 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1314 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1315 if (init != 0) 1316 sc->sc_rrun = 0; 1317 1318 /* Processor Startup Procedure */ 1319 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1320 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1321 1322 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1323 n = 0; 1324 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1325 delay(10); 1326 if (++n > 1000) { 1327 printf("SPCR 1->0 transition timeout\n"); 1328 goto exit; 1329 } 1330 } 1331 1332 n = 0; 1333 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1334 delay(10); 1335 if (++n > 1000) { 1336 printf("SPCS 0->1 transition timeout\n"); 1337 goto exit; 1338 } 1339 } 1340 /* Processor is now running !!! */ 1341 1342 /* Setup volume */ 1343 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1344 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1345 1346 /* Interrupt enable */ 1347 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1348 1349 /* playback interrupt enable */ 1350 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1351 mem |= PFIE_PI_ENABLE; 1352 BA1WRITE4(sc, CS4280_PFIE, mem); 1353 /* capture interrupt enable */ 1354 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1355 mem |= CIE_CI_ENABLE; 1356 BA1WRITE4(sc, CS4280_CIE, mem); 1357 1358 #if NMIDI > 0 1359 /* Reset midi port */ 1360 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1361 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1362 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1363 /* midi interrupt enable */ 1364 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1365 BA0WRITE4(sc, CS4280_MIDCR, mem); 1366 #endif 1367 1368 rv = 0; 1369 1370 exit: 1371 cs4280_clkrun_hack(sc, -1); 1372 return rv; 1373 } 1374 1375 static void 1376 cs4280_clear_fifos(struct cs428x_softc *sc) 1377 { 1378 int pd, cnt, n; 1379 uint32_t mem; 1380 1381 pd = 0; 1382 /* 1383 * If device power down, power up the device and keep power down 1384 * state. 1385 */ 1386 mem = BA0READ4(sc, CS4280_CLKCR1); 1387 if (!(mem & CLKCR1_SWCE)) { 1388 printf("cs4280_clear_fifo: power down found.\n"); 1389 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1390 pd = 1; 1391 } 1392 BA0WRITE4(sc, CS4280_SERBWP, 0); 1393 for (cnt = 0; cnt < 256; cnt++) { 1394 n = 0; 1395 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1396 delay(1000); 1397 if (++n > 1000) { 1398 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1399 break; 1400 } 1401 } 1402 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1403 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1404 } 1405 if (pd) 1406 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1407 } 1408 1409 #if NMIDI > 0 1410 static int 1411 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1412 void (*ointr)(void *), void *arg) 1413 { 1414 struct cs428x_softc *sc; 1415 uint32_t mem; 1416 1417 DPRINTF(("midi_open\n")); 1418 sc = addr; 1419 sc->sc_iintr = iintr; 1420 sc->sc_ointr = ointr; 1421 sc->sc_arg = arg; 1422 1423 /* midi interrupt enable */ 1424 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1425 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1426 BA0WRITE4(sc, CS4280_MIDCR, mem); 1427 #ifdef CS4280_DEBUG 1428 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1429 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1430 return(EINVAL); 1431 } 1432 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1433 #endif 1434 return 0; 1435 } 1436 1437 static void 1438 cs4280_midi_close(void *addr) 1439 { 1440 struct cs428x_softc *sc; 1441 uint32_t mem; 1442 1443 DPRINTF(("midi_close\n")); 1444 sc = addr; 1445 /* give uart a chance to drain */ 1446 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1447 mem = BA0READ4(sc, CS4280_MIDCR); 1448 mem &= ~MIDCR_MASK; 1449 BA0WRITE4(sc, CS4280_MIDCR, mem); 1450 1451 sc->sc_iintr = 0; 1452 sc->sc_ointr = 0; 1453 } 1454 1455 static int 1456 cs4280_midi_output(void *addr, int d) 1457 { 1458 struct cs428x_softc *sc; 1459 uint32_t mem; 1460 int x; 1461 1462 sc = addr; 1463 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1464 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1465 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1466 mem |= d & MIDWP_MASK; 1467 DPRINTFN(5,("midi_output d=0x%08x",d)); 1468 BA0WRITE4(sc, CS4280_MIDWP, mem); 1469 #ifdef DIAGNOSTIC 1470 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1471 DPRINTF(("Bad write data: %d %d", 1472 mem, BA0READ4(sc, CS4280_MIDWP))); 1473 return EIO; 1474 } 1475 #endif 1476 return 0; 1477 } 1478 delay(MIDI_BUSY_DELAY); 1479 } 1480 return EIO; 1481 } 1482 1483 static void 1484 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1485 { 1486 1487 mi->name = "CS4280 MIDI UART"; 1488 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1489 } 1490 1491 #endif /* NMIDI */ 1492 1493 /* DEBUG functions */ 1494 #if CS4280_DEBUG > 10 1495 static int 1496 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1497 uint32_t offset, uint32_t len) 1498 { 1499 uint32_t ctr, data; 1500 int err; 1501 1502 if ((offset & 3) || (len & 3)) 1503 return -1; 1504 1505 err = 0; 1506 len /= sizeof(uint32_t); 1507 for (ctr = 0; ctr < len; ctr++) { 1508 /* I cannot confirm this is the right thing 1509 * on BIG-ENDIAN machines 1510 */ 1511 data = BA1READ4(sc, offset+ctr*4); 1512 if (data != htole32(*(src+ctr))) { 1513 printf("0x%06x: 0x%08x(0x%08x)\n", 1514 offset+ctr*4, data, *(src+ctr)); 1515 *(src+ctr) = data; 1516 ++err; 1517 } 1518 } 1519 return err; 1520 } 1521 1522 static int 1523 cs4280_check_images(struct cs428x_softc *sc) 1524 { 1525 int idx, err; 1526 uint32_t offset; 1527 1528 offset = 0; 1529 err = 0; 1530 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1531 for (idx = 0; idx < 1; ++idx) { 1532 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1533 BA1Struct.memory[idx].offset, 1534 BA1Struct.memory[idx].size); 1535 if (err != 0) { 1536 aprint_error_dev(sc->sc_dev, 1537 "check_image failed at %d\n", idx); 1538 } 1539 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1540 } 1541 return err; 1542 } 1543 1544 #endif /* CS4280_DEBUG */ 1545
Indexes created Thu Oct 02 14:10:14 GMT 2025