cs4280.c revision 1.9
1 /* $NetBSD: cs4280.c,v 1.9 2000/12/28 22:59:11 sommerfeld Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * 44 */ 45 46 /* 47 * TODO 48 * Joystick support 49 */ 50 51 #if defined(CS4280_DEBUG) 52 #define DPRINTF(x) if (cs4280debug) printf x 53 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 54 int cs4280debug = 0; 55 #else 56 #define DPRINTF(x) 57 #define DPRINTFN(n,x) 58 #endif 59 60 #include "midi.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/fcntl.h> 66 #include <sys/malloc.h> 67 #include <sys/device.h> 68 #include <sys/types.h> 69 #include <sys/systm.h> 70 71 #include <dev/pci/pcidevs.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/cs4280reg.h> 74 #include <dev/pci/cs4280_image.h> 75 76 #include <sys/audioio.h> 77 #include <dev/audio_if.h> 78 #include <dev/midi_if.h> 79 #include <dev/mulaw.h> 80 #include <dev/auconv.h> 81 82 #include <dev/ic/ac97reg.h> 83 #include <dev/ic/ac97var.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define CSCC_PCI_BA0 0x10 89 #define CSCC_PCI_BA1 0x14 90 91 struct cs4280_dma { 92 bus_dmamap_t map; 93 caddr_t addr; /* real dma buffer */ 94 caddr_t dum; /* dummy buffer for audio driver */ 95 bus_dma_segment_t segs[1]; 96 int nsegs; 97 size_t size; 98 struct cs4280_dma *next; 99 }; 100 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 101 #define BUFADDR(p) ((void *)((p)->dum)) 102 #define KERNADDR(p) ((void *)((p)->addr)) 103 104 /* 105 * Software state 106 */ 107 struct cs4280_softc { 108 struct device sc_dev; 109 110 pci_intr_handle_t * sc_ih; 111 112 /* I/O (BA0) */ 113 bus_space_tag_t ba0t; 114 bus_space_handle_t ba0h; 115 116 /* BA1 */ 117 bus_space_tag_t ba1t; 118 bus_space_handle_t ba1h; 119 120 /* DMA */ 121 bus_dma_tag_t sc_dmatag; 122 struct cs4280_dma *sc_dmas; 123 124 void (*sc_pintr)(void *); /* dma completion intr handler */ 125 void *sc_parg; /* arg for sc_intr() */ 126 char *sc_ps, *sc_pe, *sc_pn; 127 int sc_pcount; 128 int sc_pi; 129 struct cs4280_dma *sc_pdma; 130 char *sc_pbuf; 131 #ifdef DIAGNOSTIC 132 char sc_prun; 133 #endif 134 135 void (*sc_rintr)(void *); /* dma completion intr handler */ 136 void *sc_rarg; /* arg for sc_intr() */ 137 char *sc_rs, *sc_re, *sc_rn; 138 int sc_rcount; 139 int sc_ri; 140 struct cs4280_dma *sc_rdma; 141 char *sc_rbuf; 142 int sc_rparam; /* record format */ 143 #ifdef DIAGNOSTIC 144 char sc_rrun; 145 #endif 146 147 #if NMIDI > 0 148 void (*sc_iintr)(void *, int); /* midi input ready handler */ 149 void (*sc_ointr)(void *); /* midi output ready handler */ 150 void *sc_arg; 151 #endif 152 153 u_int32_t pctl; 154 u_int32_t cctl; 155 156 struct ac97_codec_if *codec_if; 157 struct ac97_host_if host_if; 158 159 char sc_suspend; 160 void *sc_powerhook; /* Power Hook */ 161 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 162 }; 163 164 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 165 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 166 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 167 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 168 169 int cs4280_match __P((struct device *, struct cfdata *, void *)); 170 void cs4280_attach __P((struct device *, struct device *, void *)); 171 int cs4280_intr __P((void *)); 172 void cs4280_reset __P((void *)); 173 int cs4280_download_image __P((struct cs4280_softc *)); 174 175 int cs4280_download(struct cs4280_softc *, u_int32_t *, u_int32_t, u_int32_t); 176 int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 177 struct cs4280_dma *)); 178 int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 179 180 #ifdef CS4280_DEBUG 181 int cs4280_check_images __P((struct cs4280_softc *)); 182 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 183 u_int32_t); 184 #endif 185 186 struct cfattach clcs_ca = { 187 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 188 }; 189 190 int cs4280_init __P((struct cs4280_softc *, int)); 191 int cs4280_open __P((void *, int)); 192 void cs4280_close __P((void *)); 193 194 int cs4280_query_encoding __P((void *, struct audio_encoding *)); 195 int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 196 int cs4280_round_blocksize __P((void *, int)); 197 198 int cs4280_halt_output __P((void *)); 199 int cs4280_halt_input __P((void *)); 200 201 int cs4280_getdev __P((void *, struct audio_device *)); 202 203 int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 204 int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 205 int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 206 void *cs4280_malloc __P((void *, int, size_t, int, int)); 207 void cs4280_free __P((void *, void *, int)); 208 size_t cs4280_round_buffersize __P((void *, int, size_t)); 209 paddr_t cs4280_mappage __P((void *, void *, off_t, int)); 210 int cs4280_get_props __P((void *)); 211 int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 212 void *, struct audio_params *)); 213 int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 214 void *, struct audio_params *)); 215 216 217 void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 218 void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 219 int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 220 char *)); 221 int cs4280_src_wait __P((struct cs4280_softc *)); 222 int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 223 int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 224 int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 225 void cs4280_reset_codec __P((void *sc)); 226 227 void cs4280_power __P((int, void *)); 228 229 void cs4280_clear_fifos __P((struct cs4280_softc *)); 230 231 #if NMIDI > 0 232 void cs4280_midi_close __P((void*)); 233 void cs4280_midi_getinfo __P((void *, struct midi_info *)); 234 int cs4280_midi_open __P((void *, int, void (*)(void *, int), 235 void (*)(void *), void *)); 236 int cs4280_midi_output __P((void *, int)); 237 #endif 238 239 struct audio_hw_if cs4280_hw_if = { 240 cs4280_open, 241 cs4280_close, 242 NULL, 243 cs4280_query_encoding, 244 cs4280_set_params, 245 cs4280_round_blocksize, 246 NULL, 247 NULL, 248 NULL, 249 NULL, 250 NULL, 251 cs4280_halt_output, 252 cs4280_halt_input, 253 NULL, 254 cs4280_getdev, 255 NULL, 256 cs4280_mixer_set_port, 257 cs4280_mixer_get_port, 258 cs4280_query_devinfo, 259 cs4280_malloc, 260 cs4280_free, 261 cs4280_round_buffersize, 262 cs4280_mappage, 263 cs4280_get_props, 264 cs4280_trigger_output, 265 cs4280_trigger_input, 266 }; 267 268 #if NMIDI > 0 269 struct midi_hw_if cs4280_midi_hw_if = { 270 cs4280_midi_open, 271 cs4280_midi_close, 272 cs4280_midi_output, 273 cs4280_midi_getinfo, 274 0, 275 }; 276 #endif 277 278 279 280 struct audio_device cs4280_device = { 281 "CS4280", 282 "", 283 "cs4280" 284 }; 285 286 287 int 288 cs4280_match(parent, match, aux) 289 struct device *parent; 290 struct cfdata *match; 291 void *aux; 292 { 293 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 294 295 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 296 return (0); 297 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 298 #if 0 /* I can't confirm */ 299 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 300 #endif 301 ) 302 return (1); 303 return (0); 304 } 305 306 int 307 cs4280_read_codec(sc_, add, data) 308 void *sc_; 309 u_int8_t add; 310 u_int16_t *data; 311 { 312 struct cs4280_softc *sc = sc_; 313 int n; 314 315 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 316 /* 317 * Make sure that there is not data sitting around from a preivous 318 * uncompleted access. 319 */ 320 BA0READ4(sc, CS4280_ACSDA); 321 322 /* Set up AC97 control registers. */ 323 BA0WRITE4(sc, CS4280_ACCAD, add); 324 BA0WRITE4(sc, CS4280_ACCDA, 0); 325 BA0WRITE4(sc, CS4280_ACCTL, 326 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 327 328 if (cs4280_src_wait(sc) < 0) { 329 printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 330 sc->sc_dev.dv_xname, add); 331 return (1); 332 } 333 334 /* wait for valid status bit is active */ 335 n = 0; 336 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 337 delay(1); 338 while (++n > 1000) { 339 printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 340 sc->sc_dev.dv_xname, add); 341 return (1); 342 } 343 } 344 *data = BA0READ4(sc, CS4280_ACSDA); 345 DPRINTFN(5,("data=0x%04x\n", *data)); 346 return (0); 347 } 348 349 int 350 cs4280_write_codec(sc_, add, data) 351 void *sc_; 352 u_int8_t add; 353 u_int16_t data; 354 { 355 struct cs4280_softc *sc = sc_; 356 357 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 358 BA0WRITE4(sc, CS4280_ACCAD, add); 359 BA0WRITE4(sc, CS4280_ACCDA, data); 360 BA0WRITE4(sc, CS4280_ACCTL, 361 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 362 363 if (cs4280_src_wait(sc) < 0) { 364 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 365 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 366 return (1); 367 } 368 return (0); 369 } 370 371 int 372 cs4280_src_wait(sc) 373 struct cs4280_softc *sc; 374 { 375 int n; 376 n = 0; 377 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 378 delay(1000); 379 while (++n > 1000) 380 return (-1); 381 } 382 return (0); 383 } 384 385 386 void 387 cs4280_set_adc_rate(sc, rate) 388 struct cs4280_softc *sc; 389 int rate; 390 { 391 /* calculate capture rate: 392 * 393 * capture_coefficient_increment = -round(rate*128*65536/48000; 394 * capture_phase_increment = floor(48000*65536*1024/rate); 395 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 396 * cy = floor(cx/200); 397 * capture_sample_rate_correction = cx - 200*cy; 398 * capture_delay = ceil(24*48000/rate); 399 * capture_num_triplets = floor(65536*rate/24000); 400 * capture_group_length = 24000/GCD(rate, 24000); 401 * where GCD means "Greatest Common Divisor". 402 * 403 * capture_coefficient_increment, capture_phase_increment and 404 * capture_num_triplets are 32-bit signed quantities. 405 * capture_sample_rate_correction and capture_group_length are 406 * 16-bit signed quantities. 407 * capture_delay is a 14-bit unsigned quantity. 408 */ 409 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 410 u_int16_t csrc, cgl, cdlay; 411 412 /* XXX 413 * Even though, embedded_audio_spec says capture rate range 11025 to 414 * 48000, dhwiface.cpp says, 415 * 416 * "We can only decimate by up to a factor of 1/9th the hardware rate. 417 * Return an error if an attempt is made to stray outside that limit." 418 * 419 * so assume range as 48000/9 to 48000 420 */ 421 422 if (rate < 8000) 423 rate = 8000; 424 if (rate > 48000) 425 rate = 48000; 426 427 cx = rate << 16; 428 cci = cx / 48000; 429 cx -= cci * 48000; 430 cx <<= 7; 431 cci <<= 7; 432 cci += cx / 48000; 433 cci = - cci; 434 435 cx = 48000 << 16; 436 cpi = cx / rate; 437 cx -= cpi * rate; 438 cx <<= 10; 439 cpi <<= 10; 440 cy = cx / rate; 441 cpi += cy; 442 cx -= cy * rate; 443 444 cy = cx / 200; 445 csrc = cx - 200*cy; 446 447 cdlay = ((48000 * 24) + rate - 1) / rate; 448 #if 0 449 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 450 #endif 451 452 cnt = rate << 16; 453 cnt /= 24000; 454 455 cgl = 1; 456 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 457 if (((rate / tmp1) * tmp1) != rate) 458 cgl *= 2; 459 } 460 if (((rate / 3) * 3) != rate) 461 cgl *= 3; 462 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 463 if (((rate / tmp1) * tmp1) != rate) 464 cgl *= 5; 465 } 466 #if 0 467 /* XXX what manual says */ 468 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 469 tmp1 |= csrc<<16; 470 BA1WRITE4(sc, CS4280_CSRC, tmp1); 471 #else 472 /* suggested by cs461x.c (ALSA driver) */ 473 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 474 #endif 475 476 #if 0 477 /* I am confused. The sample rate calculation section says 478 * cci *is* 32-bit signed quantity but in the parameter description 479 * section, CCI only assigned 16bit. 480 * I believe size of the variable. 481 */ 482 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 483 tmp1 |= cci<<16; 484 BA1WRITE4(sc, CS4280_CCI, tmp1); 485 #else 486 BA1WRITE4(sc, CS4280_CCI, cci); 487 #endif 488 489 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 490 tmp1 |= cdlay <<18; 491 BA1WRITE4(sc, CS4280_CD, tmp1); 492 493 BA1WRITE4(sc, CS4280_CPI, cpi); 494 495 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 496 tmp1 |= cgl; 497 BA1WRITE4(sc, CS4280_CGL, tmp1); 498 499 BA1WRITE4(sc, CS4280_CNT, cnt); 500 501 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 502 tmp1 |= cgl; 503 BA1WRITE4(sc, CS4280_CGC, tmp1); 504 } 505 506 void 507 cs4280_set_dac_rate(sc, rate) 508 struct cs4280_softc *sc; 509 int rate; 510 { 511 /* 512 * playback rate may range from 8000Hz to 48000Hz 513 * 514 * play_phase_increment = floor(rate*65536*1024/48000) 515 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 516 * py=floor(px/200) 517 * play_sample_rate_correction = px - 200*py 518 * 519 * play_phase_increment is a 32bit signed quantity. 520 * play_sample_rate_correction is a 16bit signed quantity. 521 */ 522 int32_t ppi; 523 int16_t psrc; 524 u_int32_t px, py; 525 526 if (rate < 8000) 527 rate = 8000; 528 if (rate > 48000) 529 rate = 48000; 530 px = rate << 16; 531 ppi = px/48000; 532 px -= ppi*48000; 533 ppi <<= 10; 534 px <<= 10; 535 py = px / 48000; 536 ppi += py; 537 px -= py*48000; 538 py = px/200; 539 px -= py*200; 540 psrc = px; 541 #if 0 542 /* what manual says */ 543 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 544 BA1WRITE4(sc, CS4280_PSRC, 545 ( ((psrc<<16) & PSRC_MASK) | px )); 546 #else 547 /* suggested by cs461x.c (ALSA driver) */ 548 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 549 #endif 550 BA1WRITE4(sc, CS4280_PPI, ppi); 551 } 552 553 void 554 cs4280_attach(parent, self, aux) 555 struct device *parent; 556 struct device *self; 557 void *aux; 558 { 559 struct cs4280_softc *sc = (struct cs4280_softc *)self; 560 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 561 pci_chipset_tag_t pc = pa->pa_pc; 562 char const *intrstr; 563 pci_intr_handle_t ih; 564 pcireg_t csr; 565 char devinfo[256]; 566 mixer_ctrl_t ctl; 567 u_int32_t mem; 568 569 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 570 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 571 572 /* Map I/O register */ 573 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 574 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 575 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 576 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 577 return; 578 } 579 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 580 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 581 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 582 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 583 return; 584 } 585 586 sc->sc_dmatag = pa->pa_dmat; 587 588 /* Enable the device (set bus master flag) */ 589 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 590 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 591 csr | PCI_COMMAND_MASTER_ENABLE); 592 593 /* LATENCY_TIMER setting */ 594 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 595 if ( PCI_LATTIMER(mem) < 32 ) { 596 mem &= 0xffff00ff; 597 mem |= 0x00002000; 598 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 599 } 600 601 /* Map and establish the interrupt. */ 602 if (pci_intr_map(pa, &ih)) { 603 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 604 return; 605 } 606 intrstr = pci_intr_string(pc, ih); 607 608 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 609 if (sc->sc_ih == NULL) { 610 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 611 if (intrstr != NULL) 612 printf(" at %s", intrstr); 613 printf("\n"); 614 return; 615 } 616 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 617 618 /* Initialization */ 619 if(cs4280_init(sc, 1) != 0) 620 return; 621 622 /* AC 97 attachement */ 623 sc->host_if.arg = sc; 624 sc->host_if.attach = cs4280_attach_codec; 625 sc->host_if.read = cs4280_read_codec; 626 sc->host_if.write = cs4280_write_codec; 627 sc->host_if.reset = cs4280_reset_codec; 628 629 if (ac97_attach(&sc->host_if) != 0) { 630 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 631 return; 632 } 633 634 /* Turn mute off of DAC, CD and master volumes by default */ 635 ctl.type = AUDIO_MIXER_ENUM; 636 ctl.un.ord = 0; /* off */ 637 638 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 639 AudioNmaster, AudioNmute); 640 cs4280_mixer_set_port(sc, &ctl); 641 642 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 643 AudioNdac, AudioNmute); 644 cs4280_mixer_set_port(sc, &ctl); 645 646 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 647 AudioNcd, AudioNmute); 648 cs4280_mixer_set_port(sc, &ctl); 649 650 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 651 652 #if NMIDI > 0 653 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 654 #endif 655 sc->sc_suspend = PWR_RESUME; 656 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 657 } 658 659 int 660 cs4280_intr(p) 661 void *p; 662 { 663 /* 664 * XXX 665 * 666 * Since CS4280 has only 4kB dma buffer and 667 * interrupt occurs every 2kB block, I create dummy buffer 668 * which returns to audio driver and actual dma buffer 669 * using in DMA transfer. 670 * 671 * 672 * ring buffer in audio.c is pointed by BUFADDR 673 * <------ ring buffer size == 64kB ------> 674 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 675 * |= = = =|= = = =|= = = =|= = = =|= = = =| 676 * | | | | | | <- call audio_intp every 677 * sc->sc_[pr]_count time. 678 * 679 * actual dma buffer is pointed by KERNADDR 680 * <-> dma buffer size = 4kB 681 * |= =| 682 * 683 * 684 */ 685 struct cs4280_softc *sc = p; 686 u_int32_t intr, mem; 687 char * empty_dma; 688 689 /* grab interrupt register then clear it */ 690 intr = BA0READ4(sc, CS4280_HISR); 691 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 692 693 /* not for me */ 694 if((intr & HISR_INTENA) == 0 ) 695 return 0; 696 697 /* Playback Interrupt */ 698 if (intr & HISR_PINT) { 699 mem = BA1READ4(sc, CS4280_PFIE); 700 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 701 if (sc->sc_pintr) { 702 if ((sc->sc_pi%sc->sc_pcount) == 0) 703 sc->sc_pintr(sc->sc_parg); 704 } else { 705 printf("unexpected play intr\n"); 706 } 707 /* copy buffer */ 708 ++sc->sc_pi; 709 empty_dma = sc->sc_pdma->addr; 710 if (sc->sc_pi&1) 711 empty_dma += CS4280_ICHUNK; 712 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 713 sc->sc_pn += CS4280_ICHUNK; 714 if (sc->sc_pn >= sc->sc_pe) 715 sc->sc_pn = sc->sc_ps; 716 BA1WRITE4(sc, CS4280_PFIE, mem); 717 } 718 /* Capture Interrupt */ 719 if (intr & HISR_CINT) { 720 int i; 721 int16_t rdata; 722 723 mem = BA1READ4(sc, CS4280_CIE); 724 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 725 ++sc->sc_ri; 726 empty_dma = sc->sc_rdma->addr; 727 if ((sc->sc_ri&1) == 0) 728 empty_dma += CS4280_ICHUNK; 729 730 /* 731 * XXX 732 * I think this audio data conversion should be 733 * happend in upper layer, but I put this here 734 * since there is no conversion function available. 735 */ 736 switch(sc->sc_rparam) { 737 case CF_16BIT_STEREO: 738 /* just copy it */ 739 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 740 sc->sc_rn += CS4280_ICHUNK; 741 break; 742 case CF_16BIT_MONO: 743 for (i = 0; i < 512; i++) { 744 rdata = *((int16_t *)empty_dma)++>>1; 745 rdata += *((int16_t *)empty_dma)++>>1; 746 *((int16_t *)sc->sc_rn)++ = rdata; 747 } 748 break; 749 case CF_8BIT_STEREO: 750 for (i = 0; i < 512; i++) { 751 rdata = *((int16_t*)empty_dma)++; 752 *sc->sc_rn++ = rdata >> 8; 753 rdata = *((int16_t*)empty_dma)++; 754 *sc->sc_rn++ = rdata >> 8; 755 } 756 break; 757 case CF_8BIT_MONO: 758 for (i = 0; i < 512; i++) { 759 rdata = *((int16_t*)empty_dma)++ >>1; 760 rdata += *((int16_t*)empty_dma)++ >>1; 761 *sc->sc_rn++ = rdata >>8; 762 } 763 break; 764 default: 765 /* Should not reach here */ 766 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 767 } 768 if (sc->sc_rn >= sc->sc_re) 769 sc->sc_rn = sc->sc_rs; 770 BA1WRITE4(sc, CS4280_CIE, mem); 771 if (sc->sc_rintr) { 772 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 773 sc->sc_rintr(sc->sc_rarg); 774 } else { 775 printf("unexpected record intr\n"); 776 } 777 } 778 779 #if NMIDI > 0 780 /* Midi port Interrupt */ 781 if (intr & HISR_MIDI) { 782 int data; 783 784 DPRINTF(("i: %d: ", 785 BA0READ4(sc, CS4280_MIDSR))); 786 /* Read the received data */ 787 while ((sc->sc_iintr != NULL) && 788 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 789 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 790 DPRINTF(("r:%x\n",data)); 791 sc->sc_iintr(sc->sc_arg, data); 792 } 793 794 /* Write the data */ 795 #if 1 796 /* XXX: 797 * It seems "Transmit Buffer Full" never activate until EOI 798 * is deliverd. Shall I throw EOI top of this routine ? 799 */ 800 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 801 DPRINTF(("w: ")); 802 if (sc->sc_ointr != NULL) 803 sc->sc_ointr(sc->sc_arg); 804 } 805 #else 806 while ((sc->sc_ointr != NULL) && 807 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 808 DPRINTF(("w: ")); 809 sc->sc_ointr(sc->sc_arg); 810 } 811 #endif 812 DPRINTF(("\n")); 813 } 814 #endif 815 816 return (1); 817 } 818 819 820 /* Download Proceessor Code and Data image */ 821 822 int 823 cs4280_download(sc, src, offset, len) 824 struct cs4280_softc *sc; 825 u_int32_t *src; 826 u_int32_t offset, len; 827 { 828 u_int32_t ctr; 829 830 #ifdef CS4280_DEBUG 831 u_int32_t con, data; 832 u_int8_t c0,c1,c2,c3; 833 #endif 834 if ((offset&3) || (len&3)) 835 return (-1); 836 837 len /= sizeof(u_int32_t); 838 for (ctr = 0; ctr < len; ctr++) { 839 /* XXX: 840 * I cannot confirm this is the right thing or not 841 * on BIG-ENDIAN machines. 842 */ 843 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 844 #ifdef CS4280_DEBUG 845 data = htole32(*(src+ctr)); 846 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 847 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 848 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 849 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 850 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 851 if (data != con ) { 852 printf("0x%06x: write=0x%08x read=0x%08x\n", 853 offset+ctr*4, data, con); 854 return (-1); 855 } 856 #endif 857 } 858 return (0); 859 } 860 861 int 862 cs4280_download_image(sc) 863 struct cs4280_softc *sc; 864 { 865 int idx, err; 866 u_int32_t offset = 0; 867 868 err = 0; 869 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 870 err = cs4280_download(sc, &BA1Struct.map[offset], 871 BA1Struct.memory[idx].offset, 872 BA1Struct.memory[idx].size); 873 if (err != 0) { 874 printf("%s: load_image failed at %d\n", 875 sc->sc_dev.dv_xname, idx); 876 return (-1); 877 } 878 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 879 } 880 return (err); 881 } 882 883 #ifdef CS4280_DEBUG 884 int 885 cs4280_checkimage(sc, src, offset, len) 886 struct cs4280_softc *sc; 887 u_int32_t *src; 888 u_int32_t offset, len; 889 { 890 u_int32_t ctr, data; 891 int err = 0; 892 893 if ((offset&3) || (len&3)) 894 return -1; 895 896 len /= sizeof(u_int32_t); 897 for (ctr = 0; ctr < len; ctr++) { 898 /* I cannot confirm this is the right thing 899 * on BIG-ENDIAN machines 900 */ 901 data = BA1READ4(sc, offset+ctr*4); 902 if (data != htole32(*(src+ctr))) { 903 printf("0x%06x: 0x%08x(0x%08x)\n", 904 offset+ctr*4, data, *(src+ctr)); 905 *(src+ctr) = data; 906 ++err; 907 } 908 } 909 return (err); 910 } 911 912 int 913 cs4280_check_images(sc) 914 struct cs4280_softc *sc; 915 { 916 int idx, err; 917 u_int32_t offset = 0; 918 919 err = 0; 920 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 921 for (idx = 0; idx < 1; ++idx) { 922 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 923 BA1Struct.memory[idx].offset, 924 BA1Struct.memory[idx].size); 925 if (err != 0) { 926 printf("%s: check_image failed at %d\n", 927 sc->sc_dev.dv_xname, idx); 928 } 929 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 930 } 931 return (err); 932 } 933 934 #endif 935 936 int 937 cs4280_attach_codec(sc_, codec_if) 938 void *sc_; 939 struct ac97_codec_if *codec_if; 940 { 941 struct cs4280_softc *sc = sc_; 942 943 sc->codec_if = codec_if; 944 return (0); 945 } 946 947 void 948 cs4280_reset_codec(sc_) 949 void *sc_; 950 { 951 struct cs4280_softc *sc = sc_; 952 int n; 953 954 /* Reset codec */ 955 BA0WRITE4(sc, CS4280_ACCTL, 0); 956 delay(100); /* delay 100us */ 957 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 958 959 /* 960 * It looks like we do the following procedure, too 961 */ 962 963 /* Enable AC-link sync generation */ 964 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 965 delay(50*1000); /* XXX delay 50ms */ 966 967 /* Assert valid frame signal */ 968 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 969 970 /* Wait for valid AC97 input slot */ 971 n = 0; 972 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 973 delay(1000); 974 if (++n > 1000) { 975 printf("reset_codec: AC97 inputs slot ready timeout\n"); 976 return; 977 } 978 } 979 } 980 981 982 /* Processor Soft Reset */ 983 void 984 cs4280_reset(sc_) 985 void *sc_; 986 { 987 struct cs4280_softc *sc = sc_; 988 989 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 990 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 991 delay(100); 992 /* Clear RSTSP bit in SPCR */ 993 BA1WRITE4(sc, CS4280_SPCR, 0); 994 /* enable DMA reqest */ 995 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 996 } 997 998 int 999 cs4280_open(addr, flags) 1000 void *addr; 1001 int flags; 1002 { 1003 return (0); 1004 } 1005 1006 void 1007 cs4280_close(addr) 1008 void *addr; 1009 { 1010 struct cs4280_softc *sc = addr; 1011 1012 cs4280_halt_output(sc); 1013 cs4280_halt_input(sc); 1014 1015 sc->sc_pintr = 0; 1016 sc->sc_rintr = 0; 1017 } 1018 1019 int 1020 cs4280_query_encoding(addr, fp) 1021 void *addr; 1022 struct audio_encoding *fp; 1023 { 1024 switch (fp->index) { 1025 case 0: 1026 strcpy(fp->name, AudioEulinear); 1027 fp->encoding = AUDIO_ENCODING_ULINEAR; 1028 fp->precision = 8; 1029 fp->flags = 0; 1030 break; 1031 case 1: 1032 strcpy(fp->name, AudioEmulaw); 1033 fp->encoding = AUDIO_ENCODING_ULAW; 1034 fp->precision = 8; 1035 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1036 break; 1037 case 2: 1038 strcpy(fp->name, AudioEalaw); 1039 fp->encoding = AUDIO_ENCODING_ALAW; 1040 fp->precision = 8; 1041 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1042 break; 1043 case 3: 1044 strcpy(fp->name, AudioEslinear); 1045 fp->encoding = AUDIO_ENCODING_SLINEAR; 1046 fp->precision = 8; 1047 fp->flags = 0; 1048 break; 1049 case 4: 1050 strcpy(fp->name, AudioEslinear_le); 1051 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1052 fp->precision = 16; 1053 fp->flags = 0; 1054 break; 1055 case 5: 1056 strcpy(fp->name, AudioEulinear_le); 1057 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1058 fp->precision = 16; 1059 fp->flags = 0; 1060 break; 1061 case 6: 1062 strcpy(fp->name, AudioEslinear_be); 1063 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1064 fp->precision = 16; 1065 fp->flags = 0; 1066 break; 1067 case 7: 1068 strcpy(fp->name, AudioEulinear_be); 1069 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1070 fp->precision = 16; 1071 fp->flags = 0; 1072 break; 1073 default: 1074 return (EINVAL); 1075 } 1076 return (0); 1077 } 1078 1079 int 1080 cs4280_set_params(addr, setmode, usemode, play, rec) 1081 void *addr; 1082 int setmode, usemode; 1083 struct audio_params *play, *rec; 1084 { 1085 struct cs4280_softc *sc = addr; 1086 struct audio_params *p; 1087 int mode; 1088 1089 for (mode = AUMODE_RECORD; mode != -1; 1090 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1091 if ((setmode & mode) == 0) 1092 continue; 1093 1094 p = mode == AUMODE_PLAY ? play : rec; 1095 1096 if (p == play) { 1097 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1098 p->sample_rate, p->precision, p->channels)); 1099 /* play back data format may be 8- or 16-bit and 1100 * either stereo or mono. 1101 * playback rate may range from 8000Hz to 48000Hz 1102 */ 1103 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1104 (p->precision != 8 && p->precision != 16) || 1105 (p->channels != 1 && p->channels != 2) ) { 1106 return (EINVAL); 1107 } 1108 } else { 1109 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1110 p->sample_rate, p->precision, p->channels)); 1111 /* capture data format must be 16bit stereo 1112 * and sample rate range from 11025Hz to 48000Hz. 1113 * 1114 * XXX: it looks like to work with 8000Hz, 1115 * although data sheets say lower limit is 1116 * 11025 Hz. 1117 */ 1118 1119 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1120 (p->precision != 8 && p->precision != 16) || 1121 (p->channels != 1 && p->channels != 2) ) { 1122 return (EINVAL); 1123 } 1124 } 1125 p->factor = 1; 1126 p->sw_code = 0; 1127 1128 /* capturing data is slinear */ 1129 switch (p->encoding) { 1130 case AUDIO_ENCODING_SLINEAR_BE: 1131 if (mode == AUMODE_RECORD) { 1132 if (p->precision == 16) 1133 p->sw_code = swap_bytes; 1134 } 1135 break; 1136 case AUDIO_ENCODING_SLINEAR_LE: 1137 break; 1138 case AUDIO_ENCODING_ULINEAR_BE: 1139 if (mode == AUMODE_RECORD) { 1140 if (p->precision == 16) 1141 p->sw_code = change_sign16_swap_bytes_le; 1142 else 1143 p->sw_code = change_sign8; 1144 } 1145 break; 1146 case AUDIO_ENCODING_ULINEAR_LE: 1147 if (mode == AUMODE_RECORD) { 1148 if (p->precision == 16) 1149 p->sw_code = change_sign16_le; 1150 else 1151 p->sw_code = change_sign8; 1152 } 1153 break; 1154 case AUDIO_ENCODING_ULAW: 1155 if (mode == AUMODE_PLAY) { 1156 p->factor = 2; 1157 p->sw_code = mulaw_to_slinear16_le; 1158 } else { 1159 p->sw_code = slinear8_to_mulaw; 1160 } 1161 break; 1162 case AUDIO_ENCODING_ALAW: 1163 if (mode == AUMODE_PLAY) { 1164 p->factor = 2; 1165 p->sw_code = alaw_to_slinear16_le; 1166 } else { 1167 p->sw_code = slinear8_to_alaw; 1168 } 1169 break; 1170 default: 1171 return (EINVAL); 1172 } 1173 } 1174 1175 /* set sample rate */ 1176 cs4280_set_dac_rate(sc, play->sample_rate); 1177 cs4280_set_adc_rate(sc, rec->sample_rate); 1178 return (0); 1179 } 1180 1181 int 1182 cs4280_round_blocksize(hdl, blk) 1183 void *hdl; 1184 int blk; 1185 { 1186 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1187 } 1188 1189 size_t 1190 cs4280_round_buffersize(addr, direction, size) 1191 void *addr; 1192 int direction; 1193 size_t size; 1194 { 1195 /* although real dma buffer size is 4KB, 1196 * let the audio.c driver use a larger buffer. 1197 * ( suggested by Lennart Augustsson. ) 1198 */ 1199 return (size); 1200 } 1201 1202 int 1203 cs4280_get_props(hdl) 1204 void *hdl; 1205 { 1206 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1207 #ifdef notyet 1208 /* XXX 1209 * How can I mmap ? 1210 */ 1211 AUDIO_PROP_MMAP 1212 #endif 1213 1214 } 1215 1216 int 1217 cs4280_mixer_get_port(addr, cp) 1218 void *addr; 1219 mixer_ctrl_t *cp; 1220 { 1221 struct cs4280_softc *sc = addr; 1222 1223 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1224 } 1225 1226 paddr_t 1227 cs4280_mappage(addr, mem, off, prot) 1228 void *addr; 1229 void *mem; 1230 off_t off; 1231 int prot; 1232 { 1233 struct cs4280_softc *sc = addr; 1234 struct cs4280_dma *p; 1235 1236 if (off < 0) 1237 return (-1); 1238 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1239 ; 1240 if (!p) { 1241 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1242 return (-1); 1243 } 1244 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1245 off, prot, BUS_DMA_WAITOK)); 1246 } 1247 1248 1249 int 1250 cs4280_query_devinfo(addr, dip) 1251 void *addr; 1252 mixer_devinfo_t *dip; 1253 { 1254 struct cs4280_softc *sc = addr; 1255 1256 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1257 } 1258 1259 int 1260 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1261 struct cs4280_softc *sc; 1262 char *class, *device, *qualifier; 1263 { 1264 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1265 device, qualifier)); 1266 } 1267 1268 int 1269 cs4280_halt_output(addr) 1270 void *addr; 1271 { 1272 struct cs4280_softc *sc = addr; 1273 u_int32_t mem; 1274 1275 mem = BA1READ4(sc, CS4280_PCTL); 1276 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1277 #ifdef DIAGNOSTIC 1278 sc->sc_prun = 0; 1279 #endif 1280 return (0); 1281 } 1282 1283 int 1284 cs4280_halt_input(addr) 1285 void *addr; 1286 { 1287 struct cs4280_softc *sc = addr; 1288 u_int32_t mem; 1289 1290 mem = BA1READ4(sc, CS4280_CCTL); 1291 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1292 #ifdef DIAGNOSTIC 1293 sc->sc_rrun = 0; 1294 #endif 1295 return (0); 1296 } 1297 1298 int 1299 cs4280_getdev(addr, retp) 1300 void *addr; 1301 struct audio_device *retp; 1302 { 1303 *retp = cs4280_device; 1304 return (0); 1305 } 1306 1307 int 1308 cs4280_mixer_set_port(addr, cp) 1309 void *addr; 1310 mixer_ctrl_t *cp; 1311 { 1312 struct cs4280_softc *sc = addr; 1313 int val; 1314 1315 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1316 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1317 return (val); 1318 } 1319 1320 1321 int 1322 cs4280_freemem(sc, p) 1323 struct cs4280_softc *sc; 1324 struct cs4280_dma *p; 1325 { 1326 bus_dmamap_unload(sc->sc_dmatag, p->map); 1327 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1328 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1329 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1330 return (0); 1331 } 1332 1333 int 1334 cs4280_allocmem(sc, size, align, p) 1335 struct cs4280_softc *sc; 1336 size_t size; 1337 size_t align; 1338 struct cs4280_dma *p; 1339 { 1340 int error; 1341 1342 /* XXX */ 1343 p->size = size; 1344 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1345 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1346 &p->nsegs, BUS_DMA_NOWAIT); 1347 if (error) { 1348 printf("%s: unable to allocate dma, error=%d\n", 1349 sc->sc_dev.dv_xname, error); 1350 return (error); 1351 } 1352 1353 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1354 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1355 if (error) { 1356 printf("%s: unable to map dma, error=%d\n", 1357 sc->sc_dev.dv_xname, error); 1358 goto free; 1359 } 1360 1361 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1362 0, BUS_DMA_NOWAIT, &p->map); 1363 if (error) { 1364 printf("%s: unable to create dma map, error=%d\n", 1365 sc->sc_dev.dv_xname, error); 1366 goto unmap; 1367 } 1368 1369 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1370 BUS_DMA_NOWAIT); 1371 if (error) { 1372 printf("%s: unable to load dma map, error=%d\n", 1373 sc->sc_dev.dv_xname, error); 1374 goto destroy; 1375 } 1376 return (0); 1377 1378 destroy: 1379 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1380 unmap: 1381 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1382 free: 1383 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1384 return (error); 1385 } 1386 1387 1388 void * 1389 cs4280_malloc(addr, direction, size, pool, flags) 1390 void *addr; 1391 int direction; 1392 size_t size; 1393 int pool, flags; 1394 { 1395 struct cs4280_softc *sc = addr; 1396 struct cs4280_dma *p; 1397 caddr_t q; 1398 int error; 1399 1400 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1401 q = malloc(size, pool, flags); 1402 if (!q) 1403 return (0); 1404 p = malloc(sizeof(*p), pool, flags); 1405 if (!p) { 1406 free(q,pool); 1407 return (0); 1408 } 1409 /* 1410 * cs4280 has fixed 4kB buffer 1411 */ 1412 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1413 1414 if (error) { 1415 free(q, pool); 1416 free(p, pool); 1417 return (0); 1418 } 1419 1420 p->next = sc->sc_dmas; 1421 sc->sc_dmas = p; 1422 p->dum = q; /* return to audio driver */ 1423 1424 return (p->dum); 1425 } 1426 1427 void 1428 cs4280_free(addr, ptr, pool) 1429 void *addr; 1430 void *ptr; 1431 int pool; 1432 { 1433 struct cs4280_softc *sc = addr; 1434 struct cs4280_dma **pp, *p; 1435 1436 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1437 if (BUFADDR(p) == ptr) { 1438 cs4280_freemem(sc, p); 1439 *pp = p->next; 1440 free(p->dum, pool); 1441 free(p, pool); 1442 return; 1443 } 1444 } 1445 } 1446 1447 int 1448 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1449 void *addr; 1450 void *start, *end; 1451 int blksize; 1452 void (*intr) __P((void *)); 1453 void *arg; 1454 struct audio_params *param; 1455 { 1456 struct cs4280_softc *sc = addr; 1457 u_int32_t pfie, pctl, mem, pdtc; 1458 struct cs4280_dma *p; 1459 1460 #ifdef DIAGNOSTIC 1461 if (sc->sc_prun) 1462 printf("cs4280_trigger_output: already running\n"); 1463 sc->sc_prun = 1; 1464 #endif 1465 1466 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1467 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1468 sc->sc_pintr = intr; 1469 sc->sc_parg = arg; 1470 1471 /* stop playback DMA */ 1472 mem = BA1READ4(sc, CS4280_PCTL); 1473 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1474 1475 /* setup PDTC */ 1476 pdtc = BA1READ4(sc, CS4280_PDTC); 1477 pdtc &= ~PDTC_MASK; 1478 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1479 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1480 1481 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1482 param->precision, param->factor, param->channels, 1483 param->encoding)); 1484 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1485 ; 1486 if (p == NULL) { 1487 printf("cs4280_trigger_output: bad addr %p\n", start); 1488 return (EINVAL); 1489 } 1490 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1491 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1492 "4kB align\n", DMAADDR(p)); 1493 return (EINVAL); 1494 } 1495 1496 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1497 sc->sc_ps = (char *)start; 1498 sc->sc_pe = (char *)end; 1499 sc->sc_pdma = p; 1500 sc->sc_pbuf = KERNADDR(p); 1501 sc->sc_pi = 0; 1502 sc->sc_pn = sc->sc_ps; 1503 if (blksize >= CS4280_DCHUNK) { 1504 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1505 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1506 ++sc->sc_pi; 1507 } else { 1508 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1509 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1510 } 1511 1512 /* initiate playback dma */ 1513 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1514 1515 /* set PFIE */ 1516 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1517 1518 if (param->precision * param->factor == 8) 1519 pfie |= PFIE_8BIT; 1520 if (param->channels == 1) 1521 pfie |= PFIE_MONO; 1522 1523 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1524 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1525 pfie |= PFIE_SWAPPED; 1526 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1527 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1528 pfie |= PFIE_UNSIGNED; 1529 1530 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1531 1532 cs4280_set_dac_rate(sc, param->sample_rate); 1533 1534 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1535 pctl |= sc->pctl; 1536 BA1WRITE4(sc, CS4280_PCTL, pctl); 1537 return (0); 1538 } 1539 1540 int 1541 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1542 void *addr; 1543 void *start, *end; 1544 int blksize; 1545 void (*intr) __P((void *)); 1546 void *arg; 1547 struct audio_params *param; 1548 { 1549 struct cs4280_softc *sc = addr; 1550 u_int32_t cctl, cie; 1551 struct cs4280_dma *p; 1552 1553 #ifdef DIAGNOSTIC 1554 if (sc->sc_rrun) 1555 printf("cs4280_trigger_input: already running\n"); 1556 sc->sc_rrun = 1; 1557 #endif 1558 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1559 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1560 sc->sc_rintr = intr; 1561 sc->sc_rarg = arg; 1562 1563 sc->sc_ri = 0; 1564 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1565 sc->sc_rs = (char *)start; 1566 sc->sc_re = (char *)end; 1567 sc->sc_rn = sc->sc_rs; 1568 1569 /* setup format information for internal converter */ 1570 sc->sc_rparam = 0; 1571 if (param->precision == 8) { 1572 sc->sc_rparam += CF_8BIT; 1573 sc->sc_rcount <<= 1; 1574 } 1575 if (param->channels == 1) { 1576 sc->sc_rparam += CF_MONO; 1577 sc->sc_rcount <<= 1; 1578 } 1579 1580 /* stop capture DMA */ 1581 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1582 BA1WRITE4(sc, CS4280_CCTL, cctl); 1583 1584 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1585 ; 1586 if (!p) { 1587 printf("cs4280_trigger_input: bad addr %p\n", start); 1588 return (EINVAL); 1589 } 1590 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1591 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1592 "4kB align\n", DMAADDR(p)); 1593 return (EINVAL); 1594 } 1595 sc->sc_rdma = p; 1596 sc->sc_rbuf = KERNADDR(p); 1597 1598 /* initiate capture dma */ 1599 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1600 1601 /* set CIE */ 1602 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1603 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1604 1605 cs4280_set_adc_rate(sc, param->sample_rate); 1606 1607 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1608 cctl |= sc->cctl; 1609 BA1WRITE4(sc, CS4280_CCTL, cctl); 1610 return (0); 1611 } 1612 1613 int 1614 cs4280_init(sc, init) 1615 struct cs4280_softc *sc; 1616 int init; 1617 { 1618 int n; 1619 u_int32_t mem; 1620 1621 /* Start PLL out in known state */ 1622 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1623 /* Start serial ports out in known state */ 1624 BA0WRITE4(sc, CS4280_SERMC1, 0); 1625 1626 /* Specify type of CODEC */ 1627 /* XXX should not be here */ 1628 #define SERACC_CODEC_TYPE_1_03 1629 #ifdef SERACC_CODEC_TYPE_1_03 1630 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1631 #else 1632 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1633 #endif 1634 1635 /* Reset codec */ 1636 BA0WRITE4(sc, CS4280_ACCTL, 0); 1637 delay(100); /* delay 100us */ 1638 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1639 1640 /* Enable AC-link sync generation */ 1641 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1642 delay(50*1000); /* delay 50ms */ 1643 1644 /* Set the serial port timing configuration */ 1645 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1646 1647 /* Setup clock control */ 1648 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1649 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1650 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1651 1652 /* Power up the PLL */ 1653 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1654 delay(50*1000); /* delay 50ms */ 1655 1656 /* Turn on clock */ 1657 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1658 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1659 1660 /* Set the serial port FIFO pointer to the 1661 * first sample in FIFO. (not documented) */ 1662 cs4280_clear_fifos(sc); 1663 1664 #if 0 1665 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1666 BA0WRITE4(sc, CS4280_SERBSP, 0); 1667 #endif 1668 1669 /* Configure the serial port */ 1670 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1671 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1672 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1673 1674 /* Wait for CODEC ready */ 1675 n = 0; 1676 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1677 delay(125); 1678 if (++n > 1000) { 1679 printf("%s: codec ready timeout\n", 1680 sc->sc_dev.dv_xname); 1681 return(1); 1682 } 1683 } 1684 1685 /* Assert valid frame signal */ 1686 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1687 1688 /* Wait for valid AC97 input slot */ 1689 n = 0; 1690 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1691 (ACISV_ISV3 | ACISV_ISV4)) { 1692 delay(1000); 1693 if (++n > 1000) { 1694 printf("AC97 inputs slot ready timeout\n"); 1695 return(1); 1696 } 1697 } 1698 1699 /* Set AC97 output slot valid signals */ 1700 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1701 1702 /* reset the processor */ 1703 cs4280_reset(sc); 1704 1705 /* Download the image to the processor */ 1706 if (cs4280_download_image(sc) != 0) { 1707 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1708 return(1); 1709 } 1710 1711 /* Save playback parameter and then write zero. 1712 * this ensures that DMA doesn't immediately occur upon 1713 * starting the processor core 1714 */ 1715 mem = BA1READ4(sc, CS4280_PCTL); 1716 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1717 cs4280_halt_output(sc); 1718 1719 /* Save capture parameter and then write zero. 1720 * this ensures that DMA doesn't immediately occur upon 1721 * starting the processor core 1722 */ 1723 mem = BA1READ4(sc, CS4280_CCTL); 1724 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1725 cs4280_halt_input(sc); 1726 1727 /* Processor Startup Procedure */ 1728 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1729 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1730 1731 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1732 n = 0; 1733 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1734 delay(10); 1735 if (++n > 1000) { 1736 printf("SPCR 1->0 transition timeout\n"); 1737 return(1); 1738 } 1739 } 1740 1741 n = 0; 1742 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1743 delay(10); 1744 if (++n > 1000) { 1745 printf("SPCS 0->1 transition timeout\n"); 1746 return(1); 1747 } 1748 } 1749 /* Processor is now running !!! */ 1750 1751 /* Setup volume */ 1752 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1753 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1754 1755 /* Interrupt enable */ 1756 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1757 1758 /* playback interrupt enable */ 1759 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1760 mem |= PFIE_PI_ENABLE; 1761 BA1WRITE4(sc, CS4280_PFIE, mem); 1762 /* capture interrupt enable */ 1763 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1764 mem |= CIE_CI_ENABLE; 1765 BA1WRITE4(sc, CS4280_CIE, mem); 1766 1767 #if NMIDI > 0 1768 /* Reset midi port */ 1769 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1770 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1771 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1772 /* midi interrupt enable */ 1773 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1774 BA0WRITE4(sc, CS4280_MIDCR, mem); 1775 #endif 1776 return(0); 1777 } 1778 1779 void 1780 cs4280_power(why, v) 1781 int why; 1782 void *v; 1783 { 1784 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1785 int i; 1786 1787 DPRINTF(("%s: cs4280_power why=%d\n", 1788 sc->sc_dev.dv_xname, why)); 1789 switch (why) { 1790 case PWR_SUSPEND: 1791 case PWR_STANDBY: 1792 sc->sc_suspend = why; 1793 1794 cs4280_halt_output(sc); 1795 cs4280_halt_input(sc); 1796 /* Save AC97 registers */ 1797 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1798 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1799 continue; 1800 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]); 1801 } 1802 /* should I powerdown here ? */ 1803 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1804 break; 1805 case PWR_RESUME: 1806 if (sc->sc_suspend == PWR_RESUME) { 1807 printf("cs4280_power: odd, resume without suspend.\n"); 1808 sc->sc_suspend = why; 1809 return; 1810 } 1811 sc->sc_suspend = why; 1812 cs4280_init(sc, 0); 1813 cs4280_reset_codec(sc); 1814 1815 /* restore ac97 registers */ 1816 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1817 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1818 continue; 1819 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1820 } 1821 break; 1822 case PWR_SOFTSUSPEND: 1823 case PWR_SOFTSTANDBY: 1824 case PWR_SOFTRESUME: 1825 break; 1826 } 1827 } 1828 1829 void 1830 cs4280_clear_fifos(sc) 1831 struct cs4280_softc *sc; 1832 { 1833 int pd = 0, cnt, n; 1834 u_int32_t mem; 1835 1836 /* 1837 * If device power down, power up the device and keep power down 1838 * state. 1839 */ 1840 mem = BA0READ4(sc, CS4280_CLKCR1); 1841 if (!(mem & CLKCR1_SWCE)) { 1842 printf("cs4280_clear_fifo: power down found.\n"); 1843 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1844 pd = 1; 1845 } 1846 BA0WRITE4(sc, CS4280_SERBWP, 0); 1847 for (cnt = 0; cnt < 256; cnt++) { 1848 n = 0; 1849 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1850 delay(1000); 1851 if (++n > 1000) { 1852 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1853 break; 1854 } 1855 } 1856 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1857 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1858 } 1859 if (pd) 1860 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1861 } 1862 1863 #if NMIDI > 0 1864 int 1865 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1866 void *addr; 1867 int flags; 1868 void (*iintr)__P((void *, int)); 1869 void (*ointr)__P((void *)); 1870 void *arg; 1871 { 1872 struct cs4280_softc *sc = addr; 1873 u_int32_t mem; 1874 1875 DPRINTF(("midi_open\n")); 1876 sc->sc_iintr = iintr; 1877 sc->sc_ointr = ointr; 1878 sc->sc_arg = arg; 1879 1880 /* midi interrupt enable */ 1881 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1882 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1883 BA0WRITE4(sc, CS4280_MIDCR, mem); 1884 #ifdef CS4280_DEBUG 1885 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1886 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1887 return(EINVAL); 1888 } 1889 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1890 #endif 1891 return (0); 1892 } 1893 1894 void 1895 cs4280_midi_close(addr) 1896 void *addr; 1897 { 1898 struct cs4280_softc *sc = addr; 1899 u_int32_t mem; 1900 1901 DPRINTF(("midi_close\n")); 1902 mem = BA0READ4(sc, CS4280_MIDCR); 1903 mem &= ~MIDCR_MASK; 1904 BA0WRITE4(sc, CS4280_MIDCR, mem); 1905 1906 sc->sc_iintr = 0; 1907 sc->sc_ointr = 0; 1908 } 1909 1910 int 1911 cs4280_midi_output(addr, d) 1912 void *addr; 1913 int d; 1914 { 1915 struct cs4280_softc *sc = addr; 1916 u_int32_t mem; 1917 int x; 1918 1919 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1920 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1921 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1922 mem |= d & MIDWP_MASK; 1923 DPRINTFN(5,("midi_output d=0x%08x",d)); 1924 BA0WRITE4(sc, CS4280_MIDWP, mem); 1925 #ifdef DIAGNOSTIC 1926 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1927 DPRINTF(("Bad write data: %d %d", 1928 mem, BA0READ4(sc, CS4280_MIDWP))); 1929 return(EIO); 1930 } 1931 #endif 1932 return (0); 1933 } 1934 delay(MIDI_BUSY_DELAY); 1935 } 1936 return (EIO); 1937 } 1938 1939 void 1940 cs4280_midi_getinfo(addr, mi) 1941 void *addr; 1942 struct midi_info *mi; 1943 { 1944 mi->name = "CS4280 MIDI UART"; 1945 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1946 } 1947 1948 #endif 1949
Indexes created Thu Oct 02 14:10:14 GMT 2025