cs4280reg.h revision 1.1
1 /* $NetBSD: cs4280reg.h,v 1.1 1999/12/13 20:19:25 augustss Exp $ */ 2 /* $Tera: cs4280reg.h,v 1.2 1999/12/13 09:01:57 tacha Exp $ */ 3 4 /* 5 * Copyright (c) 1999 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 #define CS4280_BA0_SIZE 0x2000 36 #define CS4280_BA1_SIZE 0x40000 37 38 /* BA0 */ 39 40 /* Interrupt Reporting Registers */ 41 #define CS4280_HISR 0x000 /* Host Interrupt Status Register */ 42 #define HISR_INTENA 0x80000000 43 #define HISR_MIDI 0x00100000 44 #define HISR_CINT 0x00000002 45 #define HISR_PINT 0x00000001 46 #define CS4280_HICR 0x008 /* Host Interrupt Control Register */ 47 #define HICR_CHGM 0x00000002 48 #define HICR_IEV 0x00000001 49 50 /* Clock Control Registers */ 51 #define CS4280_CLKCR1 0x400 /* Clock Control Register 1 */ 52 #define CLKCR1_PLLSS_SPBC 0x00000000 53 #define CLKCR1_PLLSS_RSV 0x00000004 54 #define CLKCR1_PLLSS_PCI 0x00000008 55 #define CLKCR1_PLLSS_RSV2 0x0000000c 56 #define CLKCR1_PLLP 0x00000010 57 #define CLKCR1_SWCE 0x00000020 58 59 #define CS4280_CLKCR2 0x404 /* Clock Control Register 2 */ 60 #define CLKCR2_PDIVS_RSV 0x00000002 61 #define CLKCR2_PDIVS_8 0x00000008 62 #define CLKCR2_PDIVS_16 0x00000000 63 64 #define CS4280_PLLM 0x408 /* PLL Multiplier Register */ 65 #define PLLM_STATE 0x0000003a 66 67 #define CS4280_PLLCC 0x40c /* PLL Capacitor Coefficient Register */ 68 #define PLLCC_CDR_STATE 0x00000006 69 #define PLLCC_LPF_STATE 0x00000078 70 71 /* General Configuration Registers */ 72 #define CS4280_SERMC1 0x420 /* Serial Port Master Control Register 1 */ 73 #define SERMC1_MSPE 0x00000001 74 #define SERMC1_PTC_MASK 0x0000000e 75 #define SERMC1_PTC_CS423X 0x00000000 76 #define SERMC1_PTC_AC97 0x00000002 77 #define SERMC1_PLB_EN 0x00000010 78 #define SERMC1_XLB_EN 0x00000020 79 #define CS4280_SERC1 0x428 /* Serial Port Configuration Register 1 */ 80 #define SERC1_SO1EN 0x00000001 81 #define SERC1_SO1F_MASK 0x0000000e 82 #define SERC1_SO1F_CS423X 0x00000000 83 #define SERC1_SO1F_AC97 0x00000002 84 #define SERC1_SO1F_DAC 0x00000004 85 #define SERC1_SO1F_SPDIF 0x00000006 86 #define CS4280_SERC2 0x42c /* Serial Port Configuration Register 2 */ 87 #define SERC2_SI1EN 0x00000001 88 #define SERC2_SI1F_MASK 0x0000000e 89 #define SERC2_SI1F_CS423X 0x00000000 90 #define SERC2_SI1F_AC97 0x00000002 91 #define SERC2_SI1F_ADC 0x00000004 92 #define SERC2_SI1F_SPDIF 0x00000006 93 94 #define CS4280_SERBST 0x440 95 #define SERBST_RRDY 0x00000001 96 #define SERBST_WBSY 0x00000002 97 #define CS4280_SERBCM 0x444 98 #define SERBCM_RDC 0x000000001 99 #define SERBCM_WRC 0x000000002 100 #define CS4280_SERBAD 0x448 101 #define CS4280_SERBWP 0x450 102 /* AC97 Registers */ 103 #define CS4280_ACCTL 0x460 /* AC97 Control Register */ 104 #define ACCTL_RSTN 0x00000001 105 #define ACCTL_ESYN 0x00000002 106 #define ACCTL_VFRM 0x00000004 107 #define ACCTL_DCV 0x00000008 108 #define ACCTL_CRW 0x00000010 109 #define ACCTL_ASYN 0x00000020 110 #define ACCTL_TC 0x00000040 111 #define CS4280_ACSTS 0x464 /* AC97 Status Register */ 112 #define ACSTS_CRDY 0x00000001 113 #define ACSTS_VSTS 0x00000002 114 #define ACSTS_WKUP 0x00000004 115 #define CS4280_ACOSV 0x468 /* AC97 Output Slot Valid Register */ 116 #define ACOSV_SLV3 0x00000001 117 #define ACOSV_SLV4 0x00000002 118 #define ACOSV_SLV5 0x00000004 119 #define ACOSV_SLV6 0x00000008 120 #define ACOSV_SLV7 0x00000010 121 #define ACOSV_SLV8 0x00000020 122 #define ACOSV_SLV9 0x00000040 123 #define ACOSV_SLV10 0x00000080 124 #define ACOSV_SLV11 0x00000100 125 #define ACOSV_SLV12 0x00000200 126 127 #define CS4280_ACCAD 0x46c /* AC97 Command Address Register */ 128 #define CS4280_ACCDA 0x470 /* AC97 Command Data Register */ 129 #define CS4280_ACISV 0x474 /* AC97 Input Slot Valid Register */ 130 #define ACISV_ISV3 0x00000001 131 #define ACISV_ISV4 0x00000002 132 #define ACISV_ISV5 0x00000004 133 #define ACISV_ISV6 0x00000008 134 #define ACISV_ISV7 0x00000010 135 #define ACISV_ISV8 0x00000020 136 #define ACISV_ISV9 0x00000040 137 #define ACISV_ISV10 0x00000080 138 #define ACISV_ISV11 0x00000100 139 #define ACISV_ISV12 0x00000200 140 #define CS4280_ACSAD 0x478 /* AC97 Status Address Register */ 141 #define CS4280_ACSDA 0x47c /* AC97 Status Data Register */ 142 143 /* Host Access Methods */ 144 #define CS4280_GPIOR 0x4b8 /* General Purpose I/O Register */ 145 #define CS4280_EGPIODR 0x4bc /* Extended GPIO Direction Register */ 146 #define CS4280_EGPIOPTR 0x4c0 /* Extended GPIO Polarity/Type Register */ 147 #define CS4280_EGPIOTR 0x4c4 /* Extended GPIO Sticky Register */ 148 #define CS4280_EGPIOWR 0x4c8 /* Extended GPIO Wakeup Register */ 149 #define CS4280_EGPIOSR 0x4cc /* Extended GPIO Status Register */ 150 151 /* Control Register */ 152 #define CS4280_CFGI 0x4b0 /* Configuration Interface Register */ 153 154 #define CS4280_SERACC 0x4d8 155 #define SERACC_CTYPE_MASK 0x00000001 156 #define SERACC_CTYPE_1_03 0x00000000 157 #define SERACC_CTYPE_2_0 0x00000001 158 #define SERACC_TWO_CODECS 0x00000002 159 #define SERACC_MDM 0x00000004 160 #define SERACC_HSP 0x00000008 161 162 163 /* BA1 */ 164 165 /* Playback Parameters */ 166 #define CS4280_PDTC 0x00c0 /* Playback DMA Transaction Count */ 167 #define PDTC_MASK 0x000003ff 168 #define CS4280_MK_PDTC(x) ((x)/2 - 1) 169 #define CS4280_PFIE 0x00c4 /* Playback Format and Interrupt Enable */ 170 #define PFIE_UNSIGNED 0x00008000 /* Playback Format is unsigned */ 171 #define PFIE_SWAPPED 0x00004000 /* Playback Format is need swapped */ 172 #define PFIE_MONO 0x00002000 /* Playback Format is monoral */ 173 #define PFIE_8BIT 0x00001000 /* Playback Format is 8bit */ 174 #define PFIE_PI_ENABLE 0x00000000 /* Playback Interrupt Enabled */ 175 #define PFIE_PI_DISABLE 0x00000010 /* Playback Interrupt Disabled */ 176 #define PFIE_PI_MASK 0x0000003f 177 #define PFIE_MASK 0x0000f03f 178 #define CS4280_PBA 0x00c8 /* Playback Buffer Address */ 179 #define CS4280_PVOL 0x00f8 /* Playback Volume */ 180 #define CS4280_PSRC 0x0288 /* Playback Sample Rate Correction */ 181 #define PSRC_MASK 0xffff0000 182 #define CS4280_MK_PSRC(psrc, py) ((((psrc) << 16) & 0xffff0000) | ((py) & 0xffff)) 183 #define CS4280_PCTL 0x02a4 /* Playback Control */ 184 #define PCTL_MASK 0xffff0000 185 #define CS4280_PPI 0x02b4 /* Playback Phase Increment */ 186 187 /* Capture Parameters */ 188 #define CS4280_CCTL 0x0064 /* Capture Control */ 189 #define CCTL_MASK 0x0000ffff 190 #define CS4280_CDTC 0x0100 /* Capture DMA Transaction Count */ 191 #define CS4280_CIE 0x0104 /* Capture Interrupt Enable */ 192 #define CIE_CI_ENABLE 0x00000001 /* Capture Interrupt enabled */ 193 #define CIE_CI_DISABLE 0x00000011 /* Capture Interrupt disabled */ 194 #define CIE_CI_MASK 0x0000003f 195 #define CS4280_CBA 0x010c /* Capture Buffer Address */ 196 #define CS4280_CSRC 0x02c8 /* Capture Sample Rate Correction */ 197 #define CSRC_MASK 0xffff0000 198 #define CS4280_MK_CSRC(csrc, cy) ((((csrc) << 16) & 0xffff0000) | ((cy) & 0xffff)) 199 #define CS4280_CCI 0x02d8 /* Capture Coefficient Increment */ 200 #define CCI_MASK 0xffff0000 201 #define CS4280_CD 0x02e0 /* Capture Delay */ 202 #define CD_MASK 0xfffc000 203 #define CS4280_CPI 0x02f4 /* Capture Phase Incremnt */ 204 #define CS4280_CGL 0x0134 /* Capture Group Length */ 205 #define CGL_MASK 0x0000ffff 206 #define CS4280_CNT 0x0340 /* Capture Number of Triplets */ 207 #define CS4280_CGC 0x0138 /* Capture Group Count */ 208 #define CGC_MASK 0x0000ffff 209 #define CS4280_CVOL 0x02f8 /* Capture Volume */ 210 211 #define CS4280_MIDCR 0x0490 /* MIDI Control Register */ 212 #define MIDCR_TXE 0x00000001 /* MIDI Transmit Enable */ 213 #define MIDCR_RXE 0x00000002 /* MIDI Receive Enable */ 214 #define MIDCR_RIE 0x00000004 /* MIDI Receive Interrupt Enable */ 215 #define MIDCR_TIE 0x00000008 /* MIDI Transmit Interrupt Enable */ 216 #define MIDCR_MLB 0x00000010 /* MIDI Loop Back Enable */ 217 #define MIDCR_MRST 0x00000020 /* MIDI Reset */ 218 #define MIDCR_MASK 0x0000003f 219 #define CS4280_MIDSR 0x0494 /* Host MIDI Status Register */ 220 #define MIDSR_TBF 0x00000001 /* Transmit Buffer Full */ 221 #define MIDSR_RBE 0x00000002 /* Receive Buffer Empty */ 222 #define CS4280_MIDWP 0x0498 /* MIDI Write Port */ 223 #define MIDWP_MASK 0x000000ff 224 #define CS4280_MIDRP 0x049c /* MIDI Read Port */ 225 226 #define CS4280_JSPT 0x0480 /* Joystick Poll/Trigger Register */ 227 #define CS4280_JSCTL 0x0484 /* Joystick Control Register */ 228 #define CS4280_JSC1 0x0488 /* Joystick Coordinate Register 1 */ 229 #define CS4280_JSC2 0x048c /* Joystick Coordinate Register 2 */ 230 231 /* Processor Registers */ 232 #define CS4280_SPCR 0x30000 /* Processor Control Register */ 233 #define SPCR_RUN 0x00000001 234 #define SPCR_STPFR 0x00000002 235 #define SPCR_RUNFR 0x00000004 236 #define SPCR_DRQEN 0x00000020 237 #define SPCR_RSTSP 0x00000040 238 #define CS4280_DREG 0x30004 239 #define CS4280_DSRWP 0x30008 240 #define CS4280_TWPR 0x3000c /* Trap Write Port Register */ 241 #define CS4280_SPWR 0x30010 242 #define CS4280_SPCS 0x30028 /* Processor Clock Status Register */ 243 #define SPCS_SPRUN 0x00000100 244 #define CS4280_FRMT 0x30030 /* Frame Timer Register */ 245 #define FRMT_FTV 0x00000adf 246 247 248 #define CF_MONO 0x01 249 #define CF_8BIT 0x02 250 251 #define CF_16BIT_STEREO 0x00 252 #define CF_16BIT_MONO 0x01 253 #define CF_8BIT_STEREO 0x02 254 #define CF_8BIT_MONO 0x03 255 256 #define MIDI_BUSY_WAIT 100 257 #define MIDI_BUSY_DELAY 100 /* Delay when UART is busy */ 258 259 /* 3*1024 parameter, 3.5*1024 sample, 2*3.5*1024 code */ 260 #define BA1_DWORD_SIZE (13 * 1024 + 512) 261 #define BA1_MEMORY_COUNT 3 262 263 struct BA1struct { 264 struct { 265 u_int32_t offset; 266 u_int32_t size; 267 } memory[BA1_MEMORY_COUNT]; 268 u_int32_t map[BA1_DWORD_SIZE]; 269 }; 270 271 #define CS4280_ICHUNK 2048 /* Bytes between interrupts */ 272 #define CS4280_DCHUNK 4096 /* Bytes of DMA memory */ 273 #define CS4280_DALIGN 4096 /* Alignment of DMA memory */ 274 275 /* AC97 Registers */ 276 #define CS4280_SAVE_REG_MAX 0x10 277 278 /* AC97 Registers: stolen from /sys/dev/ic/ac97.c */ 279 #define AC97_REG_RESET 0x00 280 #define AC97_REG_MASTER_VOLUME 0x02 281 #define AC97_REG_HEADPHONE_VOLUME 0x04 282 #define AC97_REG_MASTER_VOLUME_MONO 0x06 283 #define AC97_REG_MASTER_TONE 0x08 284 #define AC97_REG_PCBEEP_VOLUME 0x0a 285 #define AC97_REG_PHONE_VOLUME 0x0c 286 #define AC97_REG_MIC_VOLUME 0x0e 287 #define AC97_REG_LINEIN_VOLUME 0x10 288 #define AC97_REG_CD_VOLUME 0x12 289 #define AC97_REG_VIDEO_VOLUME 0x14 290 #define AC97_REG_AUX_VOLUME 0x16 291 #define AC97_REG_PCMOUT_VOLUME 0x18 292 #define AC97_REG_RECORD_SELECT 0x1a 293 #define AC97_REG_RECORD_GAIN 0x1c 294 #define AC97_REG_RECORD_GAIN_MIC 0x1e 295 #define AC97_REG_GP 0x20 296 #define AC97_REG_3D_CONTROL 0x22 297 #define AC97_REG_POWER 0x26 298 #define CS4280_POWER_DOWN_ALL 0x7f0f 299 #define AC97_REG_VENDOR_ID1 0x7c 300 #define AC97_REG_VENDOR_ID2 0x7e 301
Indexes created Wed Oct 15 16:09:53 GMT 2025