cs4281.c revision 1.3.2.3
1 1.3.2.3 bouyer /* $NetBSD: cs4281.c,v 1.3.2.3 2001/04/21 17:49:11 bouyer Exp $ */ 2 1.3.2.2 bouyer 3 1.3.2.2 bouyer /* 4 1.3.2.2 bouyer * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 1.3.2.2 bouyer * 6 1.3.2.2 bouyer * Redistribution and use in source and binary forms, with or without 7 1.3.2.2 bouyer * modification, are permitted provided that the following conditions 8 1.3.2.2 bouyer * are met: 9 1.3.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 10 1.3.2.2 bouyer * notice, this list of conditions and the following disclaimer. 11 1.3.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 12 1.3.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 13 1.3.2.2 bouyer * documentation and/or other materials provided with the distribution. 14 1.3.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 15 1.3.2.2 bouyer * must display the following acknowledgement: 16 1.3.2.2 bouyer * This product includes software developed by Tatoku Ogaito 17 1.3.2.2 bouyer * for the NetBSD Project. 18 1.3.2.2 bouyer * 4. The name of the author may not be used to endorse or promote products 19 1.3.2.2 bouyer * derived from this software without specific prior written permission 20 1.3.2.2 bouyer * 21 1.3.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 1.3.2.2 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 1.3.2.2 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 1.3.2.2 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 1.3.2.2 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 1.3.2.2 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 1.3.2.2 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.3.2.2 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 1.3.2.2 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 1.3.2.2 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1.3.2.2 bouyer */ 32 1.3.2.2 bouyer 33 1.3.2.2 bouyer /* 34 1.3.2.2 bouyer * Cirrus Logic CS4281 driver. 35 1.3.2.2 bouyer * Data sheets can be found 36 1.3.2.2 bouyer * http://www.cirrus.com/ftp/pub/4281.pdf 37 1.3.2.2 bouyer * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 1.3.2.2 bouyer * 39 1.3.2.2 bouyer * TODO: 40 1.3.2.2 bouyer * 1: midi and FM support 41 1.3.2.2 bouyer * 2: ... 42 1.3.2.2 bouyer * 43 1.3.2.2 bouyer */ 44 1.3.2.2 bouyer 45 1.3.2.2 bouyer #include <sys/param.h> 46 1.3.2.2 bouyer #include <sys/systm.h> 47 1.3.2.2 bouyer #include <sys/kernel.h> 48 1.3.2.2 bouyer #include <sys/malloc.h> 49 1.3.2.2 bouyer #include <sys/fcntl.h> 50 1.3.2.2 bouyer #include <sys/device.h> 51 1.3.2.2 bouyer #include <sys/types.h> 52 1.3.2.2 bouyer #include <sys/systm.h> 53 1.3.2.2 bouyer 54 1.3.2.2 bouyer #include <dev/pci/pcidevs.h> 55 1.3.2.2 bouyer #include <dev/pci/pcivar.h> 56 1.3.2.2 bouyer #include <dev/pci/cs4281reg.h> 57 1.3.2.2 bouyer #include <dev/pci/cs428xreg.h> 58 1.3.2.2 bouyer 59 1.3.2.2 bouyer #include <sys/audioio.h> 60 1.3.2.2 bouyer #include <dev/audio_if.h> 61 1.3.2.2 bouyer #include <dev/midi_if.h> 62 1.3.2.2 bouyer #include <dev/mulaw.h> 63 1.3.2.2 bouyer #include <dev/auconv.h> 64 1.3.2.2 bouyer 65 1.3.2.2 bouyer #include <dev/ic/ac97reg.h> 66 1.3.2.2 bouyer #include <dev/ic/ac97var.h> 67 1.3.2.2 bouyer 68 1.3.2.2 bouyer #include <dev/pci/cs428x.h> 69 1.3.2.2 bouyer 70 1.3.2.2 bouyer #include <machine/bus.h> 71 1.3.2.2 bouyer 72 1.3.2.2 bouyer #if defined(ENABLE_SECONDARY_CODEC) 73 1.3.2.2 bouyer #define MAX_CHANNELS (4) 74 1.3.2.2 bouyer #define MAX_FIFO_SIZE 32 /* 128/4channels */ 75 1.3.2.2 bouyer #else 76 1.3.2.2 bouyer #define MAX_CHANNELS (2) 77 1.3.2.2 bouyer #define MAX_FIFO_SIZE 64 /* 128/2channels */ 78 1.3.2.2 bouyer #endif 79 1.3.2.2 bouyer 80 1.3.2.2 bouyer /* IF functions for audio driver */ 81 1.3.2.2 bouyer int cs4281_match(struct device *, struct cfdata *, void *); 82 1.3.2.2 bouyer void cs4281_attach(struct device *, struct device *, void *); 83 1.3.2.2 bouyer int cs4281_intr(void *); 84 1.3.2.2 bouyer int cs4281_query_encoding(void *, struct audio_encoding *); 85 1.3.2.2 bouyer int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 86 1.3.2.2 bouyer int cs4281_halt_output(void *); 87 1.3.2.2 bouyer int cs4281_halt_input(void *); 88 1.3.2.2 bouyer int cs4281_getdev(void *, struct audio_device *); 89 1.3.2.2 bouyer int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 90 1.3.2.2 bouyer void *, struct audio_params *); 91 1.3.2.2 bouyer int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 92 1.3.2.2 bouyer void *, struct audio_params *); 93 1.3.2.2 bouyer 94 1.3.2.2 bouyer void cs4281_reset_codec(void *); 95 1.3.2.2 bouyer 96 1.3.2.2 bouyer /* Internal functions */ 97 1.3.2.2 bouyer u_int8_t cs4281_sr2regval(int); 98 1.3.2.3 bouyer void cs4281_set_dac_rate(struct cs428x_softc *, int); 99 1.3.2.3 bouyer void cs4281_set_adc_rate(struct cs428x_softc *, int); 100 1.3.2.3 bouyer int cs4281_init(struct cs428x_softc *, int); 101 1.3.2.2 bouyer 102 1.3.2.2 bouyer /* Power Management */ 103 1.3.2.2 bouyer void cs4281_power(int, void *); 104 1.3.2.2 bouyer 105 1.3.2.2 bouyer struct audio_hw_if cs4281_hw_if = { 106 1.3.2.2 bouyer cs428x_open, 107 1.3.2.2 bouyer cs428x_close, 108 1.3.2.2 bouyer NULL, 109 1.3.2.2 bouyer cs4281_query_encoding, 110 1.3.2.2 bouyer cs4281_set_params, 111 1.3.2.2 bouyer cs428x_round_blocksize, 112 1.3.2.2 bouyer NULL, 113 1.3.2.2 bouyer NULL, 114 1.3.2.2 bouyer NULL, 115 1.3.2.2 bouyer NULL, 116 1.3.2.2 bouyer NULL, 117 1.3.2.2 bouyer cs4281_halt_output, 118 1.3.2.2 bouyer cs4281_halt_input, 119 1.3.2.2 bouyer NULL, 120 1.3.2.2 bouyer cs4281_getdev, 121 1.3.2.2 bouyer NULL, 122 1.3.2.2 bouyer cs428x_mixer_set_port, 123 1.3.2.2 bouyer cs428x_mixer_get_port, 124 1.3.2.2 bouyer cs428x_query_devinfo, 125 1.3.2.2 bouyer cs428x_malloc, 126 1.3.2.2 bouyer cs428x_free, 127 1.3.2.2 bouyer cs428x_round_buffersize, 128 1.3.2.2 bouyer cs428x_mappage, 129 1.3.2.2 bouyer cs428x_get_props, 130 1.3.2.2 bouyer cs4281_trigger_output, 131 1.3.2.2 bouyer cs4281_trigger_input, 132 1.3.2.2 bouyer }; 133 1.3.2.2 bouyer 134 1.3.2.2 bouyer #if NMIDI > 0 && 0 135 1.3.2.2 bouyer /* Midi Interface */ 136 1.3.2.2 bouyer void cs4281_midi_close(void*); 137 1.3.2.2 bouyer void cs4281_midi_getinfo(void *, struct midi_info *); 138 1.3.2.2 bouyer int cs4281_midi_open(void *, int, void (*)(void *, int), 139 1.3.2.2 bouyer void (*)(void *), void *); 140 1.3.2.2 bouyer int cs4281_midi_output(void *, int); 141 1.3.2.2 bouyer 142 1.3.2.2 bouyer struct midi_hw_if cs4281_midi_hw_if = { 143 1.3.2.2 bouyer cs4281_midi_open, 144 1.3.2.2 bouyer cs4281_midi_close, 145 1.3.2.2 bouyer cs4281_midi_output, 146 1.3.2.2 bouyer cs4281_midi_getinfo, 147 1.3.2.2 bouyer 0, 148 1.3.2.2 bouyer }; 149 1.3.2.2 bouyer #endif 150 1.3.2.2 bouyer 151 1.3.2.2 bouyer struct cfattach clct_ca = { 152 1.3.2.2 bouyer sizeof(struct cs428x_softc), cs4281_match, cs4281_attach 153 1.3.2.2 bouyer }; 154 1.3.2.2 bouyer 155 1.3.2.2 bouyer struct audio_device cs4281_device = { 156 1.3.2.2 bouyer "CS4281", 157 1.3.2.2 bouyer "", 158 1.3.2.2 bouyer "cs4281" 159 1.3.2.2 bouyer }; 160 1.3.2.2 bouyer 161 1.3.2.2 bouyer 162 1.3.2.2 bouyer int 163 1.3.2.2 bouyer cs4281_match(parent, match, aux) 164 1.3.2.2 bouyer struct device *parent; 165 1.3.2.2 bouyer struct cfdata *match; 166 1.3.2.2 bouyer void *aux; 167 1.3.2.2 bouyer { 168 1.3.2.2 bouyer struct pci_attach_args *pa = (struct pci_attach_args *)aux; 169 1.3.2.2 bouyer 170 1.3.2.2 bouyer if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 171 1.3.2.2 bouyer return 0; 172 1.3.2.2 bouyer if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 173 1.3.2.2 bouyer return 1; 174 1.3.2.2 bouyer return 0; 175 1.3.2.2 bouyer } 176 1.3.2.2 bouyer 177 1.3.2.2 bouyer void 178 1.3.2.2 bouyer cs4281_attach(parent, self, aux) 179 1.3.2.2 bouyer struct device *parent; 180 1.3.2.2 bouyer struct device *self; 181 1.3.2.2 bouyer void *aux; 182 1.3.2.2 bouyer { 183 1.3.2.2 bouyer struct cs428x_softc *sc = (struct cs428x_softc *)self; 184 1.3.2.2 bouyer struct pci_attach_args *pa = (struct pci_attach_args *)aux; 185 1.3.2.2 bouyer pci_chipset_tag_t pc = pa->pa_pc; 186 1.3.2.2 bouyer char const *intrstr; 187 1.3.2.2 bouyer pci_intr_handle_t ih; 188 1.3.2.2 bouyer pcireg_t reg; 189 1.3.2.2 bouyer char devinfo[256]; 190 1.3.2.2 bouyer int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 191 1.3.2.2 bouyer 192 1.3.2.2 bouyer pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 193 1.3.2.2 bouyer printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 194 1.3.2.2 bouyer 195 1.3.2.2 bouyer /* Map I/O register */ 196 1.3.2.2 bouyer if (pci_mapreg_map(pa, PCI_BA0, 197 1.3.2.2 bouyer PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 198 1.3.2.2 bouyer &sc->ba0t, &sc->ba0h, NULL, NULL)) { 199 1.3.2.2 bouyer printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 200 1.3.2.2 bouyer return; 201 1.3.2.2 bouyer } 202 1.3.2.2 bouyer if (pci_mapreg_map(pa, PCI_BA1, 203 1.3.2.2 bouyer PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 204 1.3.2.2 bouyer &sc->ba1t, &sc->ba1h, NULL, NULL)) { 205 1.3.2.2 bouyer printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 206 1.3.2.2 bouyer return; 207 1.3.2.2 bouyer } 208 1.3.2.2 bouyer 209 1.3.2.2 bouyer sc->sc_dmatag = pa->pa_dmat; 210 1.3.2.2 bouyer 211 1.3.2.2 bouyer /* 212 1.3.2.2 bouyer * Set Power State D0. 213 1.3.2.2 bouyer * Without do this, 0xffffffff is read from all registers after 214 1.3.2.2 bouyer * using Windows. 215 1.3.2.2 bouyer * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 216 1.3.2.2 bouyer */ 217 1.3.2.2 bouyer if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 218 1.3.2.2 bouyer &pci_pwrmgmt_cap_reg, 0)) { 219 1.3.2.2 bouyer 220 1.3.2.2 bouyer pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 221 1.3.2.2 bouyer reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 222 1.3.2.2 bouyer pci_pwrmgmt_csr_reg); 223 1.3.2.2 bouyer if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 224 1.3.2.2 bouyer pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 225 1.3.2.2 bouyer (reg & ~PCI_PMCSR_STATE_MASK) | 226 1.3.2.2 bouyer PCI_PMCSR_STATE_D0); 227 1.3.2.2 bouyer } 228 1.3.2.2 bouyer } 229 1.3.2.2 bouyer 230 1.3.2.2 bouyer /* Enable the device (set bus master flag) */ 231 1.3.2.2 bouyer reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 232 1.3.2.2 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 233 1.3.2.2 bouyer reg | PCI_COMMAND_MASTER_ENABLE); 234 1.3.2.2 bouyer 235 1.3.2.2 bouyer #if 0 236 1.3.2.2 bouyer /* LATENCY_TIMER setting */ 237 1.3.2.2 bouyer temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 238 1.3.2.2 bouyer if ( PCI_LATTIMER(temp1) < 32 ) { 239 1.3.2.2 bouyer temp1 &= 0xffff00ff; 240 1.3.2.2 bouyer temp1 |= 0x00002000; 241 1.3.2.2 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 242 1.3.2.2 bouyer } 243 1.3.2.2 bouyer #endif 244 1.3.2.2 bouyer 245 1.3.2.2 bouyer /* Map and establish the interrupt. */ 246 1.3.2.2 bouyer if (pci_intr_map(pa, &ih)) { 247 1.3.2.2 bouyer printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 248 1.3.2.2 bouyer return; 249 1.3.2.2 bouyer } 250 1.3.2.2 bouyer intrstr = pci_intr_string(pc, ih); 251 1.3.2.2 bouyer 252 1.3.2.2 bouyer sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 253 1.3.2.2 bouyer if (sc->sc_ih == NULL) { 254 1.3.2.2 bouyer printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 255 1.3.2.2 bouyer if (intrstr != NULL) 256 1.3.2.2 bouyer printf(" at %s", intrstr); 257 1.3.2.2 bouyer printf("\n"); 258 1.3.2.2 bouyer return; 259 1.3.2.2 bouyer } 260 1.3.2.2 bouyer printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 261 1.3.2.2 bouyer 262 1.3.2.2 bouyer /* 263 1.3.2.2 bouyer * Sound System start-up 264 1.3.2.2 bouyer */ 265 1.3.2.3 bouyer if (cs4281_init(sc,1) != 0) 266 1.3.2.2 bouyer return; 267 1.3.2.2 bouyer 268 1.3.2.2 bouyer sc->type = TYPE_CS4281; 269 1.3.2.2 bouyer sc->halt_input = cs4281_halt_input; 270 1.3.2.2 bouyer sc->halt_output = cs4281_halt_output; 271 1.3.2.2 bouyer 272 1.3.2.2 bouyer sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 273 1.3.2.2 bouyer sc->dma_align = 0x10; 274 1.3.2.2 bouyer sc->hw_blocksize = sc->dma_size / 2; 275 1.3.2.2 bouyer 276 1.3.2.2 bouyer /* AC 97 attachment */ 277 1.3.2.2 bouyer sc->host_if.arg = sc; 278 1.3.2.2 bouyer sc->host_if.attach = cs428x_attach_codec; 279 1.3.2.2 bouyer sc->host_if.read = cs428x_read_codec; 280 1.3.2.2 bouyer sc->host_if.write = cs428x_write_codec; 281 1.3.2.2 bouyer sc->host_if.reset = cs4281_reset_codec; 282 1.3.2.2 bouyer if (ac97_attach(&sc->host_if) != 0) { 283 1.3.2.2 bouyer printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 284 1.3.2.2 bouyer return; 285 1.3.2.2 bouyer } 286 1.3.2.2 bouyer audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 287 1.3.2.2 bouyer 288 1.3.2.2 bouyer #if NMIDI > 0 && 0 289 1.3.2.2 bouyer midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 290 1.3.2.2 bouyer #endif 291 1.3.2.2 bouyer 292 1.3.2.2 bouyer sc->sc_suspend = PWR_RESUME; 293 1.3.2.2 bouyer sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 294 1.3.2.2 bouyer } 295 1.3.2.2 bouyer 296 1.3.2.2 bouyer int 297 1.3.2.2 bouyer cs4281_intr(p) 298 1.3.2.2 bouyer void *p; 299 1.3.2.2 bouyer { 300 1.3.2.2 bouyer struct cs428x_softc *sc = p; 301 1.3.2.2 bouyer u_int32_t intr, hdsr0, hdsr1; 302 1.3.2.2 bouyer char *empty_dma; 303 1.3.2.2 bouyer int handled = 0; 304 1.3.2.2 bouyer 305 1.3.2.2 bouyer hdsr0 = 0; 306 1.3.2.2 bouyer hdsr1 = 0; 307 1.3.2.2 bouyer 308 1.3.2.2 bouyer /* grab interrupt register */ 309 1.3.2.2 bouyer intr = BA0READ4(sc, CS4281_HISR); 310 1.3.2.2 bouyer 311 1.3.2.2 bouyer DPRINTF(("cs4281_intr:")); 312 1.3.2.2 bouyer /* not for me */ 313 1.3.2.2 bouyer if ((intr & HISR_INTENA) == 0) { 314 1.3.2.2 bouyer /* clear the interrupt register */ 315 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 316 1.3.2.2 bouyer return 0; 317 1.3.2.2 bouyer } 318 1.3.2.2 bouyer 319 1.3.2.2 bouyer if (intr & HISR_DMA0) 320 1.3.2.2 bouyer hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 321 1.3.2.2 bouyer if (intr & HISR_DMA1) 322 1.3.2.2 bouyer hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 323 1.3.2.2 bouyer /* clear the interrupt register */ 324 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 325 1.3.2.2 bouyer 326 1.3.2.2 bouyer DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 327 1.3.2.2 bouyer intr, hdsr0, hdsr1)); 328 1.3.2.2 bouyer 329 1.3.2.2 bouyer /* Playback Interrupt */ 330 1.3.2.2 bouyer if (intr & HISR_DMA0) { 331 1.3.2.2 bouyer handled = 1; 332 1.3.2.2 bouyer DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 333 1.3.2.2 bouyer (int)BA0READ4(sc, CS4281_DCC0))); 334 1.3.2.2 bouyer if (sc->sc_pintr) { 335 1.3.2.2 bouyer if ((sc->sc_pi%sc->sc_pcount) == 0) 336 1.3.2.2 bouyer sc->sc_pintr(sc->sc_parg); 337 1.3.2.2 bouyer } else { 338 1.3.2.2 bouyer printf("unexpected play intr\n"); 339 1.3.2.2 bouyer } 340 1.3.2.2 bouyer /* copy buffer */ 341 1.3.2.2 bouyer ++sc->sc_pi; 342 1.3.2.2 bouyer empty_dma = sc->sc_pdma->addr; 343 1.3.2.2 bouyer if (sc->sc_pi&1) 344 1.3.2.2 bouyer empty_dma += sc->hw_blocksize; 345 1.3.2.2 bouyer memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 346 1.3.2.2 bouyer sc->sc_pn += sc->hw_blocksize; 347 1.3.2.2 bouyer if (sc->sc_pn >= sc->sc_pe) 348 1.3.2.2 bouyer sc->sc_pn = sc->sc_ps; 349 1.3.2.2 bouyer } 350 1.3.2.2 bouyer if (intr & HISR_DMA1) { 351 1.3.2.2 bouyer handled = 1; 352 1.3.2.2 bouyer /* copy from dma */ 353 1.3.2.2 bouyer DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 354 1.3.2.2 bouyer (int)BA0READ4(sc, CS4281_DCC1))); 355 1.3.2.2 bouyer ++sc->sc_ri; 356 1.3.2.2 bouyer empty_dma = sc->sc_rdma->addr; 357 1.3.2.2 bouyer if ((sc->sc_ri & 1) == 0) 358 1.3.2.2 bouyer empty_dma += sc->hw_blocksize; 359 1.3.2.2 bouyer memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 360 1.3.2.2 bouyer if (sc->sc_rn >= sc->sc_re) 361 1.3.2.2 bouyer sc->sc_rn = sc->sc_rs; 362 1.3.2.2 bouyer if (sc->sc_rintr) { 363 1.3.2.2 bouyer if ((sc->sc_ri % sc->sc_rcount) == 0) 364 1.3.2.2 bouyer sc->sc_rintr(sc->sc_rarg); 365 1.3.2.2 bouyer } else { 366 1.3.2.2 bouyer printf("unexpected record intr\n"); 367 1.3.2.2 bouyer } 368 1.3.2.2 bouyer } 369 1.3.2.2 bouyer DPRINTF(("\n")); 370 1.3.2.2 bouyer 371 1.3.2.2 bouyer return handled; 372 1.3.2.2 bouyer } 373 1.3.2.2 bouyer 374 1.3.2.2 bouyer int 375 1.3.2.2 bouyer cs4281_query_encoding(addr, fp) 376 1.3.2.2 bouyer void *addr; 377 1.3.2.2 bouyer struct audio_encoding *fp; 378 1.3.2.2 bouyer { 379 1.3.2.2 bouyer switch (fp->index) { 380 1.3.2.2 bouyer case 0: 381 1.3.2.2 bouyer strcpy(fp->name, AudioEulinear); 382 1.3.2.2 bouyer fp->encoding = AUDIO_ENCODING_ULINEAR; 383 1.3.2.2 bouyer fp->precision = 8; 384 1.3.2.2 bouyer fp->flags = 0; 385 1.3.2.2 bouyer break; 386 1.3.2.2 bouyer case 1: 387 1.3.2.2 bouyer strcpy(fp->name, AudioEmulaw); 388 1.3.2.2 bouyer fp->encoding = AUDIO_ENCODING_ULAW; 389 1.3.2.2 bouyer fp->precision = 8; 390 1.3.2.2 bouyer fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 391 1.3.2.2 bouyer break; 392 1.3.2.2 bouyer case 2: 393 1.3.2.2 bouyer strcpy(fp->name, AudioEalaw); 394 1.3.2.2 bouyer fp->encoding = AUDIO_ENCODING_ALAW; 395 1.3.2.2 bouyer fp->precision = 8; 396 1.3.2.2 bouyer fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 397 1.3.2.2 bouyer break; 398 1.3.2.2 bouyer case 3: 399 1.3.2.2 bouyer strcpy(fp->name, AudioEslinear); 400 1.3.2.2 bouyer fp->encoding = AUDIO_ENCODING_SLINEAR; 401 1.3.2.2 bouyer fp->precision = 8; 402 1.3.2.2 bouyer fp->flags = 0; 403 1.3.2.2 bouyer break; 404 1.3.2.2 bouyer case 4: 405 1.3.2.2 bouyer strcpy(fp->name, AudioEslinear_le); 406 1.3.2.2 bouyer fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 407 1.3.2.2 bouyer fp->precision = 16; 408 1.3.2.2 bouyer fp->flags = 0; 409 1.3.2.2 bouyer break; 410 1.3.2.2 bouyer case 5: 411 1.3.2.2 bouyer strcpy(fp->name, AudioEulinear_le); 412 1.3.2.2 bouyer fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 413 1.3.2.2 bouyer fp->precision = 16; 414 1.3.2.2 bouyer fp->flags = 0; 415 1.3.2.2 bouyer break; 416 1.3.2.2 bouyer case 6: 417 1.3.2.2 bouyer strcpy(fp->name, AudioEslinear_be); 418 1.3.2.2 bouyer fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 419 1.3.2.2 bouyer fp->precision = 16; 420 1.3.2.2 bouyer fp->flags = 0; 421 1.3.2.2 bouyer break; 422 1.3.2.2 bouyer case 7: 423 1.3.2.2 bouyer strcpy(fp->name, AudioEulinear_be); 424 1.3.2.2 bouyer fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 425 1.3.2.2 bouyer fp->precision = 16; 426 1.3.2.2 bouyer fp->flags = 0; 427 1.3.2.2 bouyer break; 428 1.3.2.2 bouyer default: 429 1.3.2.2 bouyer return EINVAL; 430 1.3.2.2 bouyer } 431 1.3.2.2 bouyer return 0; 432 1.3.2.2 bouyer } 433 1.3.2.2 bouyer 434 1.3.2.2 bouyer int 435 1.3.2.2 bouyer cs4281_set_params(addr, setmode, usemode, play, rec) 436 1.3.2.2 bouyer void *addr; 437 1.3.2.2 bouyer int setmode, usemode; 438 1.3.2.2 bouyer struct audio_params *play, *rec; 439 1.3.2.2 bouyer { 440 1.3.2.2 bouyer struct cs428x_softc *sc = addr; 441 1.3.2.2 bouyer struct audio_params *p; 442 1.3.2.2 bouyer int mode; 443 1.3.2.2 bouyer 444 1.3.2.2 bouyer for (mode = AUMODE_RECORD; mode != -1; 445 1.3.2.2 bouyer mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 446 1.3.2.2 bouyer if ((setmode & mode) == 0) 447 1.3.2.2 bouyer continue; 448 1.3.2.2 bouyer 449 1.3.2.2 bouyer p = mode == AUMODE_PLAY ? play : rec; 450 1.3.2.2 bouyer 451 1.3.2.2 bouyer if (p == play) { 452 1.3.2.2 bouyer DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 453 1.3.2.2 bouyer p->sample_rate, p->precision, p->channels)); 454 1.3.2.2 bouyer if (p->sample_rate < 6023 || p->sample_rate > 48000 || 455 1.3.2.2 bouyer (p->precision != 8 && p->precision != 16) || 456 1.3.2.2 bouyer (p->channels != 1 && p->channels != 2)) { 457 1.3.2.2 bouyer return (EINVAL); 458 1.3.2.2 bouyer } 459 1.3.2.2 bouyer } else { 460 1.3.2.2 bouyer DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 461 1.3.2.2 bouyer p->sample_rate, p->precision, p->channels)); 462 1.3.2.2 bouyer if (p->sample_rate < 6023 || p->sample_rate > 48000 || 463 1.3.2.2 bouyer (p->precision != 8 && p->precision != 16) || 464 1.3.2.2 bouyer (p->channels != 1 && p->channels != 2)) { 465 1.3.2.2 bouyer return (EINVAL); 466 1.3.2.2 bouyer } 467 1.3.2.2 bouyer } 468 1.3.2.2 bouyer p->factor = 1; 469 1.3.2.2 bouyer p->sw_code = 0; 470 1.3.2.2 bouyer 471 1.3.2.2 bouyer switch (p->encoding) { 472 1.3.2.2 bouyer case AUDIO_ENCODING_SLINEAR_BE: 473 1.3.2.2 bouyer break; 474 1.3.2.2 bouyer case AUDIO_ENCODING_SLINEAR_LE: 475 1.3.2.2 bouyer break; 476 1.3.2.2 bouyer case AUDIO_ENCODING_ULINEAR_BE: 477 1.3.2.2 bouyer break; 478 1.3.2.2 bouyer case AUDIO_ENCODING_ULINEAR_LE: 479 1.3.2.2 bouyer break; 480 1.3.2.2 bouyer case AUDIO_ENCODING_ULAW: 481 1.3.2.2 bouyer if (mode == AUMODE_PLAY) { 482 1.3.2.2 bouyer p->sw_code = mulaw_to_slinear8; 483 1.3.2.2 bouyer } else { 484 1.3.2.2 bouyer p->sw_code = slinear8_to_mulaw; 485 1.3.2.2 bouyer } 486 1.3.2.2 bouyer break; 487 1.3.2.2 bouyer case AUDIO_ENCODING_ALAW: 488 1.3.2.2 bouyer if (mode == AUMODE_PLAY) { 489 1.3.2.2 bouyer p->sw_code = alaw_to_slinear8; 490 1.3.2.2 bouyer } else { 491 1.3.2.2 bouyer p->sw_code = slinear8_to_alaw; 492 1.3.2.2 bouyer } 493 1.3.2.2 bouyer break; 494 1.3.2.2 bouyer default: 495 1.3.2.2 bouyer return (EINVAL); 496 1.3.2.2 bouyer } 497 1.3.2.2 bouyer } 498 1.3.2.2 bouyer 499 1.3.2.2 bouyer /* set sample rate */ 500 1.3.2.2 bouyer cs4281_set_dac_rate(sc, play->sample_rate); 501 1.3.2.2 bouyer cs4281_set_adc_rate(sc, rec->sample_rate); 502 1.3.2.2 bouyer return 0; 503 1.3.2.2 bouyer } 504 1.3.2.2 bouyer 505 1.3.2.2 bouyer int 506 1.3.2.2 bouyer cs4281_halt_output(addr) 507 1.3.2.2 bouyer void *addr; 508 1.3.2.2 bouyer { 509 1.3.2.2 bouyer struct cs428x_softc *sc = addr; 510 1.3.2.2 bouyer 511 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 512 1.3.2.2 bouyer sc->sc_prun = 0; 513 1.3.2.2 bouyer return 0; 514 1.3.2.2 bouyer } 515 1.3.2.2 bouyer 516 1.3.2.2 bouyer int 517 1.3.2.2 bouyer cs4281_halt_input(addr) 518 1.3.2.2 bouyer void *addr; 519 1.3.2.2 bouyer { 520 1.3.2.2 bouyer struct cs428x_softc *sc = addr; 521 1.3.2.2 bouyer 522 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 523 1.3.2.2 bouyer sc->sc_rrun = 0; 524 1.3.2.2 bouyer return 0; 525 1.3.2.2 bouyer } 526 1.3.2.2 bouyer 527 1.3.2.2 bouyer int 528 1.3.2.2 bouyer cs4281_getdev(addr, retp) 529 1.3.2.2 bouyer void *addr; 530 1.3.2.2 bouyer struct audio_device *retp; 531 1.3.2.2 bouyer { 532 1.3.2.2 bouyer *retp = cs4281_device; 533 1.3.2.2 bouyer return 0; 534 1.3.2.2 bouyer } 535 1.3.2.2 bouyer 536 1.3.2.2 bouyer int 537 1.3.2.2 bouyer cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 538 1.3.2.2 bouyer void *addr; 539 1.3.2.2 bouyer void *start, *end; 540 1.3.2.2 bouyer int blksize; 541 1.3.2.2 bouyer void (*intr) __P((void *)); 542 1.3.2.2 bouyer void *arg; 543 1.3.2.2 bouyer struct audio_params *param; 544 1.3.2.2 bouyer { 545 1.3.2.2 bouyer struct cs428x_softc *sc = addr; 546 1.3.2.2 bouyer u_int32_t fmt=0; 547 1.3.2.2 bouyer struct cs428x_dma *p; 548 1.3.2.2 bouyer int dma_count; 549 1.3.2.2 bouyer 550 1.3.2.2 bouyer #ifdef DIAGNOSTIC 551 1.3.2.2 bouyer if (sc->sc_prun) 552 1.3.2.2 bouyer printf("cs4281_trigger_output: already running\n"); 553 1.3.2.2 bouyer #endif 554 1.3.2.3 bouyer sc->sc_prun = 1; 555 1.3.2.2 bouyer 556 1.3.2.2 bouyer DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 557 1.3.2.2 bouyer "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 558 1.3.2.2 bouyer sc->sc_pintr = intr; 559 1.3.2.2 bouyer sc->sc_parg = arg; 560 1.3.2.2 bouyer 561 1.3.2.2 bouyer /* stop playback DMA */ 562 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 563 1.3.2.2 bouyer 564 1.3.2.2 bouyer DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 565 1.3.2.2 bouyer param->precision, param->factor, param->channels, 566 1.3.2.2 bouyer param->encoding)); 567 1.3.2.2 bouyer for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 568 1.3.2.2 bouyer ; 569 1.3.2.2 bouyer if (p == NULL) { 570 1.3.2.2 bouyer printf("cs4281_trigger_output: bad addr %p\n", start); 571 1.3.2.2 bouyer return (EINVAL); 572 1.3.2.2 bouyer } 573 1.3.2.2 bouyer 574 1.3.2.2 bouyer sc->sc_pcount = blksize / sc->hw_blocksize; 575 1.3.2.2 bouyer sc->sc_ps = (char *)start; 576 1.3.2.2 bouyer sc->sc_pe = (char *)end; 577 1.3.2.2 bouyer sc->sc_pdma = p; 578 1.3.2.2 bouyer sc->sc_pbuf = KERNADDR(p); 579 1.3.2.2 bouyer sc->sc_pi = 0; 580 1.3.2.2 bouyer sc->sc_pn = sc->sc_ps; 581 1.3.2.2 bouyer if (blksize >= sc->dma_size) { 582 1.3.2.2 bouyer sc->sc_pn = sc->sc_ps + sc->dma_size; 583 1.3.2.2 bouyer memcpy(sc->sc_pbuf, start, sc->dma_size); 584 1.3.2.2 bouyer ++sc->sc_pi; 585 1.3.2.2 bouyer } else { 586 1.3.2.2 bouyer sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 587 1.3.2.2 bouyer memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 588 1.3.2.2 bouyer } 589 1.3.2.2 bouyer 590 1.3.2.2 bouyer dma_count = sc->dma_size; 591 1.3.2.2 bouyer if (param->precision * param->factor != 8) 592 1.3.2.2 bouyer dma_count /= 2; /* 16 bit */ 593 1.3.2.2 bouyer if (param->channels > 1) 594 1.3.2.2 bouyer dma_count /= 2; /* Stereo */ 595 1.3.2.2 bouyer 596 1.3.2.2 bouyer DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 597 1.3.2.2 bouyer (int)DMAADDR(p), dma_count)); 598 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 599 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 600 1.3.2.2 bouyer 601 1.3.2.2 bouyer /* set playback format */ 602 1.3.2.2 bouyer fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 603 1.3.2.2 bouyer if (param->precision * param->factor == 8) 604 1.3.2.2 bouyer fmt |= DMRn_SIZE8; 605 1.3.2.2 bouyer if (param->channels == 1) 606 1.3.2.2 bouyer fmt |= DMRn_MONO; 607 1.3.2.2 bouyer if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 608 1.3.2.2 bouyer param->encoding == AUDIO_ENCODING_SLINEAR_BE) 609 1.3.2.2 bouyer fmt |= DMRn_BEND; 610 1.3.2.2 bouyer if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 611 1.3.2.2 bouyer param->encoding == AUDIO_ENCODING_ULINEAR_LE) 612 1.3.2.2 bouyer fmt |= DMRn_USIGN; 613 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DMR0, fmt); 614 1.3.2.2 bouyer 615 1.3.2.2 bouyer /* set sample rate */ 616 1.3.2.3 bouyer sc->sc_prate = param->sample_rate; 617 1.3.2.2 bouyer cs4281_set_dac_rate(sc, param->sample_rate); 618 1.3.2.2 bouyer 619 1.3.2.2 bouyer /* start DMA */ 620 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 621 1.3.2.2 bouyer /* Enable interrupts */ 622 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 623 1.3.2.2 bouyer 624 1.3.2.2 bouyer DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 625 1.3.2.2 bouyer DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 626 1.3.2.2 bouyer DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 627 1.3.2.2 bouyer DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 628 1.3.2.2 bouyer DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 629 1.3.2.2 bouyer DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 630 1.3.2.2 bouyer BA0READ4(sc, CS4281_DACSR))); 631 1.3.2.2 bouyer DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 632 1.3.2.2 bouyer DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 633 1.3.2.2 bouyer BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 634 1.3.2.2 bouyer 635 1.3.2.2 bouyer return 0; 636 1.3.2.2 bouyer } 637 1.3.2.2 bouyer 638 1.3.2.2 bouyer int 639 1.3.2.2 bouyer cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 640 1.3.2.2 bouyer void *addr; 641 1.3.2.2 bouyer void *start, *end; 642 1.3.2.2 bouyer int blksize; 643 1.3.2.2 bouyer void (*intr) __P((void *)); 644 1.3.2.2 bouyer void *arg; 645 1.3.2.2 bouyer struct audio_params *param; 646 1.3.2.2 bouyer { 647 1.3.2.2 bouyer struct cs428x_softc *sc = addr; 648 1.3.2.2 bouyer struct cs428x_dma *p; 649 1.3.2.2 bouyer u_int32_t fmt=0; 650 1.3.2.2 bouyer int dma_count; 651 1.3.2.2 bouyer 652 1.3.2.2 bouyer printf("cs4281_trigger_input: not implemented yet\n"); 653 1.3.2.2 bouyer #ifdef DIAGNOSTIC 654 1.3.2.2 bouyer if (sc->sc_rrun) 655 1.3.2.2 bouyer printf("cs4281_trigger_input: already running\n"); 656 1.3.2.2 bouyer #endif 657 1.3.2.3 bouyer sc->sc_rrun = 1; 658 1.3.2.2 bouyer DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 659 1.3.2.2 bouyer "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 660 1.3.2.2 bouyer sc->sc_rintr = intr; 661 1.3.2.2 bouyer sc->sc_rarg = arg; 662 1.3.2.2 bouyer 663 1.3.2.2 bouyer /* stop recording DMA */ 664 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 665 1.3.2.2 bouyer 666 1.3.2.2 bouyer for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 667 1.3.2.2 bouyer ; 668 1.3.2.2 bouyer if (!p) { 669 1.3.2.2 bouyer printf("cs4281_trigger_input: bad addr %p\n", start); 670 1.3.2.2 bouyer return (EINVAL); 671 1.3.2.2 bouyer } 672 1.3.2.2 bouyer 673 1.3.2.2 bouyer sc->sc_rcount = blksize / sc->hw_blocksize; 674 1.3.2.2 bouyer sc->sc_rs = (char *)start; 675 1.3.2.2 bouyer sc->sc_re = (char *)end; 676 1.3.2.2 bouyer sc->sc_rdma = p; 677 1.3.2.2 bouyer sc->sc_rbuf = KERNADDR(p); 678 1.3.2.2 bouyer sc->sc_ri = 0; 679 1.3.2.2 bouyer sc->sc_rn = sc->sc_rs; 680 1.3.2.2 bouyer 681 1.3.2.2 bouyer dma_count = sc->dma_size; 682 1.3.2.2 bouyer if (param->precision * param->factor == 8) 683 1.3.2.2 bouyer dma_count /= 2; 684 1.3.2.2 bouyer if (param->channels > 1) 685 1.3.2.2 bouyer dma_count /= 2; 686 1.3.2.2 bouyer 687 1.3.2.2 bouyer DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 688 1.3.2.2 bouyer (int)DMAADDR(p), dma_count)); 689 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 690 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 691 1.3.2.2 bouyer 692 1.3.2.2 bouyer /* set recording format */ 693 1.3.2.2 bouyer fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 694 1.3.2.2 bouyer if (param->precision * param->factor == 8) 695 1.3.2.2 bouyer fmt |= DMRn_SIZE8; 696 1.3.2.2 bouyer if (param->channels == 1) 697 1.3.2.2 bouyer fmt |= DMRn_MONO; 698 1.3.2.2 bouyer if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 699 1.3.2.2 bouyer param->encoding == AUDIO_ENCODING_SLINEAR_BE) 700 1.3.2.2 bouyer fmt |= DMRn_BEND; 701 1.3.2.2 bouyer if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 702 1.3.2.2 bouyer param->encoding == AUDIO_ENCODING_ULINEAR_LE) 703 1.3.2.2 bouyer fmt |= DMRn_USIGN; 704 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DMR1, fmt); 705 1.3.2.2 bouyer 706 1.3.2.2 bouyer /* set sample rate */ 707 1.3.2.3 bouyer sc->sc_rrate = param->sample_rate; 708 1.3.2.2 bouyer cs4281_set_adc_rate(sc, param->sample_rate); 709 1.3.2.2 bouyer 710 1.3.2.2 bouyer /* Start DMA */ 711 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 712 1.3.2.2 bouyer /* Enable interrupts */ 713 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 714 1.3.2.2 bouyer 715 1.3.2.2 bouyer DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 716 1.3.2.2 bouyer DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 717 1.3.2.2 bouyer DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 718 1.3.2.2 bouyer DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 719 1.3.2.2 bouyer 720 1.3.2.2 bouyer return 0; 721 1.3.2.2 bouyer } 722 1.3.2.2 bouyer 723 1.3.2.2 bouyer /* Power Hook */ 724 1.3.2.2 bouyer void 725 1.3.2.2 bouyer cs4281_power(why, v) 726 1.3.2.2 bouyer int why; 727 1.3.2.2 bouyer void *v; 728 1.3.2.2 bouyer { 729 1.3.2.2 bouyer struct cs428x_softc *sc = (struct cs428x_softc *)v; 730 1.3.2.3 bouyer static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 731 1.3.2.3 bouyer static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 732 1.3.2.2 bouyer 733 1.3.2.2 bouyer DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 734 1.3.2.2 bouyer switch (why) { 735 1.3.2.2 bouyer case PWR_SUSPEND: 736 1.3.2.2 bouyer case PWR_STANDBY: 737 1.3.2.2 bouyer sc->sc_suspend = why; 738 1.3.2.2 bouyer 739 1.3.2.3 bouyer /* save current playback status */ 740 1.3.2.3 bouyer if (sc->sc_prun) { 741 1.3.2.3 bouyer dcr0 = BA0READ4(sc, CS4281_DCR0); 742 1.3.2.3 bouyer dmr0 = BA0READ4(sc, CS4281_DMR0); 743 1.3.2.3 bouyer dbc0 = BA0READ4(sc, CS4281_DBC0); 744 1.3.2.3 bouyer dba0 = BA0READ4(sc, CS4281_DBA0); 745 1.3.2.3 bouyer } 746 1.3.2.3 bouyer 747 1.3.2.3 bouyer /* save current capture status */ 748 1.3.2.3 bouyer if (sc->sc_rrun) { 749 1.3.2.3 bouyer dcr1 = BA0READ4(sc, CS4281_DCR1); 750 1.3.2.3 bouyer dmr1 = BA0READ4(sc, CS4281_DMR1); 751 1.3.2.3 bouyer dbc1 = BA0READ4(sc, CS4281_DBC1); 752 1.3.2.3 bouyer dba1 = BA0READ4(sc, CS4281_DBA1); 753 1.3.2.3 bouyer } 754 1.3.2.3 bouyer /* Stop DMA */ 755 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 756 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 757 1.3.2.2 bouyer break; 758 1.3.2.2 bouyer case PWR_RESUME: 759 1.3.2.2 bouyer if (sc->sc_suspend == PWR_RESUME) { 760 1.3.2.2 bouyer printf("cs4281_power: odd, resume without suspend.\n"); 761 1.3.2.2 bouyer sc->sc_suspend = why; 762 1.3.2.2 bouyer return; 763 1.3.2.2 bouyer } 764 1.3.2.2 bouyer sc->sc_suspend = why; 765 1.3.2.3 bouyer cs4281_init(sc,0); 766 1.3.2.2 bouyer cs4281_reset_codec(sc); 767 1.3.2.2 bouyer 768 1.3.2.3 bouyer /* restore ac97 registers */ 769 1.3.2.2 bouyer (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 770 1.3.2.3 bouyer 771 1.3.2.3 bouyer /* restore DMA related status */ 772 1.3.2.3 bouyer if (sc->sc_prun) { 773 1.3.2.3 bouyer cs4281_set_dac_rate(sc, sc->sc_prate); 774 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DBA0, dba0); 775 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DBC0, dbc0); 776 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DMR0, dmr0); 777 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DCR0, dcr0); 778 1.3.2.3 bouyer } 779 1.3.2.3 bouyer if (sc->sc_rrun) { 780 1.3.2.3 bouyer cs4281_set_adc_rate(sc, sc->sc_rrate); 781 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DBA1, dba1); 782 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DBC1, dbc1); 783 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DMR1, dmr1); 784 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_DCR1, dcr1); 785 1.3.2.3 bouyer } 786 1.3.2.3 bouyer /* enable intterupts */ 787 1.3.2.3 bouyer if (sc->sc_prun || sc->sc_rrun) 788 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 789 1.3.2.2 bouyer break; 790 1.3.2.2 bouyer case PWR_SOFTSUSPEND: 791 1.3.2.2 bouyer case PWR_SOFTSTANDBY: 792 1.3.2.2 bouyer case PWR_SOFTRESUME: 793 1.3.2.2 bouyer break; 794 1.3.2.2 bouyer } 795 1.3.2.2 bouyer } 796 1.3.2.2 bouyer 797 1.3.2.2 bouyer /* control AC97 codec */ 798 1.3.2.2 bouyer void 799 1.3.2.2 bouyer cs4281_reset_codec(void *addr) 800 1.3.2.2 bouyer { 801 1.3.2.2 bouyer struct cs428x_softc *sc; 802 1.3.2.2 bouyer u_int16_t data; 803 1.3.2.2 bouyer u_int32_t dat32; 804 1.3.2.2 bouyer int n; 805 1.3.2.2 bouyer 806 1.3.2.2 bouyer sc = addr; 807 1.3.2.2 bouyer 808 1.3.2.2 bouyer DPRINTFN(3,("cs4281_reset_codec\n")); 809 1.3.2.2 bouyer 810 1.3.2.2 bouyer /* Reset codec */ 811 1.3.2.2 bouyer BA0WRITE4(sc, CS428X_ACCTL, 0); 812 1.3.2.2 bouyer delay(50); /* delay 50us */ 813 1.3.2.2 bouyer 814 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SPMC, 0); 815 1.3.2.2 bouyer delay(100); /* delay 100us */ 816 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 817 1.3.2.2 bouyer #if defined(ENABLE_SECONDARY_CODEC) 818 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 819 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 820 1.3.2.2 bouyer #endif 821 1.3.2.2 bouyer delay(50000); /* XXX: delay 50ms */ 822 1.3.2.2 bouyer 823 1.3.2.2 bouyer /* Enable ASYNC generation */ 824 1.3.2.2 bouyer BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 825 1.3.2.2 bouyer 826 1.3.2.2 bouyer /* Wait for Codec ready. Linux driver wait 50ms here */ 827 1.3.2.2 bouyer n = 0; 828 1.3.2.2 bouyer while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 829 1.3.2.2 bouyer delay(100); 830 1.3.2.2 bouyer if (++n > 1000) { 831 1.3.2.2 bouyer printf("reset_codec: AC97 codec ready timeout\n"); 832 1.3.2.2 bouyer return; 833 1.3.2.2 bouyer } 834 1.3.2.2 bouyer } 835 1.3.2.2 bouyer #if defined(ENABLE_SECONDARY_CODEC) 836 1.3.2.2 bouyer /* secondary codec ready*/ 837 1.3.2.2 bouyer n = 0; 838 1.3.2.2 bouyer while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 839 1.3.2.2 bouyer delay(100); 840 1.3.2.2 bouyer if (++n > 1000) 841 1.3.2.2 bouyer return; 842 1.3.2.2 bouyer } 843 1.3.2.2 bouyer #endif 844 1.3.2.2 bouyer /* Set the serial timing configuration */ 845 1.3.2.2 bouyer /* XXX: undocumented but the Linux driver do this */ 846 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 847 1.3.2.2 bouyer 848 1.3.2.2 bouyer /* Wait for Codec ready signal */ 849 1.3.2.2 bouyer n = 0; 850 1.3.2.2 bouyer do { 851 1.3.2.2 bouyer delay(1000); 852 1.3.2.2 bouyer if (++n > 1000) { 853 1.3.2.2 bouyer printf("%s: Timeout waiting for Codec ready\n", 854 1.3.2.2 bouyer sc->sc_dev.dv_xname); 855 1.3.2.2 bouyer return; 856 1.3.2.2 bouyer } 857 1.3.2.2 bouyer dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 858 1.3.2.2 bouyer } while (dat32 == 0); 859 1.3.2.2 bouyer 860 1.3.2.2 bouyer /* Enable Valid Frame output on ASDOUT */ 861 1.3.2.2 bouyer BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 862 1.3.2.2 bouyer 863 1.3.2.2 bouyer /* Wait until Codec Calibration is finished. Codec register 26h */ 864 1.3.2.2 bouyer n = 0; 865 1.3.2.2 bouyer do { 866 1.3.2.2 bouyer delay(1); 867 1.3.2.2 bouyer if (++n > 1000) { 868 1.3.2.2 bouyer printf("%s: Timeout waiting for Codec calibration\n", 869 1.3.2.2 bouyer sc->sc_dev.dv_xname); 870 1.3.2.2 bouyer return ; 871 1.3.2.2 bouyer } 872 1.3.2.2 bouyer cs428x_read_codec(sc, AC97_REG_POWER, &data); 873 1.3.2.2 bouyer } while ((data & 0x0f) != 0x0f); 874 1.3.2.2 bouyer 875 1.3.2.2 bouyer /* Set the serial timing configuration again */ 876 1.3.2.2 bouyer /* XXX: undocumented but the Linux driver do this */ 877 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 878 1.3.2.2 bouyer 879 1.3.2.2 bouyer /* Wait until we've sampled input slots 3 & 4 as valid */ 880 1.3.2.2 bouyer n = 0; 881 1.3.2.2 bouyer do { 882 1.3.2.2 bouyer delay(1000); 883 1.3.2.2 bouyer if (++n > 1000) { 884 1.3.2.2 bouyer printf("%s: Timeout waiting for sampled input slots as valid\n", 885 1.3.2.2 bouyer sc->sc_dev.dv_xname); 886 1.3.2.2 bouyer return; 887 1.3.2.2 bouyer } 888 1.3.2.2 bouyer dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 889 1.3.2.2 bouyer } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 890 1.3.2.2 bouyer 891 1.3.2.2 bouyer /* Start digital data transfer of audio data to the codec */ 892 1.3.2.2 bouyer BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 893 1.3.2.2 bouyer } 894 1.3.2.2 bouyer 895 1.3.2.2 bouyer 896 1.3.2.2 bouyer /* Internal functions */ 897 1.3.2.2 bouyer 898 1.3.2.2 bouyer /* convert sample rate to register value */ 899 1.3.2.2 bouyer u_int8_t 900 1.3.2.2 bouyer cs4281_sr2regval(rate) 901 1.3.2.2 bouyer int rate; 902 1.3.2.2 bouyer { 903 1.3.2.2 bouyer u_int8_t retval; 904 1.3.2.2 bouyer 905 1.3.2.2 bouyer /* We don't have to change here. but anyway ... */ 906 1.3.2.2 bouyer if (rate > 48000) 907 1.3.2.2 bouyer rate = 48000; 908 1.3.2.2 bouyer if (rate < 6023) 909 1.3.2.2 bouyer rate = 6023; 910 1.3.2.2 bouyer 911 1.3.2.2 bouyer switch (rate) { 912 1.3.2.2 bouyer case 8000: 913 1.3.2.2 bouyer retval = 5; 914 1.3.2.2 bouyer break; 915 1.3.2.2 bouyer case 11025: 916 1.3.2.2 bouyer retval = 4; 917 1.3.2.2 bouyer break; 918 1.3.2.2 bouyer case 16000: 919 1.3.2.2 bouyer retval = 3; 920 1.3.2.2 bouyer break; 921 1.3.2.2 bouyer case 22050: 922 1.3.2.2 bouyer retval = 2; 923 1.3.2.2 bouyer break; 924 1.3.2.2 bouyer case 44100: 925 1.3.2.2 bouyer retval = 1; 926 1.3.2.2 bouyer break; 927 1.3.2.2 bouyer case 48000: 928 1.3.2.2 bouyer retval = 0; 929 1.3.2.2 bouyer break; 930 1.3.2.2 bouyer default: 931 1.3.2.2 bouyer retval = 1536000/rate; /* == 24576000/(rate*16) */ 932 1.3.2.2 bouyer } 933 1.3.2.2 bouyer return retval; 934 1.3.2.2 bouyer } 935 1.3.2.2 bouyer 936 1.3.2.2 bouyer void 937 1.3.2.2 bouyer cs4281_set_adc_rate(sc, rate) 938 1.3.2.2 bouyer struct cs428x_softc *sc; 939 1.3.2.2 bouyer int rate; 940 1.3.2.2 bouyer { 941 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 942 1.3.2.2 bouyer } 943 1.3.2.2 bouyer 944 1.3.2.2 bouyer void 945 1.3.2.2 bouyer cs4281_set_dac_rate(sc, rate) 946 1.3.2.2 bouyer struct cs428x_softc *sc; 947 1.3.2.2 bouyer int rate; 948 1.3.2.2 bouyer { 949 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 950 1.3.2.2 bouyer } 951 1.3.2.2 bouyer 952 1.3.2.2 bouyer int 953 1.3.2.3 bouyer cs4281_init(sc, init) 954 1.3.2.2 bouyer struct cs428x_softc *sc; 955 1.3.2.3 bouyer int init; 956 1.3.2.2 bouyer { 957 1.3.2.2 bouyer int n; 958 1.3.2.2 bouyer u_int16_t data; 959 1.3.2.2 bouyer u_int32_t dat32; 960 1.3.2.2 bouyer 961 1.3.2.2 bouyer /* set "Configuration Write Protect" register to 962 1.3.2.2 bouyer * 0x4281 to allow to write */ 963 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_CWPR, 0x4281); 964 1.3.2.2 bouyer 965 1.3.2.2 bouyer /* 966 1.3.2.2 bouyer * Unset "Full Power-Down bit of Extended PCI Power Management 967 1.3.2.2 bouyer * Control" register to release the reset state. 968 1.3.2.2 bouyer */ 969 1.3.2.2 bouyer dat32 = BA0READ4(sc, CS4281_EPPMC); 970 1.3.2.2 bouyer if (dat32 & EPPMC_FPDN) { 971 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 972 1.3.2.2 bouyer } 973 1.3.2.2 bouyer 974 1.3.2.2 bouyer /* Start PLL out in known state */ 975 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_CLKCR1, 0); 976 1.3.2.2 bouyer /* Start serial ports out in known state */ 977 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SERMC, 0); 978 1.3.2.2 bouyer 979 1.3.2.2 bouyer /* Reset codec */ 980 1.3.2.2 bouyer BA0WRITE4(sc, CS428X_ACCTL, 0); 981 1.3.2.2 bouyer delay(50); /* delay 50us */ 982 1.3.2.2 bouyer 983 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SPMC, 0); 984 1.3.2.2 bouyer delay(100); /* delay 100us */ 985 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 986 1.3.2.2 bouyer #if defined(ENABLE_SECONDARY_CODEC) 987 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 988 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 989 1.3.2.2 bouyer #endif 990 1.3.2.2 bouyer delay(50000); /* XXX: delay 50ms */ 991 1.3.2.2 bouyer 992 1.3.2.2 bouyer /* Turn on Sound System clocks based on ABITCLK */ 993 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 994 1.3.2.2 bouyer delay(50000); /* XXX: delay 50ms */ 995 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 996 1.3.2.2 bouyer 997 1.3.2.2 bouyer /* Set enables for sections that are needed in the SSPM registers */ 998 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SSPM, 999 1.3.2.2 bouyer SSPM_MIXEN | /* Mixer */ 1000 1.3.2.2 bouyer SSPM_CSRCEN | /* Capture SRC */ 1001 1.3.2.2 bouyer SSPM_PSRCEN | /* Playback SRC */ 1002 1.3.2.2 bouyer SSPM_JSEN | /* Joystick */ 1003 1.3.2.2 bouyer SSPM_ACLEN | /* AC LINK */ 1004 1.3.2.2 bouyer SSPM_FMEN /* FM */ 1005 1.3.2.2 bouyer ); 1006 1.3.2.2 bouyer 1007 1.3.2.2 bouyer /* Wait for clock stabilization */ 1008 1.3.2.2 bouyer n = 0; 1009 1.3.2.2 bouyer #if 1 1010 1.3.2.2 bouyer /* what document says */ 1011 1.3.2.2 bouyer while ( ( BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1012 1.3.2.2 bouyer != (CLKCR1_DLLRDY | CLKCR1_CLKON )) { 1013 1.3.2.2 bouyer delay(100); 1014 1.3.2.2 bouyer if ( ++n > 1000 ) 1015 1.3.2.2 bouyer return -1; 1016 1.3.2.2 bouyer } 1017 1.3.2.2 bouyer #else 1018 1.3.2.2 bouyer /* Cirrus driver for Linux does */ 1019 1.3.2.2 bouyer while ( !(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1020 1.3.2.2 bouyer delay(1000); 1021 1.3.2.2 bouyer if ( ++n > 1000 ) 1022 1.3.2.2 bouyer return -1; 1023 1.3.2.2 bouyer } 1024 1.3.2.2 bouyer #endif 1025 1.3.2.2 bouyer 1026 1.3.2.2 bouyer /* Enable ASYNC generation */ 1027 1.3.2.2 bouyer BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1028 1.3.2.2 bouyer 1029 1.3.2.2 bouyer /* Wait for Codec ready. Linux driver wait 50ms here */ 1030 1.3.2.2 bouyer n = 0; 1031 1.3.2.2 bouyer while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1032 1.3.2.2 bouyer delay(100); 1033 1.3.2.2 bouyer if (++n > 1000) 1034 1.3.2.2 bouyer return -1; 1035 1.3.2.2 bouyer } 1036 1.3.2.2 bouyer 1037 1.3.2.2 bouyer #if defined(ENABLE_SECONDARY_CODEC) 1038 1.3.2.2 bouyer /* secondary codec ready*/ 1039 1.3.2.2 bouyer n = 0; 1040 1.3.2.2 bouyer while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1041 1.3.2.2 bouyer delay(100); 1042 1.3.2.2 bouyer if (++n > 1000) 1043 1.3.2.2 bouyer return -1; 1044 1.3.2.2 bouyer } 1045 1.3.2.2 bouyer #endif 1046 1.3.2.2 bouyer 1047 1.3.2.2 bouyer /* Set the serial timing configuration */ 1048 1.3.2.2 bouyer /* XXX: undocumented but the Linux driver do this */ 1049 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1050 1.3.2.2 bouyer 1051 1.3.2.2 bouyer /* Wait for Codec ready signal */ 1052 1.3.2.2 bouyer n = 0; 1053 1.3.2.2 bouyer do { 1054 1.3.2.2 bouyer delay(1000); 1055 1.3.2.2 bouyer if (++n > 1000) { 1056 1.3.2.2 bouyer printf("%s: Timeout waiting for Codec ready\n", 1057 1.3.2.2 bouyer sc->sc_dev.dv_xname); 1058 1.3.2.2 bouyer return -1; 1059 1.3.2.2 bouyer } 1060 1.3.2.2 bouyer dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1061 1.3.2.2 bouyer } while (dat32 == 0); 1062 1.3.2.2 bouyer 1063 1.3.2.2 bouyer /* Enable Valid Frame output on ASDOUT */ 1064 1.3.2.2 bouyer BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1065 1.3.2.2 bouyer 1066 1.3.2.2 bouyer /* Wait until Codec Calibration is finished. Codec register 26h */ 1067 1.3.2.2 bouyer n = 0; 1068 1.3.2.2 bouyer do { 1069 1.3.2.2 bouyer delay(1); 1070 1.3.2.2 bouyer if (++n > 1000) { 1071 1.3.2.2 bouyer printf("%s: Timeout waiting for Codec calibration\n", 1072 1.3.2.2 bouyer sc->sc_dev.dv_xname); 1073 1.3.2.2 bouyer return -1; 1074 1.3.2.2 bouyer } 1075 1.3.2.2 bouyer cs428x_read_codec(sc, AC97_REG_POWER, &data); 1076 1.3.2.2 bouyer } while ((data & 0x0f) != 0x0f); 1077 1.3.2.2 bouyer 1078 1.3.2.2 bouyer /* Set the serial timing configuration again */ 1079 1.3.2.2 bouyer /* XXX: undocumented but the Linux driver do this */ 1080 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1081 1.3.2.2 bouyer 1082 1.3.2.2 bouyer /* Wait until we've sampled input slots 3 & 4 as valid */ 1083 1.3.2.2 bouyer n = 0; 1084 1.3.2.2 bouyer do { 1085 1.3.2.2 bouyer delay(1000); 1086 1.3.2.2 bouyer if (++n > 1000) { 1087 1.3.2.2 bouyer printf("%s: Timeout waiting for sampled input slots as valid\n", 1088 1.3.2.2 bouyer sc->sc_dev.dv_xname); 1089 1.3.2.2 bouyer return -1; 1090 1.3.2.2 bouyer } 1091 1.3.2.2 bouyer dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1092 1.3.2.2 bouyer } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1093 1.3.2.2 bouyer 1094 1.3.2.2 bouyer /* Start digital data transfer of audio data to the codec */ 1095 1.3.2.2 bouyer BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1096 1.3.2.2 bouyer 1097 1.3.2.2 bouyer cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1098 1.3.2.2 bouyer cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1099 1.3.2.2 bouyer 1100 1.3.2.2 bouyer /* Power on the DAC */ 1101 1.3.2.2 bouyer cs428x_read_codec(sc, AC97_REG_POWER, &data); 1102 1.3.2.2 bouyer cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1103 1.3.2.2 bouyer 1104 1.3.2.2 bouyer /* Wait until we sample a DAC ready state. 1105 1.3.2.2 bouyer * Not documented, but Linux driver does. 1106 1.3.2.2 bouyer */ 1107 1.3.2.2 bouyer for (n = 0; n < 32; ++n) { 1108 1.3.2.2 bouyer delay(1000); 1109 1.3.2.2 bouyer cs428x_read_codec(sc, AC97_REG_POWER, &data); 1110 1.3.2.2 bouyer if (data & 0x02) 1111 1.3.2.2 bouyer break; 1112 1.3.2.2 bouyer } 1113 1.3.2.2 bouyer 1114 1.3.2.2 bouyer /* Power on the ADC */ 1115 1.3.2.2 bouyer cs428x_read_codec(sc, AC97_REG_POWER, &data); 1116 1.3.2.2 bouyer cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1117 1.3.2.2 bouyer 1118 1.3.2.2 bouyer /* Wait until we sample ADC ready state. 1119 1.3.2.2 bouyer * Not documented, but Linux driver does. 1120 1.3.2.2 bouyer */ 1121 1.3.2.2 bouyer for (n = 0; n < 32; ++n) { 1122 1.3.2.2 bouyer delay(1000); 1123 1.3.2.2 bouyer cs428x_read_codec(sc, AC97_REG_POWER, &data); 1124 1.3.2.2 bouyer if (data & 0x01) 1125 1.3.2.2 bouyer break; 1126 1.3.2.2 bouyer } 1127 1.3.2.2 bouyer 1128 1.3.2.2 bouyer #if 0 1129 1.3.2.2 bouyer /* Initialize AC-Link features */ 1130 1.3.2.2 bouyer /* variable sample-rate support */ 1131 1.3.2.2 bouyer mem = BA0READ4(sc, CS4281_SERMC); 1132 1.3.2.2 bouyer mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1133 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SERMC, mem); 1134 1.3.2.2 bouyer /* XXX: more... */ 1135 1.3.2.2 bouyer 1136 1.3.2.2 bouyer /* Initialize SSCR register features */ 1137 1.3.2.2 bouyer /* XXX: hardware volume setting */ 1138 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1139 1.3.2.2 bouyer #endif 1140 1.3.2.2 bouyer 1141 1.3.2.2 bouyer /* disable Sound Blaster Pro emulation */ 1142 1.3.2.2 bouyer /* XXX: 1143 1.3.2.2 bouyer * Cannot set since the documents does not describe which bit is 1144 1.3.2.2 bouyer * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1145 1.3.2.2 bouyer * we can ignore it.*/ 1146 1.3.2.2 bouyer #if 0 1147 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1148 1.3.2.2 bouyer #endif 1149 1.3.2.2 bouyer 1150 1.3.2.2 bouyer /* map AC97 PCM playback to DMA Channel 0 */ 1151 1.3.2.2 bouyer /* Reset FEN bit to setup first */ 1152 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc,CS4281_FCR0) & ~FCRn_FEN)); 1153 1.3.2.2 bouyer /* 1154 1.3.2.2 bouyer *| RS[4:0]/| | 1155 1.3.2.2 bouyer *| LS[4:0] | AC97 | Slot Function 1156 1.3.2.2 bouyer *|---------+--------+-------------------- 1157 1.3.2.2 bouyer *| 0 | 3 | Left PCM Playback 1158 1.3.2.2 bouyer *| 1 | 4 | Right PCM Playback 1159 1.3.2.2 bouyer *| 2 | 5 | Phone Line 1 DAC 1160 1.3.2.2 bouyer *| 3 | 6 | Center PCM Playback 1161 1.3.2.2 bouyer *.... 1162 1.3.2.2 bouyer * quoted from Table 29(p109) 1163 1.3.2.2 bouyer */ 1164 1.3.2.2 bouyer dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1165 1.3.2.2 bouyer 0x00 << 16 | /* LS[4:0] = 0 see above */ 1166 1.3.2.2 bouyer 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1167 1.3.2.2 bouyer 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1168 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_FCR0, dat32); 1169 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1170 1.3.2.2 bouyer 1171 1.3.2.2 bouyer /* map AC97 PCM record to DMA Channel 1 */ 1172 1.3.2.2 bouyer /* Reset FEN bit to setup first */ 1173 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc,CS4281_FCR1) & ~FCRn_FEN)); 1174 1.3.2.2 bouyer /* 1175 1.3.2.2 bouyer *| RS[4:0]/| 1176 1.3.2.2 bouyer *| LS[4:0] | AC97 | Slot Function 1177 1.3.2.2 bouyer *|---------+------+------------------- 1178 1.3.2.2 bouyer *| 10 | 3 | Left PCM Record 1179 1.3.2.2 bouyer *| 11 | 4 | Right PCM Record 1180 1.3.2.2 bouyer *| 12 | 5 | Phone Line 1 ADC 1181 1.3.2.2 bouyer *| 13 | 6 | Mic ADC 1182 1.3.2.2 bouyer *.... 1183 1.3.2.2 bouyer * quoted from Table 30(p109) 1184 1.3.2.2 bouyer */ 1185 1.3.2.2 bouyer dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1186 1.3.2.2 bouyer 0x0a << 16 | /* LS[4:0] = 10 See above */ 1187 1.3.2.2 bouyer 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1188 1.3.2.2 bouyer 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1189 1.3.2.2 bouyer 1190 1.3.2.2 bouyer /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1191 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1192 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1193 1.3.2.2 bouyer 1194 1.3.2.2 bouyer #if 0 1195 1.3.2.2 bouyer /* Disable DMA Channel 2, 3 */ 1196 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc,CS4281_FCR2) & ~FCRn_FEN)); 1197 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc,CS4281_FCR3) & ~FCRn_FEN)); 1198 1.3.2.2 bouyer #endif 1199 1.3.2.2 bouyer 1200 1.3.2.2 bouyer /* Set the SRC Slot Assignment accordingly */ 1201 1.3.2.2 bouyer /*| PLSS[4:0]/ 1202 1.3.2.2 bouyer *| PRSS[4:0] | AC97 | Slot Function 1203 1.3.2.2 bouyer *|-----------+------+---------------- 1204 1.3.2.2 bouyer *| 0 | 3 | Left PCM Playback 1205 1.3.2.2 bouyer *| 1 | 4 | Right PCM Playback 1206 1.3.2.2 bouyer *| 2 | 5 | phone line 1 DAC 1207 1.3.2.2 bouyer *| 3 | 6 | Center PCM Playback 1208 1.3.2.2 bouyer *| 4 | 7 | Left Surround PCM Playback 1209 1.3.2.2 bouyer *| 5 | 8 | Right Surround PCM Playback 1210 1.3.2.2 bouyer *...... 1211 1.3.2.2 bouyer * 1212 1.3.2.2 bouyer *| CLSS[4:0]/ 1213 1.3.2.2 bouyer *| CRSS[4:0] | AC97 | Codec |Slot Function 1214 1.3.2.2 bouyer *|-----------+------+-------+----------------- 1215 1.3.2.2 bouyer *| 10 | 3 |Primary| Left PCM Record 1216 1.3.2.2 bouyer *| 11 | 4 |Primary| Right PCM Record 1217 1.3.2.2 bouyer *| 12 | 5 |Primary| Phone Line 1 ADC 1218 1.3.2.2 bouyer *| 13 | 6 |Primary| Mic ADC 1219 1.3.2.2 bouyer *|..... 1220 1.3.2.2 bouyer *| 20 | 3 | Sec. | Left PCM Record 1221 1.3.2.2 bouyer *| 21 | 4 | Sec. | Right PCM Record 1222 1.3.2.2 bouyer *| 22 | 5 | Sec. | Phone Line 1 ADC 1223 1.3.2.2 bouyer *| 23 | 6 | Sec. | Mic ADC 1224 1.3.2.2 bouyer */ 1225 1.3.2.2 bouyer dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1226 1.3.2.2 bouyer 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1227 1.3.2.2 bouyer 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1228 1.3.2.2 bouyer 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1229 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_SRCSA, dat32); 1230 1.3.2.2 bouyer 1231 1.3.2.2 bouyer /* Set interrupt to occured at Half and Full terminal 1232 1.3.2.2 bouyer * count interrupt enable for DMA channel 0 and 1. 1233 1.3.2.2 bouyer * To keep DMA stop, set MSK. 1234 1.3.2.2 bouyer */ 1235 1.3.2.2 bouyer dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1236 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DCR0, dat32); 1237 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DCR1, dat32); 1238 1.3.2.2 bouyer 1239 1.3.2.2 bouyer /* Set Auto-Initialize Contorl enable */ 1240 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DMR0, 1241 1.3.2.2 bouyer DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1242 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_DMR1, 1243 1.3.2.2 bouyer DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1244 1.3.2.2 bouyer 1245 1.3.2.2 bouyer /* Clear DMA Mask in HIMR */ 1246 1.3.2.2 bouyer dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1247 1.3.2.2 bouyer BA0WRITE4(sc, CS4281_HIMR, 1248 1.3.2.2 bouyer BA0READ4(sc, CS4281_HIMR) & dat32); 1249 1.3.2.3 bouyer 1250 1.3.2.3 bouyer /* set current status */ 1251 1.3.2.3 bouyer if (init != 0) { 1252 1.3.2.3 bouyer sc->sc_prun = 0; 1253 1.3.2.3 bouyer sc->sc_rrun = 0; 1254 1.3.2.3 bouyer } 1255 1.3.2.3 bouyer 1256 1.3.2.3 bouyer /* setup playback volume */ 1257 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_PPRVC, 7); 1258 1.3.2.3 bouyer BA0WRITE4(sc, CS4281_PPLVC, 7); 1259 1.3.2.3 bouyer 1260 1.3.2.2 bouyer return 0; 1261 1.3.2.2 bouyer } 1262
Indexes created Thu Oct 02 14:10:14 GMT 2025