cs4281.c revision 1.4.2.4
1 1.4.2.4 he /* $NetBSD: cs4281.c,v 1.4.2.4 2001/12/27 11:56:54 he Exp $ */ 2 1.4.2.2 he 3 1.4.2.2 he /* 4 1.4.2.2 he * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 1.4.2.2 he * 6 1.4.2.2 he * Redistribution and use in source and binary forms, with or without 7 1.4.2.2 he * modification, are permitted provided that the following conditions 8 1.4.2.2 he * are met: 9 1.4.2.2 he * 1. Redistributions of source code must retain the above copyright 10 1.4.2.2 he * notice, this list of conditions and the following disclaimer. 11 1.4.2.2 he * 2. Redistributions in binary form must reproduce the above copyright 12 1.4.2.2 he * notice, this list of conditions and the following disclaimer in the 13 1.4.2.2 he * documentation and/or other materials provided with the distribution. 14 1.4.2.2 he * 3. All advertising materials mentioning features or use of this software 15 1.4.2.2 he * must display the following acknowledgement: 16 1.4.2.2 he * This product includes software developed by Tatoku Ogaito 17 1.4.2.2 he * for the NetBSD Project. 18 1.4.2.2 he * 4. The name of the author may not be used to endorse or promote products 19 1.4.2.2 he * derived from this software without specific prior written permission 20 1.4.2.2 he * 21 1.4.2.2 he * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 1.4.2.2 he * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 1.4.2.2 he * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 1.4.2.2 he * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 1.4.2.2 he * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 1.4.2.2 he * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 1.4.2.2 he * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.4.2.2 he * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 1.4.2.2 he * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 1.4.2.2 he * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1.4.2.2 he */ 32 1.4.2.2 he 33 1.4.2.2 he /* 34 1.4.2.2 he * Cirrus Logic CS4281 driver. 35 1.4.2.2 he * Data sheets can be found 36 1.4.2.2 he * http://www.cirrus.com/ftp/pub/4281.pdf 37 1.4.2.2 he * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 1.4.2.2 he * 39 1.4.2.2 he * TODO: 40 1.4.2.2 he * 1: midi and FM support 41 1.4.2.2 he * 2: ... 42 1.4.2.2 he * 43 1.4.2.2 he */ 44 1.4.2.2 he 45 1.4.2.2 he #include <sys/param.h> 46 1.4.2.2 he #include <sys/systm.h> 47 1.4.2.2 he #include <sys/kernel.h> 48 1.4.2.2 he #include <sys/malloc.h> 49 1.4.2.2 he #include <sys/fcntl.h> 50 1.4.2.2 he #include <sys/device.h> 51 1.4.2.2 he #include <sys/types.h> 52 1.4.2.2 he #include <sys/systm.h> 53 1.4.2.2 he 54 1.4.2.2 he #include <dev/pci/pcidevs.h> 55 1.4.2.2 he #include <dev/pci/pcivar.h> 56 1.4.2.2 he #include <dev/pci/cs4281reg.h> 57 1.4.2.2 he #include <dev/pci/cs428xreg.h> 58 1.4.2.2 he 59 1.4.2.2 he #include <sys/audioio.h> 60 1.4.2.2 he #include <dev/audio_if.h> 61 1.4.2.2 he #include <dev/midi_if.h> 62 1.4.2.2 he #include <dev/mulaw.h> 63 1.4.2.2 he #include <dev/auconv.h> 64 1.4.2.2 he 65 1.4.2.2 he #include <dev/ic/ac97reg.h> 66 1.4.2.2 he #include <dev/ic/ac97var.h> 67 1.4.2.2 he 68 1.4.2.2 he #include <dev/pci/cs428x.h> 69 1.4.2.2 he 70 1.4.2.2 he #include <machine/bus.h> 71 1.4.2.2 he 72 1.4.2.2 he #if defined(ENABLE_SECONDARY_CODEC) 73 1.4.2.2 he #define MAX_CHANNELS (4) 74 1.4.2.2 he #define MAX_FIFO_SIZE 32 /* 128/4channels */ 75 1.4.2.2 he #else 76 1.4.2.2 he #define MAX_CHANNELS (2) 77 1.4.2.2 he #define MAX_FIFO_SIZE 64 /* 128/2channels */ 78 1.4.2.2 he #endif 79 1.4.2.2 he 80 1.4.2.2 he /* IF functions for audio driver */ 81 1.4.2.2 he int cs4281_match(struct device *, struct cfdata *, void *); 82 1.4.2.2 he void cs4281_attach(struct device *, struct device *, void *); 83 1.4.2.2 he int cs4281_intr(void *); 84 1.4.2.2 he int cs4281_query_encoding(void *, struct audio_encoding *); 85 1.4.2.2 he int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 86 1.4.2.2 he int cs4281_halt_output(void *); 87 1.4.2.2 he int cs4281_halt_input(void *); 88 1.4.2.2 he int cs4281_getdev(void *, struct audio_device *); 89 1.4.2.2 he int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 90 1.4.2.2 he void *, struct audio_params *); 91 1.4.2.2 he int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 92 1.4.2.2 he void *, struct audio_params *); 93 1.4.2.2 he 94 1.4.2.2 he void cs4281_reset_codec(void *); 95 1.4.2.2 he 96 1.4.2.2 he /* Internal functions */ 97 1.4.2.2 he u_int8_t cs4281_sr2regval(int); 98 1.4.2.2 he void cs4281_set_dac_rate(struct cs428x_softc *, int); 99 1.4.2.2 he void cs4281_set_adc_rate(struct cs428x_softc *, int); 100 1.4.2.2 he int cs4281_init(struct cs428x_softc *, int); 101 1.4.2.2 he 102 1.4.2.2 he /* Power Management */ 103 1.4.2.2 he void cs4281_power(int, void *); 104 1.4.2.2 he 105 1.4.2.2 he struct audio_hw_if cs4281_hw_if = { 106 1.4.2.2 he cs428x_open, 107 1.4.2.2 he cs428x_close, 108 1.4.2.2 he NULL, 109 1.4.2.2 he cs4281_query_encoding, 110 1.4.2.2 he cs4281_set_params, 111 1.4.2.2 he cs428x_round_blocksize, 112 1.4.2.2 he NULL, 113 1.4.2.2 he NULL, 114 1.4.2.2 he NULL, 115 1.4.2.2 he NULL, 116 1.4.2.2 he NULL, 117 1.4.2.2 he cs4281_halt_output, 118 1.4.2.2 he cs4281_halt_input, 119 1.4.2.2 he NULL, 120 1.4.2.2 he cs4281_getdev, 121 1.4.2.2 he NULL, 122 1.4.2.2 he cs428x_mixer_set_port, 123 1.4.2.2 he cs428x_mixer_get_port, 124 1.4.2.2 he cs428x_query_devinfo, 125 1.4.2.2 he cs428x_malloc, 126 1.4.2.2 he cs428x_free, 127 1.4.2.2 he cs428x_round_buffersize, 128 1.4.2.2 he cs428x_mappage, 129 1.4.2.2 he cs428x_get_props, 130 1.4.2.2 he cs4281_trigger_output, 131 1.4.2.2 he cs4281_trigger_input, 132 1.4.2.2 he }; 133 1.4.2.2 he 134 1.4.2.2 he #if NMIDI > 0 && 0 135 1.4.2.2 he /* Midi Interface */ 136 1.4.2.2 he void cs4281_midi_close(void*); 137 1.4.2.2 he void cs4281_midi_getinfo(void *, struct midi_info *); 138 1.4.2.2 he int cs4281_midi_open(void *, int, void (*)(void *, int), 139 1.4.2.2 he void (*)(void *), void *); 140 1.4.2.2 he int cs4281_midi_output(void *, int); 141 1.4.2.2 he 142 1.4.2.2 he struct midi_hw_if cs4281_midi_hw_if = { 143 1.4.2.2 he cs4281_midi_open, 144 1.4.2.2 he cs4281_midi_close, 145 1.4.2.2 he cs4281_midi_output, 146 1.4.2.2 he cs4281_midi_getinfo, 147 1.4.2.2 he 0, 148 1.4.2.2 he }; 149 1.4.2.2 he #endif 150 1.4.2.2 he 151 1.4.2.2 he struct cfattach clct_ca = { 152 1.4.2.2 he sizeof(struct cs428x_softc), cs4281_match, cs4281_attach 153 1.4.2.2 he }; 154 1.4.2.2 he 155 1.4.2.2 he struct audio_device cs4281_device = { 156 1.4.2.2 he "CS4281", 157 1.4.2.2 he "", 158 1.4.2.2 he "cs4281" 159 1.4.2.2 he }; 160 1.4.2.2 he 161 1.4.2.2 he 162 1.4.2.2 he int 163 1.4.2.2 he cs4281_match(parent, match, aux) 164 1.4.2.2 he struct device *parent; 165 1.4.2.2 he struct cfdata *match; 166 1.4.2.2 he void *aux; 167 1.4.2.2 he { 168 1.4.2.2 he struct pci_attach_args *pa = (struct pci_attach_args *)aux; 169 1.4.2.2 he 170 1.4.2.2 he if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 171 1.4.2.2 he return 0; 172 1.4.2.2 he if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 173 1.4.2.2 he return 1; 174 1.4.2.2 he return 0; 175 1.4.2.2 he } 176 1.4.2.2 he 177 1.4.2.2 he void 178 1.4.2.2 he cs4281_attach(parent, self, aux) 179 1.4.2.2 he struct device *parent; 180 1.4.2.2 he struct device *self; 181 1.4.2.2 he void *aux; 182 1.4.2.2 he { 183 1.4.2.2 he struct cs428x_softc *sc = (struct cs428x_softc *)self; 184 1.4.2.2 he struct pci_attach_args *pa = (struct pci_attach_args *)aux; 185 1.4.2.2 he pci_chipset_tag_t pc = pa->pa_pc; 186 1.4.2.2 he char const *intrstr; 187 1.4.2.2 he pci_intr_handle_t ih; 188 1.4.2.2 he pcireg_t reg; 189 1.4.2.2 he char devinfo[256]; 190 1.4.2.2 he int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 191 1.4.2.2 he 192 1.4.2.2 he pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 193 1.4.2.2 he printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 194 1.4.2.2 he 195 1.4.2.2 he /* Map I/O register */ 196 1.4.2.2 he if (pci_mapreg_map(pa, PCI_BA0, 197 1.4.2.2 he PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 198 1.4.2.2 he &sc->ba0t, &sc->ba0h, NULL, NULL)) { 199 1.4.2.2 he printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 200 1.4.2.2 he return; 201 1.4.2.2 he } 202 1.4.2.2 he if (pci_mapreg_map(pa, PCI_BA1, 203 1.4.2.2 he PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 204 1.4.2.2 he &sc->ba1t, &sc->ba1h, NULL, NULL)) { 205 1.4.2.2 he printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 206 1.4.2.2 he return; 207 1.4.2.2 he } 208 1.4.2.2 he 209 1.4.2.2 he sc->sc_dmatag = pa->pa_dmat; 210 1.4.2.2 he 211 1.4.2.2 he /* 212 1.4.2.2 he * Set Power State D0. 213 1.4.2.2 he * Without do this, 0xffffffff is read from all registers after 214 1.4.2.2 he * using Windows. 215 1.4.2.2 he * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 216 1.4.2.2 he */ 217 1.4.2.2 he if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 218 1.4.2.2 he &pci_pwrmgmt_cap_reg, 0)) { 219 1.4.2.2 he 220 1.4.2.2 he pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 221 1.4.2.2 he reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 222 1.4.2.2 he pci_pwrmgmt_csr_reg); 223 1.4.2.2 he if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 224 1.4.2.2 he pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 225 1.4.2.2 he (reg & ~PCI_PMCSR_STATE_MASK) | 226 1.4.2.2 he PCI_PMCSR_STATE_D0); 227 1.4.2.2 he } 228 1.4.2.2 he } 229 1.4.2.2 he 230 1.4.2.2 he /* Enable the device (set bus master flag) */ 231 1.4.2.2 he reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 232 1.4.2.2 he pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 233 1.4.2.2 he reg | PCI_COMMAND_MASTER_ENABLE); 234 1.4.2.2 he 235 1.4.2.2 he #if 0 236 1.4.2.2 he /* LATENCY_TIMER setting */ 237 1.4.2.2 he temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 238 1.4.2.2 he if ( PCI_LATTIMER(temp1) < 32 ) { 239 1.4.2.2 he temp1 &= 0xffff00ff; 240 1.4.2.2 he temp1 |= 0x00002000; 241 1.4.2.2 he pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 242 1.4.2.2 he } 243 1.4.2.2 he #endif 244 1.4.2.2 he 245 1.4.2.2 he /* Map and establish the interrupt. */ 246 1.4.2.3 he if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 247 1.4.2.2 he pa->pa_intrline, &ih)) { 248 1.4.2.2 he printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 249 1.4.2.2 he return; 250 1.4.2.2 he } 251 1.4.2.2 he intrstr = pci_intr_string(pc, ih); 252 1.4.2.2 he 253 1.4.2.2 he sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 254 1.4.2.2 he if (sc->sc_ih == NULL) { 255 1.4.2.2 he printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 256 1.4.2.2 he if (intrstr != NULL) 257 1.4.2.2 he printf(" at %s", intrstr); 258 1.4.2.2 he printf("\n"); 259 1.4.2.2 he return; 260 1.4.2.2 he } 261 1.4.2.2 he printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 262 1.4.2.2 he 263 1.4.2.2 he /* 264 1.4.2.2 he * Sound System start-up 265 1.4.2.2 he */ 266 1.4.2.2 he if (cs4281_init(sc,1) != 0) 267 1.4.2.2 he return; 268 1.4.2.2 he 269 1.4.2.2 he sc->type = TYPE_CS4281; 270 1.4.2.2 he sc->halt_input = cs4281_halt_input; 271 1.4.2.2 he sc->halt_output = cs4281_halt_output; 272 1.4.2.2 he 273 1.4.2.2 he sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 274 1.4.2.2 he sc->dma_align = 0x10; 275 1.4.2.2 he sc->hw_blocksize = sc->dma_size / 2; 276 1.4.2.2 he 277 1.4.2.2 he /* AC 97 attachment */ 278 1.4.2.2 he sc->host_if.arg = sc; 279 1.4.2.2 he sc->host_if.attach = cs428x_attach_codec; 280 1.4.2.2 he sc->host_if.read = cs428x_read_codec; 281 1.4.2.2 he sc->host_if.write = cs428x_write_codec; 282 1.4.2.2 he sc->host_if.reset = cs4281_reset_codec; 283 1.4.2.2 he if (ac97_attach(&sc->host_if) != 0) { 284 1.4.2.2 he printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 285 1.4.2.2 he return; 286 1.4.2.2 he } 287 1.4.2.2 he audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 288 1.4.2.2 he 289 1.4.2.2 he #if NMIDI > 0 && 0 290 1.4.2.2 he midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 291 1.4.2.2 he #endif 292 1.4.2.2 he 293 1.4.2.2 he sc->sc_suspend = PWR_RESUME; 294 1.4.2.2 he sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 295 1.4.2.2 he } 296 1.4.2.2 he 297 1.4.2.2 he int 298 1.4.2.2 he cs4281_intr(p) 299 1.4.2.2 he void *p; 300 1.4.2.2 he { 301 1.4.2.2 he struct cs428x_softc *sc = p; 302 1.4.2.2 he u_int32_t intr, hdsr0, hdsr1; 303 1.4.2.2 he char *empty_dma; 304 1.4.2.2 he int handled = 0; 305 1.4.2.2 he 306 1.4.2.2 he hdsr0 = 0; 307 1.4.2.2 he hdsr1 = 0; 308 1.4.2.2 he 309 1.4.2.2 he /* grab interrupt register */ 310 1.4.2.2 he intr = BA0READ4(sc, CS4281_HISR); 311 1.4.2.2 he 312 1.4.2.2 he DPRINTF(("cs4281_intr:")); 313 1.4.2.2 he /* not for me */ 314 1.4.2.2 he if ((intr & HISR_INTENA) == 0) { 315 1.4.2.2 he /* clear the interrupt register */ 316 1.4.2.2 he BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 317 1.4.2.2 he return 0; 318 1.4.2.2 he } 319 1.4.2.2 he 320 1.4.2.2 he if (intr & HISR_DMA0) 321 1.4.2.2 he hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 322 1.4.2.2 he if (intr & HISR_DMA1) 323 1.4.2.2 he hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 324 1.4.2.2 he /* clear the interrupt register */ 325 1.4.2.2 he BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 326 1.4.2.2 he 327 1.4.2.2 he DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 328 1.4.2.2 he intr, hdsr0, hdsr1)); 329 1.4.2.2 he 330 1.4.2.2 he /* Playback Interrupt */ 331 1.4.2.2 he if (intr & HISR_DMA0) { 332 1.4.2.2 he handled = 1; 333 1.4.2.2 he DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 334 1.4.2.2 he (int)BA0READ4(sc, CS4281_DCC0))); 335 1.4.2.2 he if (sc->sc_pintr) { 336 1.4.2.2 he if ((sc->sc_pi%sc->sc_pcount) == 0) 337 1.4.2.2 he sc->sc_pintr(sc->sc_parg); 338 1.4.2.2 he } else { 339 1.4.2.2 he printf("unexpected play intr\n"); 340 1.4.2.2 he } 341 1.4.2.2 he /* copy buffer */ 342 1.4.2.2 he ++sc->sc_pi; 343 1.4.2.2 he empty_dma = sc->sc_pdma->addr; 344 1.4.2.2 he if (sc->sc_pi&1) 345 1.4.2.2 he empty_dma += sc->hw_blocksize; 346 1.4.2.2 he memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 347 1.4.2.2 he sc->sc_pn += sc->hw_blocksize; 348 1.4.2.2 he if (sc->sc_pn >= sc->sc_pe) 349 1.4.2.2 he sc->sc_pn = sc->sc_ps; 350 1.4.2.2 he } 351 1.4.2.2 he if (intr & HISR_DMA1) { 352 1.4.2.2 he handled = 1; 353 1.4.2.2 he /* copy from dma */ 354 1.4.2.2 he DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 355 1.4.2.2 he (int)BA0READ4(sc, CS4281_DCC1))); 356 1.4.2.2 he ++sc->sc_ri; 357 1.4.2.2 he empty_dma = sc->sc_rdma->addr; 358 1.4.2.2 he if ((sc->sc_ri & 1) == 0) 359 1.4.2.2 he empty_dma += sc->hw_blocksize; 360 1.4.2.2 he memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 361 1.4.2.2 he if (sc->sc_rn >= sc->sc_re) 362 1.4.2.2 he sc->sc_rn = sc->sc_rs; 363 1.4.2.2 he if (sc->sc_rintr) { 364 1.4.2.2 he if ((sc->sc_ri % sc->sc_rcount) == 0) 365 1.4.2.2 he sc->sc_rintr(sc->sc_rarg); 366 1.4.2.2 he } else { 367 1.4.2.2 he printf("unexpected record intr\n"); 368 1.4.2.2 he } 369 1.4.2.2 he } 370 1.4.2.2 he DPRINTF(("\n")); 371 1.4.2.2 he 372 1.4.2.2 he return handled; 373 1.4.2.2 he } 374 1.4.2.2 he 375 1.4.2.2 he int 376 1.4.2.2 he cs4281_query_encoding(addr, fp) 377 1.4.2.2 he void *addr; 378 1.4.2.2 he struct audio_encoding *fp; 379 1.4.2.2 he { 380 1.4.2.2 he switch (fp->index) { 381 1.4.2.2 he case 0: 382 1.4.2.2 he strcpy(fp->name, AudioEulinear); 383 1.4.2.2 he fp->encoding = AUDIO_ENCODING_ULINEAR; 384 1.4.2.2 he fp->precision = 8; 385 1.4.2.2 he fp->flags = 0; 386 1.4.2.2 he break; 387 1.4.2.2 he case 1: 388 1.4.2.2 he strcpy(fp->name, AudioEmulaw); 389 1.4.2.2 he fp->encoding = AUDIO_ENCODING_ULAW; 390 1.4.2.2 he fp->precision = 8; 391 1.4.2.2 he fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 392 1.4.2.2 he break; 393 1.4.2.2 he case 2: 394 1.4.2.2 he strcpy(fp->name, AudioEalaw); 395 1.4.2.2 he fp->encoding = AUDIO_ENCODING_ALAW; 396 1.4.2.2 he fp->precision = 8; 397 1.4.2.2 he fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 398 1.4.2.2 he break; 399 1.4.2.2 he case 3: 400 1.4.2.2 he strcpy(fp->name, AudioEslinear); 401 1.4.2.2 he fp->encoding = AUDIO_ENCODING_SLINEAR; 402 1.4.2.2 he fp->precision = 8; 403 1.4.2.2 he fp->flags = 0; 404 1.4.2.2 he break; 405 1.4.2.2 he case 4: 406 1.4.2.2 he strcpy(fp->name, AudioEslinear_le); 407 1.4.2.2 he fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 408 1.4.2.2 he fp->precision = 16; 409 1.4.2.2 he fp->flags = 0; 410 1.4.2.2 he break; 411 1.4.2.2 he case 5: 412 1.4.2.2 he strcpy(fp->name, AudioEulinear_le); 413 1.4.2.2 he fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 414 1.4.2.2 he fp->precision = 16; 415 1.4.2.2 he fp->flags = 0; 416 1.4.2.2 he break; 417 1.4.2.2 he case 6: 418 1.4.2.2 he strcpy(fp->name, AudioEslinear_be); 419 1.4.2.2 he fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 420 1.4.2.2 he fp->precision = 16; 421 1.4.2.2 he fp->flags = 0; 422 1.4.2.2 he break; 423 1.4.2.2 he case 7: 424 1.4.2.2 he strcpy(fp->name, AudioEulinear_be); 425 1.4.2.2 he fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 426 1.4.2.2 he fp->precision = 16; 427 1.4.2.2 he fp->flags = 0; 428 1.4.2.2 he break; 429 1.4.2.2 he default: 430 1.4.2.2 he return EINVAL; 431 1.4.2.2 he } 432 1.4.2.2 he return 0; 433 1.4.2.2 he } 434 1.4.2.2 he 435 1.4.2.2 he int 436 1.4.2.2 he cs4281_set_params(addr, setmode, usemode, play, rec) 437 1.4.2.2 he void *addr; 438 1.4.2.2 he int setmode, usemode; 439 1.4.2.2 he struct audio_params *play, *rec; 440 1.4.2.2 he { 441 1.4.2.2 he struct cs428x_softc *sc = addr; 442 1.4.2.2 he struct audio_params *p; 443 1.4.2.2 he int mode; 444 1.4.2.2 he 445 1.4.2.2 he for (mode = AUMODE_RECORD; mode != -1; 446 1.4.2.2 he mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 447 1.4.2.2 he if ((setmode & mode) == 0) 448 1.4.2.2 he continue; 449 1.4.2.2 he 450 1.4.2.2 he p = mode == AUMODE_PLAY ? play : rec; 451 1.4.2.2 he 452 1.4.2.2 he if (p == play) { 453 1.4.2.2 he DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 454 1.4.2.2 he p->sample_rate, p->precision, p->channels)); 455 1.4.2.2 he if (p->sample_rate < 6023 || p->sample_rate > 48000 || 456 1.4.2.2 he (p->precision != 8 && p->precision != 16) || 457 1.4.2.2 he (p->channels != 1 && p->channels != 2)) { 458 1.4.2.2 he return (EINVAL); 459 1.4.2.2 he } 460 1.4.2.2 he } else { 461 1.4.2.2 he DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 462 1.4.2.2 he p->sample_rate, p->precision, p->channels)); 463 1.4.2.2 he if (p->sample_rate < 6023 || p->sample_rate > 48000 || 464 1.4.2.2 he (p->precision != 8 && p->precision != 16) || 465 1.4.2.2 he (p->channels != 1 && p->channels != 2)) { 466 1.4.2.2 he return (EINVAL); 467 1.4.2.2 he } 468 1.4.2.2 he } 469 1.4.2.2 he p->factor = 1; 470 1.4.2.2 he p->sw_code = 0; 471 1.4.2.2 he 472 1.4.2.2 he switch (p->encoding) { 473 1.4.2.2 he case AUDIO_ENCODING_SLINEAR_BE: 474 1.4.2.2 he break; 475 1.4.2.2 he case AUDIO_ENCODING_SLINEAR_LE: 476 1.4.2.2 he break; 477 1.4.2.2 he case AUDIO_ENCODING_ULINEAR_BE: 478 1.4.2.2 he break; 479 1.4.2.2 he case AUDIO_ENCODING_ULINEAR_LE: 480 1.4.2.2 he break; 481 1.4.2.2 he case AUDIO_ENCODING_ULAW: 482 1.4.2.2 he if (mode == AUMODE_PLAY) { 483 1.4.2.2 he p->sw_code = mulaw_to_slinear8; 484 1.4.2.2 he } else { 485 1.4.2.2 he p->sw_code = slinear8_to_mulaw; 486 1.4.2.2 he } 487 1.4.2.2 he break; 488 1.4.2.2 he case AUDIO_ENCODING_ALAW: 489 1.4.2.2 he if (mode == AUMODE_PLAY) { 490 1.4.2.2 he p->sw_code = alaw_to_slinear8; 491 1.4.2.2 he } else { 492 1.4.2.2 he p->sw_code = slinear8_to_alaw; 493 1.4.2.2 he } 494 1.4.2.2 he break; 495 1.4.2.2 he default: 496 1.4.2.2 he return (EINVAL); 497 1.4.2.2 he } 498 1.4.2.2 he } 499 1.4.2.2 he 500 1.4.2.2 he /* set sample rate */ 501 1.4.2.2 he cs4281_set_dac_rate(sc, play->sample_rate); 502 1.4.2.2 he cs4281_set_adc_rate(sc, rec->sample_rate); 503 1.4.2.2 he return 0; 504 1.4.2.2 he } 505 1.4.2.2 he 506 1.4.2.2 he int 507 1.4.2.2 he cs4281_halt_output(addr) 508 1.4.2.2 he void *addr; 509 1.4.2.2 he { 510 1.4.2.2 he struct cs428x_softc *sc = addr; 511 1.4.2.2 he 512 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 513 1.4.2.2 he sc->sc_prun = 0; 514 1.4.2.2 he return 0; 515 1.4.2.2 he } 516 1.4.2.2 he 517 1.4.2.2 he int 518 1.4.2.2 he cs4281_halt_input(addr) 519 1.4.2.2 he void *addr; 520 1.4.2.2 he { 521 1.4.2.2 he struct cs428x_softc *sc = addr; 522 1.4.2.2 he 523 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 524 1.4.2.2 he sc->sc_rrun = 0; 525 1.4.2.2 he return 0; 526 1.4.2.2 he } 527 1.4.2.2 he 528 1.4.2.2 he int 529 1.4.2.2 he cs4281_getdev(addr, retp) 530 1.4.2.2 he void *addr; 531 1.4.2.2 he struct audio_device *retp; 532 1.4.2.2 he { 533 1.4.2.2 he *retp = cs4281_device; 534 1.4.2.2 he return 0; 535 1.4.2.2 he } 536 1.4.2.2 he 537 1.4.2.2 he int 538 1.4.2.2 he cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 539 1.4.2.2 he void *addr; 540 1.4.2.2 he void *start, *end; 541 1.4.2.2 he int blksize; 542 1.4.2.2 he void (*intr) __P((void *)); 543 1.4.2.2 he void *arg; 544 1.4.2.2 he struct audio_params *param; 545 1.4.2.2 he { 546 1.4.2.2 he struct cs428x_softc *sc = addr; 547 1.4.2.2 he u_int32_t fmt=0; 548 1.4.2.2 he struct cs428x_dma *p; 549 1.4.2.2 he int dma_count; 550 1.4.2.2 he 551 1.4.2.2 he #ifdef DIAGNOSTIC 552 1.4.2.2 he if (sc->sc_prun) 553 1.4.2.2 he printf("cs4281_trigger_output: already running\n"); 554 1.4.2.2 he #endif 555 1.4.2.2 he sc->sc_prun = 1; 556 1.4.2.2 he 557 1.4.2.2 he DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 558 1.4.2.2 he "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 559 1.4.2.2 he sc->sc_pintr = intr; 560 1.4.2.2 he sc->sc_parg = arg; 561 1.4.2.2 he 562 1.4.2.2 he /* stop playback DMA */ 563 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 564 1.4.2.2 he 565 1.4.2.2 he DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 566 1.4.2.2 he param->precision, param->factor, param->channels, 567 1.4.2.2 he param->encoding)); 568 1.4.2.2 he for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 569 1.4.2.2 he ; 570 1.4.2.2 he if (p == NULL) { 571 1.4.2.2 he printf("cs4281_trigger_output: bad addr %p\n", start); 572 1.4.2.2 he return (EINVAL); 573 1.4.2.2 he } 574 1.4.2.2 he 575 1.4.2.2 he sc->sc_pcount = blksize / sc->hw_blocksize; 576 1.4.2.2 he sc->sc_ps = (char *)start; 577 1.4.2.2 he sc->sc_pe = (char *)end; 578 1.4.2.2 he sc->sc_pdma = p; 579 1.4.2.2 he sc->sc_pbuf = KERNADDR(p); 580 1.4.2.2 he sc->sc_pi = 0; 581 1.4.2.2 he sc->sc_pn = sc->sc_ps; 582 1.4.2.2 he if (blksize >= sc->dma_size) { 583 1.4.2.2 he sc->sc_pn = sc->sc_ps + sc->dma_size; 584 1.4.2.2 he memcpy(sc->sc_pbuf, start, sc->dma_size); 585 1.4.2.2 he ++sc->sc_pi; 586 1.4.2.2 he } else { 587 1.4.2.2 he sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 588 1.4.2.2 he memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 589 1.4.2.2 he } 590 1.4.2.2 he 591 1.4.2.2 he dma_count = sc->dma_size; 592 1.4.2.2 he if (param->precision * param->factor != 8) 593 1.4.2.2 he dma_count /= 2; /* 16 bit */ 594 1.4.2.2 he if (param->channels > 1) 595 1.4.2.2 he dma_count /= 2; /* Stereo */ 596 1.4.2.2 he 597 1.4.2.2 he DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 598 1.4.2.2 he (int)DMAADDR(p), dma_count)); 599 1.4.2.2 he BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 600 1.4.2.2 he BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 601 1.4.2.2 he 602 1.4.2.2 he /* set playback format */ 603 1.4.2.2 he fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 604 1.4.2.2 he if (param->precision * param->factor == 8) 605 1.4.2.2 he fmt |= DMRn_SIZE8; 606 1.4.2.2 he if (param->channels == 1) 607 1.4.2.2 he fmt |= DMRn_MONO; 608 1.4.2.2 he if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 609 1.4.2.2 he param->encoding == AUDIO_ENCODING_SLINEAR_BE) 610 1.4.2.2 he fmt |= DMRn_BEND; 611 1.4.2.2 he if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 612 1.4.2.2 he param->encoding == AUDIO_ENCODING_ULINEAR_LE) 613 1.4.2.2 he fmt |= DMRn_USIGN; 614 1.4.2.2 he BA0WRITE4(sc, CS4281_DMR0, fmt); 615 1.4.2.2 he 616 1.4.2.2 he /* set sample rate */ 617 1.4.2.2 he sc->sc_prate = param->sample_rate; 618 1.4.2.2 he cs4281_set_dac_rate(sc, param->sample_rate); 619 1.4.2.2 he 620 1.4.2.2 he /* start DMA */ 621 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 622 1.4.2.2 he /* Enable interrupts */ 623 1.4.2.2 he BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 624 1.4.2.2 he 625 1.4.2.2 he DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 626 1.4.2.2 he DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 627 1.4.2.2 he DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 628 1.4.2.2 he DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 629 1.4.2.2 he DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 630 1.4.2.2 he DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 631 1.4.2.2 he BA0READ4(sc, CS4281_DACSR))); 632 1.4.2.2 he DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 633 1.4.2.2 he DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 634 1.4.2.2 he BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 635 1.4.2.2 he 636 1.4.2.2 he return 0; 637 1.4.2.2 he } 638 1.4.2.2 he 639 1.4.2.2 he int 640 1.4.2.2 he cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 641 1.4.2.2 he void *addr; 642 1.4.2.2 he void *start, *end; 643 1.4.2.2 he int blksize; 644 1.4.2.2 he void (*intr) __P((void *)); 645 1.4.2.2 he void *arg; 646 1.4.2.2 he struct audio_params *param; 647 1.4.2.2 he { 648 1.4.2.2 he struct cs428x_softc *sc = addr; 649 1.4.2.2 he struct cs428x_dma *p; 650 1.4.2.2 he u_int32_t fmt=0; 651 1.4.2.2 he int dma_count; 652 1.4.2.2 he 653 1.4.2.2 he #ifdef DIAGNOSTIC 654 1.4.2.2 he if (sc->sc_rrun) 655 1.4.2.2 he printf("cs4281_trigger_input: already running\n"); 656 1.4.2.2 he #endif 657 1.4.2.2 he sc->sc_rrun = 1; 658 1.4.2.2 he DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 659 1.4.2.2 he "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 660 1.4.2.2 he sc->sc_rintr = intr; 661 1.4.2.2 he sc->sc_rarg = arg; 662 1.4.2.2 he 663 1.4.2.2 he /* stop recording DMA */ 664 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 665 1.4.2.2 he 666 1.4.2.2 he for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 667 1.4.2.2 he ; 668 1.4.2.2 he if (!p) { 669 1.4.2.2 he printf("cs4281_trigger_input: bad addr %p\n", start); 670 1.4.2.2 he return (EINVAL); 671 1.4.2.2 he } 672 1.4.2.2 he 673 1.4.2.2 he sc->sc_rcount = blksize / sc->hw_blocksize; 674 1.4.2.2 he sc->sc_rs = (char *)start; 675 1.4.2.2 he sc->sc_re = (char *)end; 676 1.4.2.2 he sc->sc_rdma = p; 677 1.4.2.2 he sc->sc_rbuf = KERNADDR(p); 678 1.4.2.2 he sc->sc_ri = 0; 679 1.4.2.2 he sc->sc_rn = sc->sc_rs; 680 1.4.2.2 he 681 1.4.2.2 he dma_count = sc->dma_size; 682 1.4.2.2 he if (param->precision * param->factor == 8) 683 1.4.2.2 he dma_count /= 2; 684 1.4.2.2 he if (param->channels > 1) 685 1.4.2.2 he dma_count /= 2; 686 1.4.2.2 he 687 1.4.2.2 he DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 688 1.4.2.2 he (int)DMAADDR(p), dma_count)); 689 1.4.2.2 he BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 690 1.4.2.2 he BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 691 1.4.2.2 he 692 1.4.2.2 he /* set recording format */ 693 1.4.2.2 he fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 694 1.4.2.2 he if (param->precision * param->factor == 8) 695 1.4.2.2 he fmt |= DMRn_SIZE8; 696 1.4.2.2 he if (param->channels == 1) 697 1.4.2.2 he fmt |= DMRn_MONO; 698 1.4.2.2 he if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 699 1.4.2.2 he param->encoding == AUDIO_ENCODING_SLINEAR_BE) 700 1.4.2.2 he fmt |= DMRn_BEND; 701 1.4.2.2 he if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 702 1.4.2.2 he param->encoding == AUDIO_ENCODING_ULINEAR_LE) 703 1.4.2.2 he fmt |= DMRn_USIGN; 704 1.4.2.2 he BA0WRITE4(sc, CS4281_DMR1, fmt); 705 1.4.2.2 he 706 1.4.2.2 he /* set sample rate */ 707 1.4.2.2 he sc->sc_rrate = param->sample_rate; 708 1.4.2.2 he cs4281_set_adc_rate(sc, param->sample_rate); 709 1.4.2.2 he 710 1.4.2.2 he /* Start DMA */ 711 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 712 1.4.2.2 he /* Enable interrupts */ 713 1.4.2.2 he BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 714 1.4.2.2 he 715 1.4.2.2 he DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 716 1.4.2.2 he DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 717 1.4.2.2 he DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 718 1.4.2.2 he DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 719 1.4.2.2 he 720 1.4.2.2 he return 0; 721 1.4.2.2 he } 722 1.4.2.2 he 723 1.4.2.2 he /* Power Hook */ 724 1.4.2.2 he void 725 1.4.2.2 he cs4281_power(why, v) 726 1.4.2.2 he int why; 727 1.4.2.2 he void *v; 728 1.4.2.2 he { 729 1.4.2.2 he struct cs428x_softc *sc = (struct cs428x_softc *)v; 730 1.4.2.2 he static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 731 1.4.2.2 he static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 732 1.4.2.2 he 733 1.4.2.2 he DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 734 1.4.2.2 he switch (why) { 735 1.4.2.2 he case PWR_SUSPEND: 736 1.4.2.2 he case PWR_STANDBY: 737 1.4.2.2 he sc->sc_suspend = why; 738 1.4.2.2 he 739 1.4.2.2 he /* save current playback status */ 740 1.4.2.2 he if (sc->sc_prun) { 741 1.4.2.2 he dcr0 = BA0READ4(sc, CS4281_DCR0); 742 1.4.2.2 he dmr0 = BA0READ4(sc, CS4281_DMR0); 743 1.4.2.2 he dbc0 = BA0READ4(sc, CS4281_DBC0); 744 1.4.2.2 he dba0 = BA0READ4(sc, CS4281_DBA0); 745 1.4.2.2 he } 746 1.4.2.2 he 747 1.4.2.2 he /* save current capture status */ 748 1.4.2.2 he if (sc->sc_rrun) { 749 1.4.2.2 he dcr1 = BA0READ4(sc, CS4281_DCR1); 750 1.4.2.2 he dmr1 = BA0READ4(sc, CS4281_DMR1); 751 1.4.2.2 he dbc1 = BA0READ4(sc, CS4281_DBC1); 752 1.4.2.2 he dba1 = BA0READ4(sc, CS4281_DBA1); 753 1.4.2.2 he } 754 1.4.2.2 he /* Stop DMA */ 755 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 756 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 757 1.4.2.2 he break; 758 1.4.2.2 he case PWR_RESUME: 759 1.4.2.2 he if (sc->sc_suspend == PWR_RESUME) { 760 1.4.2.2 he printf("cs4281_power: odd, resume without suspend.\n"); 761 1.4.2.2 he sc->sc_suspend = why; 762 1.4.2.2 he return; 763 1.4.2.2 he } 764 1.4.2.2 he sc->sc_suspend = why; 765 1.4.2.2 he cs4281_init(sc,0); 766 1.4.2.2 he cs4281_reset_codec(sc); 767 1.4.2.2 he 768 1.4.2.2 he /* restore ac97 registers */ 769 1.4.2.2 he (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 770 1.4.2.2 he 771 1.4.2.2 he /* restore DMA related status */ 772 1.4.2.2 he if (sc->sc_prun) { 773 1.4.2.2 he cs4281_set_dac_rate(sc, sc->sc_prate); 774 1.4.2.2 he BA0WRITE4(sc, CS4281_DBA0, dba0); 775 1.4.2.2 he BA0WRITE4(sc, CS4281_DBC0, dbc0); 776 1.4.2.2 he BA0WRITE4(sc, CS4281_DMR0, dmr0); 777 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR0, dcr0); 778 1.4.2.2 he } 779 1.4.2.2 he if (sc->sc_rrun) { 780 1.4.2.2 he cs4281_set_adc_rate(sc, sc->sc_rrate); 781 1.4.2.2 he BA0WRITE4(sc, CS4281_DBA1, dba1); 782 1.4.2.2 he BA0WRITE4(sc, CS4281_DBC1, dbc1); 783 1.4.2.2 he BA0WRITE4(sc, CS4281_DMR1, dmr1); 784 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR1, dcr1); 785 1.4.2.2 he } 786 1.4.2.2 he /* enable intterupts */ 787 1.4.2.2 he if (sc->sc_prun || sc->sc_rrun) 788 1.4.2.2 he BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 789 1.4.2.2 he break; 790 1.4.2.2 he case PWR_SOFTSUSPEND: 791 1.4.2.2 he case PWR_SOFTSTANDBY: 792 1.4.2.2 he case PWR_SOFTRESUME: 793 1.4.2.2 he break; 794 1.4.2.2 he } 795 1.4.2.2 he } 796 1.4.2.2 he 797 1.4.2.2 he /* control AC97 codec */ 798 1.4.2.2 he void 799 1.4.2.2 he cs4281_reset_codec(void *addr) 800 1.4.2.2 he { 801 1.4.2.2 he struct cs428x_softc *sc; 802 1.4.2.2 he u_int16_t data; 803 1.4.2.2 he u_int32_t dat32; 804 1.4.2.2 he int n; 805 1.4.2.2 he 806 1.4.2.2 he sc = addr; 807 1.4.2.2 he 808 1.4.2.2 he DPRINTFN(3,("cs4281_reset_codec\n")); 809 1.4.2.2 he 810 1.4.2.2 he /* Reset codec */ 811 1.4.2.2 he BA0WRITE4(sc, CS428X_ACCTL, 0); 812 1.4.2.2 he delay(50); /* delay 50us */ 813 1.4.2.2 he 814 1.4.2.2 he BA0WRITE4(sc, CS4281_SPMC, 0); 815 1.4.2.2 he delay(100); /* delay 100us */ 816 1.4.2.2 he BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 817 1.4.2.2 he #if defined(ENABLE_SECONDARY_CODEC) 818 1.4.2.2 he BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 819 1.4.2.2 he BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 820 1.4.2.2 he #endif 821 1.4.2.2 he delay(50000); /* XXX: delay 50ms */ 822 1.4.2.2 he 823 1.4.2.2 he /* Enable ASYNC generation */ 824 1.4.2.2 he BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 825 1.4.2.2 he 826 1.4.2.2 he /* Wait for Codec ready. Linux driver wait 50ms here */ 827 1.4.2.2 he n = 0; 828 1.4.2.2 he while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 829 1.4.2.2 he delay(100); 830 1.4.2.2 he if (++n > 1000) { 831 1.4.2.2 he printf("reset_codec: AC97 codec ready timeout\n"); 832 1.4.2.2 he return; 833 1.4.2.2 he } 834 1.4.2.2 he } 835 1.4.2.2 he #if defined(ENABLE_SECONDARY_CODEC) 836 1.4.2.2 he /* secondary codec ready*/ 837 1.4.2.2 he n = 0; 838 1.4.2.2 he while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 839 1.4.2.2 he delay(100); 840 1.4.2.2 he if (++n > 1000) 841 1.4.2.2 he return; 842 1.4.2.2 he } 843 1.4.2.2 he #endif 844 1.4.2.2 he /* Set the serial timing configuration */ 845 1.4.2.2 he /* XXX: undocumented but the Linux driver do this */ 846 1.4.2.2 he BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 847 1.4.2.2 he 848 1.4.2.2 he /* Wait for Codec ready signal */ 849 1.4.2.2 he n = 0; 850 1.4.2.2 he do { 851 1.4.2.2 he delay(1000); 852 1.4.2.2 he if (++n > 1000) { 853 1.4.2.2 he printf("%s: Timeout waiting for Codec ready\n", 854 1.4.2.2 he sc->sc_dev.dv_xname); 855 1.4.2.2 he return; 856 1.4.2.2 he } 857 1.4.2.2 he dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 858 1.4.2.2 he } while (dat32 == 0); 859 1.4.2.2 he 860 1.4.2.2 he /* Enable Valid Frame output on ASDOUT */ 861 1.4.2.2 he BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 862 1.4.2.2 he 863 1.4.2.2 he /* Wait until Codec Calibration is finished. Codec register 26h */ 864 1.4.2.2 he n = 0; 865 1.4.2.2 he do { 866 1.4.2.2 he delay(1); 867 1.4.2.2 he if (++n > 1000) { 868 1.4.2.2 he printf("%s: Timeout waiting for Codec calibration\n", 869 1.4.2.2 he sc->sc_dev.dv_xname); 870 1.4.2.2 he return ; 871 1.4.2.2 he } 872 1.4.2.2 he cs428x_read_codec(sc, AC97_REG_POWER, &data); 873 1.4.2.2 he } while ((data & 0x0f) != 0x0f); 874 1.4.2.2 he 875 1.4.2.2 he /* Set the serial timing configuration again */ 876 1.4.2.2 he /* XXX: undocumented but the Linux driver do this */ 877 1.4.2.2 he BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 878 1.4.2.2 he 879 1.4.2.2 he /* Wait until we've sampled input slots 3 & 4 as valid */ 880 1.4.2.2 he n = 0; 881 1.4.2.2 he do { 882 1.4.2.2 he delay(1000); 883 1.4.2.2 he if (++n > 1000) { 884 1.4.2.2 he printf("%s: Timeout waiting for sampled input slots as valid\n", 885 1.4.2.2 he sc->sc_dev.dv_xname); 886 1.4.2.2 he return; 887 1.4.2.2 he } 888 1.4.2.2 he dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 889 1.4.2.2 he } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 890 1.4.2.2 he 891 1.4.2.2 he /* Start digital data transfer of audio data to the codec */ 892 1.4.2.2 he BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 893 1.4.2.2 he } 894 1.4.2.2 he 895 1.4.2.2 he 896 1.4.2.2 he /* Internal functions */ 897 1.4.2.2 he 898 1.4.2.2 he /* convert sample rate to register value */ 899 1.4.2.2 he u_int8_t 900 1.4.2.2 he cs4281_sr2regval(rate) 901 1.4.2.2 he int rate; 902 1.4.2.2 he { 903 1.4.2.2 he u_int8_t retval; 904 1.4.2.2 he 905 1.4.2.2 he /* We don't have to change here. but anyway ... */ 906 1.4.2.2 he if (rate > 48000) 907 1.4.2.2 he rate = 48000; 908 1.4.2.2 he if (rate < 6023) 909 1.4.2.2 he rate = 6023; 910 1.4.2.2 he 911 1.4.2.2 he switch (rate) { 912 1.4.2.2 he case 8000: 913 1.4.2.2 he retval = 5; 914 1.4.2.2 he break; 915 1.4.2.2 he case 11025: 916 1.4.2.2 he retval = 4; 917 1.4.2.2 he break; 918 1.4.2.2 he case 16000: 919 1.4.2.2 he retval = 3; 920 1.4.2.2 he break; 921 1.4.2.2 he case 22050: 922 1.4.2.2 he retval = 2; 923 1.4.2.2 he break; 924 1.4.2.2 he case 44100: 925 1.4.2.2 he retval = 1; 926 1.4.2.2 he break; 927 1.4.2.2 he case 48000: 928 1.4.2.2 he retval = 0; 929 1.4.2.2 he break; 930 1.4.2.2 he default: 931 1.4.2.2 he retval = 1536000/rate; /* == 24576000/(rate*16) */ 932 1.4.2.2 he } 933 1.4.2.2 he return retval; 934 1.4.2.2 he } 935 1.4.2.2 he 936 1.4.2.2 he void 937 1.4.2.2 he cs4281_set_adc_rate(sc, rate) 938 1.4.2.2 he struct cs428x_softc *sc; 939 1.4.2.2 he int rate; 940 1.4.2.2 he { 941 1.4.2.2 he BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 942 1.4.2.2 he } 943 1.4.2.2 he 944 1.4.2.2 he void 945 1.4.2.2 he cs4281_set_dac_rate(sc, rate) 946 1.4.2.2 he struct cs428x_softc *sc; 947 1.4.2.2 he int rate; 948 1.4.2.2 he { 949 1.4.2.2 he BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 950 1.4.2.2 he } 951 1.4.2.2 he 952 1.4.2.2 he int 953 1.4.2.2 he cs4281_init(sc, init) 954 1.4.2.2 he struct cs428x_softc *sc; 955 1.4.2.2 he int init; 956 1.4.2.2 he { 957 1.4.2.2 he int n; 958 1.4.2.2 he u_int16_t data; 959 1.4.2.2 he u_int32_t dat32; 960 1.4.2.2 he 961 1.4.2.2 he /* set "Configuration Write Protect" register to 962 1.4.2.2 he * 0x4281 to allow to write */ 963 1.4.2.2 he BA0WRITE4(sc, CS4281_CWPR, 0x4281); 964 1.4.2.2 he 965 1.4.2.2 he /* 966 1.4.2.2 he * Unset "Full Power-Down bit of Extended PCI Power Management 967 1.4.2.2 he * Control" register to release the reset state. 968 1.4.2.2 he */ 969 1.4.2.2 he dat32 = BA0READ4(sc, CS4281_EPPMC); 970 1.4.2.2 he if (dat32 & EPPMC_FPDN) { 971 1.4.2.2 he BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 972 1.4.2.2 he } 973 1.4.2.2 he 974 1.4.2.2 he /* Start PLL out in known state */ 975 1.4.2.2 he BA0WRITE4(sc, CS4281_CLKCR1, 0); 976 1.4.2.2 he /* Start serial ports out in known state */ 977 1.4.2.2 he BA0WRITE4(sc, CS4281_SERMC, 0); 978 1.4.2.2 he 979 1.4.2.2 he /* Reset codec */ 980 1.4.2.2 he BA0WRITE4(sc, CS428X_ACCTL, 0); 981 1.4.2.2 he delay(50); /* delay 50us */ 982 1.4.2.2 he 983 1.4.2.2 he BA0WRITE4(sc, CS4281_SPMC, 0); 984 1.4.2.2 he delay(100); /* delay 100us */ 985 1.4.2.2 he BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 986 1.4.2.2 he #if defined(ENABLE_SECONDARY_CODEC) 987 1.4.2.2 he BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 988 1.4.2.2 he BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 989 1.4.2.2 he #endif 990 1.4.2.2 he delay(50000); /* XXX: delay 50ms */ 991 1.4.2.2 he 992 1.4.2.2 he /* Turn on Sound System clocks based on ABITCLK */ 993 1.4.2.2 he BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 994 1.4.2.2 he delay(50000); /* XXX: delay 50ms */ 995 1.4.2.2 he BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 996 1.4.2.2 he 997 1.4.2.2 he /* Set enables for sections that are needed in the SSPM registers */ 998 1.4.2.2 he BA0WRITE4(sc, CS4281_SSPM, 999 1.4.2.2 he SSPM_MIXEN | /* Mixer */ 1000 1.4.2.2 he SSPM_CSRCEN | /* Capture SRC */ 1001 1.4.2.2 he SSPM_PSRCEN | /* Playback SRC */ 1002 1.4.2.2 he SSPM_JSEN | /* Joystick */ 1003 1.4.2.2 he SSPM_ACLEN | /* AC LINK */ 1004 1.4.2.2 he SSPM_FMEN /* FM */ 1005 1.4.2.2 he ); 1006 1.4.2.2 he 1007 1.4.2.2 he /* Wait for clock stabilization */ 1008 1.4.2.2 he n = 0; 1009 1.4.2.2 he #if 1 1010 1.4.2.2 he /* what document says */ 1011 1.4.2.2 he while ( ( BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1012 1.4.2.2 he != (CLKCR1_DLLRDY | CLKCR1_CLKON )) { 1013 1.4.2.2 he delay(100); 1014 1.4.2.2 he if ( ++n > 1000 ) 1015 1.4.2.2 he return -1; 1016 1.4.2.2 he } 1017 1.4.2.2 he #else 1018 1.4.2.2 he /* Cirrus driver for Linux does */ 1019 1.4.2.2 he while ( !(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1020 1.4.2.2 he delay(1000); 1021 1.4.2.2 he if ( ++n > 1000 ) 1022 1.4.2.2 he return -1; 1023 1.4.2.2 he } 1024 1.4.2.2 he #endif 1025 1.4.2.2 he 1026 1.4.2.2 he /* Enable ASYNC generation */ 1027 1.4.2.2 he BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1028 1.4.2.2 he 1029 1.4.2.2 he /* Wait for Codec ready. Linux driver wait 50ms here */ 1030 1.4.2.2 he n = 0; 1031 1.4.2.2 he while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1032 1.4.2.2 he delay(100); 1033 1.4.2.2 he if (++n > 1000) 1034 1.4.2.2 he return -1; 1035 1.4.2.2 he } 1036 1.4.2.2 he 1037 1.4.2.2 he #if defined(ENABLE_SECONDARY_CODEC) 1038 1.4.2.2 he /* secondary codec ready*/ 1039 1.4.2.2 he n = 0; 1040 1.4.2.2 he while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1041 1.4.2.2 he delay(100); 1042 1.4.2.2 he if (++n > 1000) 1043 1.4.2.2 he return -1; 1044 1.4.2.2 he } 1045 1.4.2.2 he #endif 1046 1.4.2.2 he 1047 1.4.2.2 he /* Set the serial timing configuration */ 1048 1.4.2.2 he /* XXX: undocumented but the Linux driver do this */ 1049 1.4.2.2 he BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1050 1.4.2.2 he 1051 1.4.2.2 he /* Wait for Codec ready signal */ 1052 1.4.2.2 he n = 0; 1053 1.4.2.2 he do { 1054 1.4.2.2 he delay(1000); 1055 1.4.2.2 he if (++n > 1000) { 1056 1.4.2.2 he printf("%s: Timeout waiting for Codec ready\n", 1057 1.4.2.2 he sc->sc_dev.dv_xname); 1058 1.4.2.2 he return -1; 1059 1.4.2.2 he } 1060 1.4.2.2 he dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1061 1.4.2.2 he } while (dat32 == 0); 1062 1.4.2.2 he 1063 1.4.2.2 he /* Enable Valid Frame output on ASDOUT */ 1064 1.4.2.2 he BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1065 1.4.2.2 he 1066 1.4.2.2 he /* Wait until Codec Calibration is finished. Codec register 26h */ 1067 1.4.2.2 he n = 0; 1068 1.4.2.2 he do { 1069 1.4.2.2 he delay(1); 1070 1.4.2.2 he if (++n > 1000) { 1071 1.4.2.2 he printf("%s: Timeout waiting for Codec calibration\n", 1072 1.4.2.2 he sc->sc_dev.dv_xname); 1073 1.4.2.2 he return -1; 1074 1.4.2.2 he } 1075 1.4.2.2 he cs428x_read_codec(sc, AC97_REG_POWER, &data); 1076 1.4.2.2 he } while ((data & 0x0f) != 0x0f); 1077 1.4.2.2 he 1078 1.4.2.2 he /* Set the serial timing configuration again */ 1079 1.4.2.2 he /* XXX: undocumented but the Linux driver do this */ 1080 1.4.2.2 he BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1081 1.4.2.2 he 1082 1.4.2.2 he /* Wait until we've sampled input slots 3 & 4 as valid */ 1083 1.4.2.2 he n = 0; 1084 1.4.2.2 he do { 1085 1.4.2.2 he delay(1000); 1086 1.4.2.2 he if (++n > 1000) { 1087 1.4.2.2 he printf("%s: Timeout waiting for sampled input slots as valid\n", 1088 1.4.2.2 he sc->sc_dev.dv_xname); 1089 1.4.2.2 he return -1; 1090 1.4.2.2 he } 1091 1.4.2.2 he dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1092 1.4.2.2 he } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1093 1.4.2.2 he 1094 1.4.2.2 he /* Start digital data transfer of audio data to the codec */ 1095 1.4.2.2 he BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1096 1.4.2.2 he 1097 1.4.2.2 he cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1098 1.4.2.2 he cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1099 1.4.2.2 he 1100 1.4.2.2 he /* Power on the DAC */ 1101 1.4.2.2 he cs428x_read_codec(sc, AC97_REG_POWER, &data); 1102 1.4.2.2 he cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1103 1.4.2.2 he 1104 1.4.2.2 he /* Wait until we sample a DAC ready state. 1105 1.4.2.2 he * Not documented, but Linux driver does. 1106 1.4.2.2 he */ 1107 1.4.2.2 he for (n = 0; n < 32; ++n) { 1108 1.4.2.2 he delay(1000); 1109 1.4.2.2 he cs428x_read_codec(sc, AC97_REG_POWER, &data); 1110 1.4.2.2 he if (data & 0x02) 1111 1.4.2.2 he break; 1112 1.4.2.2 he } 1113 1.4.2.2 he 1114 1.4.2.2 he /* Power on the ADC */ 1115 1.4.2.2 he cs428x_read_codec(sc, AC97_REG_POWER, &data); 1116 1.4.2.2 he cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1117 1.4.2.2 he 1118 1.4.2.2 he /* Wait until we sample ADC ready state. 1119 1.4.2.2 he * Not documented, but Linux driver does. 1120 1.4.2.2 he */ 1121 1.4.2.2 he for (n = 0; n < 32; ++n) { 1122 1.4.2.2 he delay(1000); 1123 1.4.2.2 he cs428x_read_codec(sc, AC97_REG_POWER, &data); 1124 1.4.2.2 he if (data & 0x01) 1125 1.4.2.2 he break; 1126 1.4.2.2 he } 1127 1.4.2.2 he 1128 1.4.2.2 he #if 0 1129 1.4.2.2 he /* Initialize AC-Link features */ 1130 1.4.2.2 he /* variable sample-rate support */ 1131 1.4.2.2 he mem = BA0READ4(sc, CS4281_SERMC); 1132 1.4.2.2 he mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1133 1.4.2.2 he BA0WRITE4(sc, CS4281_SERMC, mem); 1134 1.4.2.2 he /* XXX: more... */ 1135 1.4.2.2 he 1136 1.4.2.2 he /* Initialize SSCR register features */ 1137 1.4.2.2 he /* XXX: hardware volume setting */ 1138 1.4.2.2 he BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1139 1.4.2.2 he #endif 1140 1.4.2.2 he 1141 1.4.2.2 he /* disable Sound Blaster Pro emulation */ 1142 1.4.2.2 he /* XXX: 1143 1.4.2.2 he * Cannot set since the documents does not describe which bit is 1144 1.4.2.2 he * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1145 1.4.2.2 he * we can ignore it.*/ 1146 1.4.2.2 he #if 0 1147 1.4.2.2 he BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1148 1.4.2.2 he #endif 1149 1.4.2.2 he 1150 1.4.2.2 he /* map AC97 PCM playback to DMA Channel 0 */ 1151 1.4.2.2 he /* Reset FEN bit to setup first */ 1152 1.4.2.2 he BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc,CS4281_FCR0) & ~FCRn_FEN)); 1153 1.4.2.2 he /* 1154 1.4.2.2 he *| RS[4:0]/| | 1155 1.4.2.2 he *| LS[4:0] | AC97 | Slot Function 1156 1.4.2.2 he *|---------+--------+-------------------- 1157 1.4.2.2 he *| 0 | 3 | Left PCM Playback 1158 1.4.2.2 he *| 1 | 4 | Right PCM Playback 1159 1.4.2.2 he *| 2 | 5 | Phone Line 1 DAC 1160 1.4.2.2 he *| 3 | 6 | Center PCM Playback 1161 1.4.2.2 he *.... 1162 1.4.2.2 he * quoted from Table 29(p109) 1163 1.4.2.2 he */ 1164 1.4.2.2 he dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1165 1.4.2.2 he 0x00 << 16 | /* LS[4:0] = 0 see above */ 1166 1.4.2.2 he 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1167 1.4.2.2 he 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1168 1.4.2.2 he BA0WRITE4(sc, CS4281_FCR0, dat32); 1169 1.4.2.2 he BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1170 1.4.2.2 he 1171 1.4.2.2 he /* map AC97 PCM record to DMA Channel 1 */ 1172 1.4.2.2 he /* Reset FEN bit to setup first */ 1173 1.4.2.2 he BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc,CS4281_FCR1) & ~FCRn_FEN)); 1174 1.4.2.2 he /* 1175 1.4.2.2 he *| RS[4:0]/| 1176 1.4.2.2 he *| LS[4:0] | AC97 | Slot Function 1177 1.4.2.2 he *|---------+------+------------------- 1178 1.4.2.2 he *| 10 | 3 | Left PCM Record 1179 1.4.2.2 he *| 11 | 4 | Right PCM Record 1180 1.4.2.2 he *| 12 | 5 | Phone Line 1 ADC 1181 1.4.2.2 he *| 13 | 6 | Mic ADC 1182 1.4.2.2 he *.... 1183 1.4.2.2 he * quoted from Table 30(p109) 1184 1.4.2.2 he */ 1185 1.4.2.2 he dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1186 1.4.2.2 he 0x0a << 16 | /* LS[4:0] = 10 See above */ 1187 1.4.2.2 he 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1188 1.4.2.2 he 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1189 1.4.2.2 he 1190 1.4.2.2 he /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1191 1.4.2.2 he BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1192 1.4.2.2 he BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1193 1.4.2.2 he 1194 1.4.2.2 he #if 0 1195 1.4.2.2 he /* Disable DMA Channel 2, 3 */ 1196 1.4.2.2 he BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc,CS4281_FCR2) & ~FCRn_FEN)); 1197 1.4.2.2 he BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc,CS4281_FCR3) & ~FCRn_FEN)); 1198 1.4.2.2 he #endif 1199 1.4.2.2 he 1200 1.4.2.2 he /* Set the SRC Slot Assignment accordingly */ 1201 1.4.2.2 he /*| PLSS[4:0]/ 1202 1.4.2.2 he *| PRSS[4:0] | AC97 | Slot Function 1203 1.4.2.2 he *|-----------+------+---------------- 1204 1.4.2.2 he *| 0 | 3 | Left PCM Playback 1205 1.4.2.2 he *| 1 | 4 | Right PCM Playback 1206 1.4.2.2 he *| 2 | 5 | phone line 1 DAC 1207 1.4.2.2 he *| 3 | 6 | Center PCM Playback 1208 1.4.2.2 he *| 4 | 7 | Left Surround PCM Playback 1209 1.4.2.2 he *| 5 | 8 | Right Surround PCM Playback 1210 1.4.2.2 he *...... 1211 1.4.2.2 he * 1212 1.4.2.2 he *| CLSS[4:0]/ 1213 1.4.2.2 he *| CRSS[4:0] | AC97 | Codec |Slot Function 1214 1.4.2.2 he *|-----------+------+-------+----------------- 1215 1.4.2.2 he *| 10 | 3 |Primary| Left PCM Record 1216 1.4.2.2 he *| 11 | 4 |Primary| Right PCM Record 1217 1.4.2.2 he *| 12 | 5 |Primary| Phone Line 1 ADC 1218 1.4.2.2 he *| 13 | 6 |Primary| Mic ADC 1219 1.4.2.2 he *|..... 1220 1.4.2.2 he *| 20 | 3 | Sec. | Left PCM Record 1221 1.4.2.2 he *| 21 | 4 | Sec. | Right PCM Record 1222 1.4.2.2 he *| 22 | 5 | Sec. | Phone Line 1 ADC 1223 1.4.2.2 he *| 23 | 6 | Sec. | Mic ADC 1224 1.4.2.2 he */ 1225 1.4.2.2 he dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1226 1.4.2.2 he 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1227 1.4.2.2 he 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1228 1.4.2.2 he 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1229 1.4.2.2 he BA0WRITE4(sc, CS4281_SRCSA, dat32); 1230 1.4.2.2 he 1231 1.4.2.2 he /* Set interrupt to occured at Half and Full terminal 1232 1.4.2.2 he * count interrupt enable for DMA channel 0 and 1. 1233 1.4.2.2 he * To keep DMA stop, set MSK. 1234 1.4.2.2 he */ 1235 1.4.2.2 he dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1236 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR0, dat32); 1237 1.4.2.2 he BA0WRITE4(sc, CS4281_DCR1, dat32); 1238 1.4.2.2 he 1239 1.4.2.2 he /* Set Auto-Initialize Contorl enable */ 1240 1.4.2.2 he BA0WRITE4(sc, CS4281_DMR0, 1241 1.4.2.2 he DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1242 1.4.2.2 he BA0WRITE4(sc, CS4281_DMR1, 1243 1.4.2.2 he DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1244 1.4.2.2 he 1245 1.4.2.2 he /* Clear DMA Mask in HIMR */ 1246 1.4.2.2 he dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1247 1.4.2.2 he BA0WRITE4(sc, CS4281_HIMR, 1248 1.4.2.2 he BA0READ4(sc, CS4281_HIMR) & dat32); 1249 1.4.2.2 he 1250 1.4.2.2 he /* set current status */ 1251 1.4.2.2 he if (init != 0) { 1252 1.4.2.2 he sc->sc_prun = 0; 1253 1.4.2.2 he sc->sc_rrun = 0; 1254 1.4.2.2 he } 1255 1.4.2.2 he 1256 1.4.2.2 he /* setup playback volume */ 1257 1.4.2.2 he BA0WRITE4(sc, CS4281_PPRVC, 7); 1258 1.4.2.2 he BA0WRITE4(sc, CS4281_PPLVC, 7); 1259 1.4.2.2 he 1260 1.4.2.2 he return 0; 1261 1.4.2.2 he } 1262
Indexes created Thu Oct 02 14:10:14 GMT 2025