cs4281.c revision 1.1
1 /* $NetBSD: cs4281.c,v 1.1 2001/01/22 01:34:42 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: confirm this driver does work :-) 41 * 2: midi and FM support 42 * 3: ... 43 * 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/fcntl.h> 51 #include <sys/device.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include <dev/pci/pcidevs.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/cs4281reg.h> 58 #include <dev/pci/cs428xreg.h> 59 60 #include <sys/audioio.h> 61 #include <dev/audio_if.h> 62 #include <dev/midi_if.h> 63 #include <dev/mulaw.h> 64 #include <dev/auconv.h> 65 66 #include <dev/ic/ac97reg.h> 67 #include <dev/ic/ac97var.h> 68 69 #include <dev/pci/cs428x.h> 70 71 #include <machine/bus.h> 72 73 #if defined(ENABLE_SECONDARY_CODEC) 74 #define MAX_CHANNELS (4) 75 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 76 #else 77 #define MAX_CHANNELS (2) 78 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 79 #endif 80 81 /* XXX: now this is required only to support NetBSD-1.5.... */ 82 #ifndef PCI_PRODUCT_CIRRUS_CS4281 83 #define PCI_PRODUCT_CIRRUS_CS4281 (0x6005) 84 #endif 85 86 /* IF functions for audio driver */ 87 int cs4281_match(struct device *, struct cfdata *, void *); 88 void cs4281_attach(struct device *, struct device *, void *); 89 int cs4281_intr(void *); 90 int cs4281_query_encoding(void *, struct audio_encoding *); 91 int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 92 int cs4281_halt_output(void *); 93 int cs4281_halt_input(void *); 94 int cs4281_getdev(void *, struct audio_device *); 95 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 96 void *, struct audio_params *); 97 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 98 void *, struct audio_params *); 99 100 /* Internal functions */ 101 u_int8_t cs4281_sr2regval(int); 102 void cs4281_set_dac_rate(struct cs428x_softc *, int ); 103 void cs4281_set_adc_rate(struct cs428x_softc *, int ); 104 int cs4281_init(struct cs428x_softc *); 105 106 /* Power Management */ 107 void cs4281_power __P((int, void *)); 108 109 #define NOT_SHARED 110 111 #ifdef NOT_SHARED 112 /* These functions may shared with cs4280.c */ 113 int cs4281_open(void *, int); 114 void cs4281_close(void *); 115 int cs4281_round_blocksize(void *, int); 116 int cs4281_get_props(void *); 117 int cs4281_attach_codec(void *, struct ac97_codec_if *); 118 int cs4281_read_codec(void *, u_int8_t , u_int16_t *); 119 int cs4281_write_codec(void *, u_int8_t, u_int16_t); 120 void cs4281_reset_codec(void *); 121 122 int cs4281_mixer_set_port(void *, mixer_ctrl_t *); 123 int cs4281_mixer_get_port(void *, mixer_ctrl_t *); 124 int cs4281_query_devinfo(void *, mixer_devinfo_t *); 125 void *cs4281_malloc(void *, int, size_t, int, int); 126 size_t cs4281_round_buffersize(void *, int, size_t); 127 void cs4281_free(void *, void *, int); 128 paddr_t cs4281_mappage(void *, void *, off_t, int); 129 130 /* internal functions */ 131 int cs4281_allocmem(struct cs428x_softc*, size_t, int, int, struct cs428x_dma *); 132 int cs4281_src_wait(struct cs428x_softc *); 133 134 #if defined(CS4281_DEBUG) 135 #undef DPRINTF 136 #undef DPRINTFN 137 #define DPRINTF(x) if (cs4281_debug) printf x 138 #define DPRINTFN(n,x) if (cs4281_debug>(n)) printf x 139 int cs4281_debug = 5; 140 #endif 141 142 #endif /* NOT_SHARED */ 143 144 struct audio_hw_if cs4281_hw_if = { 145 cs4281_open, 146 cs4281_close, 147 NULL, 148 cs4281_query_encoding, 149 cs4281_set_params, 150 cs4281_round_blocksize, 151 NULL, 152 NULL, 153 NULL, 154 NULL, 155 NULL, 156 cs4281_halt_output, 157 cs4281_halt_input, 158 NULL, 159 cs4281_getdev, 160 NULL, 161 cs4281_mixer_set_port, 162 cs4281_mixer_get_port, 163 cs4281_query_devinfo, 164 cs4281_malloc, 165 cs4281_free, 166 cs4281_round_buffersize, 167 cs4281_mappage, 168 cs4281_get_props, 169 cs4281_trigger_output, 170 cs4281_trigger_input, 171 }; 172 173 #if NMIDI > 0 174 /* Midi Interface */ 175 void cs4281_midi_close(void*); 176 void cs4281_midi_getinfo(void *, struct midi_info *); 177 int cs4281_midi_open(void *, int, void (*)(void *, int), 178 void (*)(void *), void *); 179 int cs4281_midi_output(void *, int); 180 181 struct midi_hw_if cs4281_midi_hw_if = { 182 cs4281_midi_open, 183 cs4281_midi_close, 184 cs4281_midi_output, 185 cs4281_midi_getinfo, 186 0, 187 }; 188 #endif 189 190 struct cfattach clct_ca = { 191 sizeof(struct cs428x_softc), cs4281_match, cs4281_attach 192 }; 193 194 struct audio_device cs4281_device = { 195 "CS4281", 196 "", 197 "cs4281" 198 }; 199 200 201 /* trivial */ 202 int 203 cs4281_match(parent, match, aux) 204 struct device *parent; 205 struct cfdata *match; 206 void *aux; 207 { 208 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 209 210 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 211 return 0; 212 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 213 return 1; 214 return 0; 215 } 216 217 /* It seems to work */ 218 void 219 cs4281_attach(parent, self, aux) 220 struct device *parent; 221 struct device *self; 222 void *aux; 223 { 224 struct cs428x_softc *sc = (struct cs428x_softc *)self; 225 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 226 pci_chipset_tag_t pc = pa->pa_pc; 227 char const *intrstr; 228 pci_intr_handle_t ih; 229 pcireg_t csr; 230 char devinfo[256]; 231 232 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 233 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 234 235 /* Map I/O register */ 236 if (pci_mapreg_map(pa, PCI_BA0, 237 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 238 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 239 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 240 return; 241 } 242 if (pci_mapreg_map(pa, PCI_BA1, 243 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 244 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 245 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 246 return; 247 } 248 249 sc->sc_dmatag = pa->pa_dmat; 250 251 /* Enable the device (set bus master flag) */ 252 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 253 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 254 csr | PCI_COMMAND_MASTER_ENABLE); 255 256 #if 0 257 /* LATENCY_TIMER setting */ 258 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 259 if ( PCI_LATTIMER(temp1) < 32 ) { 260 temp1 &= 0xffff00ff; 261 temp1 |= 0x00002000; 262 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 263 } 264 #endif 265 266 /* Map and establish the interrupt. */ 267 #if 1 268 if (pci_intr_map(pa, &ih)) { 269 #else /* old */ 270 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 271 pa->pa_intrline, &ih)) { 272 #endif 273 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 274 return; 275 } 276 intrstr = pci_intr_string(pc, ih); 277 278 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 279 if (sc->sc_ih == NULL) { 280 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 281 if (intrstr != NULL) 282 printf(" at %s", intrstr); 283 printf("\n"); 284 return; 285 } 286 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 287 288 /* 289 * Sound System start-up 290 */ 291 if (cs4281_init(sc) != 0) 292 return; 293 294 sc->type = TYPE_CS4281; 295 sc->halt_input = cs4281_halt_input; 296 sc->halt_output = cs4281_halt_output; 297 298 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 299 sc->dma_align = 0x10; 300 sc->hw_blocksize = sc->dma_size / 2; 301 302 /* AC 97 attachment */ 303 sc->host_if.arg = sc; 304 sc->host_if.attach = cs4281_attach_codec; 305 sc->host_if.read = cs4281_read_codec; 306 sc->host_if.write = cs4281_write_codec; 307 sc->host_if.reset = cs4281_reset_codec; 308 if (ac97_attach(&sc->host_if) != 0) { 309 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 310 return; 311 } 312 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 313 314 #if NMIDI > 0 315 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 316 #endif 317 318 sc->sc_suspend = PWR_RESUME; 319 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 320 } 321 322 323 int 324 cs4281_intr(p) 325 void *p; 326 { 327 struct cs428x_softc *sc = p; 328 u_int32_t intr, hdsr0, hdsr1; 329 char *empty_dma; 330 331 hdsr0 = 0; 332 hdsr1 = 0; 333 334 /* grab interrupt register */ 335 intr = BA0READ4(sc, CS4281_HISR); 336 337 DPRINTF(("cs4281_intr:")); 338 /* not for me */ 339 if ((intr & HISR_INTENA) == 0) { 340 /* clear the interrupt register */ 341 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 342 return 0; 343 } 344 345 if (intr & HISR_DMA0) 346 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 347 if (intr & HISR_DMA1) 348 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 349 /* clear the interrupt register */ 350 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 351 352 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 353 intr, hdsr0, hdsr1)); 354 355 /* Playback Interrupt */ 356 if (intr & HISR_DMA0) { 357 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 358 (int)BA0READ4(sc, CS4281_DCC0))); 359 if (sc->sc_pintr) { 360 if ((sc->sc_pi%sc->sc_pcount) == 0) 361 sc->sc_pintr(sc->sc_parg); 362 } else { 363 printf("unexpected play intr\n"); 364 } 365 /* copy buffer */ 366 ++sc->sc_pi; 367 empty_dma = sc->sc_pdma->addr; 368 if (sc->sc_pi&1) 369 empty_dma += sc->hw_blocksize; 370 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 371 sc->sc_pn += sc->hw_blocksize; 372 if (sc->sc_pn >= sc->sc_pe) 373 sc->sc_pn = sc->sc_ps; 374 } 375 if (intr & HISR_DMA1) { 376 /* copy from dma */ 377 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 378 (int)BA0READ4(sc, CS4281_DCC1))); 379 ++sc->sc_ri; 380 empty_dma = sc->sc_rdma->addr; 381 if ((sc->sc_ri & 1) == 0) 382 empty_dma += sc->hw_blocksize; 383 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 384 if (sc->sc_rn >= sc->sc_re) 385 sc->sc_rn = sc->sc_rs; 386 if (sc->sc_rintr) { 387 if ((sc->sc_ri % sc->sc_rcount) == 0) 388 sc->sc_rintr(sc->sc_rarg); 389 } else { 390 printf("unexpected record intr\n"); 391 } 392 } 393 DPRINTF(("\n")); 394 return 1; 395 } 396 397 int 398 cs4281_query_encoding(addr, fp) 399 void *addr; 400 struct audio_encoding *fp; 401 { 402 switch (fp->index) { 403 case 0: 404 strcpy(fp->name, AudioEulinear); 405 fp->encoding = AUDIO_ENCODING_ULINEAR; 406 fp->precision = 8; 407 fp->flags = 0; 408 break; 409 case 1: 410 strcpy(fp->name, AudioEmulaw); 411 fp->encoding = AUDIO_ENCODING_ULAW; 412 fp->precision = 8; 413 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 414 break; 415 case 2: 416 strcpy(fp->name, AudioEalaw); 417 fp->encoding = AUDIO_ENCODING_ALAW; 418 fp->precision = 8; 419 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 420 break; 421 case 3: 422 strcpy(fp->name, AudioEslinear); 423 fp->encoding = AUDIO_ENCODING_SLINEAR; 424 fp->precision = 8; 425 fp->flags = 0; 426 break; 427 case 4: 428 strcpy(fp->name, AudioEslinear_le); 429 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 430 fp->precision = 16; 431 fp->flags = 0; 432 break; 433 case 5: 434 strcpy(fp->name, AudioEulinear_le); 435 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 436 fp->precision = 16; 437 fp->flags = 0; 438 break; 439 case 6: 440 strcpy(fp->name, AudioEslinear_be); 441 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 442 fp->precision = 16; 443 fp->flags = 0; 444 break; 445 case 7: 446 strcpy(fp->name, AudioEulinear_be); 447 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 448 fp->precision = 16; 449 fp->flags = 0; 450 break; 451 default: 452 return EINVAL; 453 } 454 return 0; 455 } 456 457 int 458 cs4281_set_params(addr, setmode, usemode, play, rec) 459 void *addr; 460 int setmode, usemode; 461 struct audio_params *play, *rec; 462 { 463 struct cs428x_softc *sc = addr; 464 struct audio_params *p; 465 int mode; 466 467 for (mode = AUMODE_RECORD; mode != -1; 468 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 469 if ((setmode & mode) == 0) 470 continue; 471 472 p = mode == AUMODE_PLAY ? play : rec; 473 474 if (p == play) { 475 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 476 p->sample_rate, p->precision, p->channels)); 477 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 478 (p->precision != 8 && p->precision != 16) || 479 (p->channels != 1 && p->channels != 2)) { 480 return (EINVAL); 481 } 482 } else { 483 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 484 p->sample_rate, p->precision, p->channels)); 485 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 486 (p->precision != 8 && p->precision != 16) || 487 (p->channels != 1 && p->channels != 2)) { 488 return (EINVAL); 489 } 490 } 491 p->factor = 1; 492 p->sw_code = 0; 493 494 switch (p->encoding) { 495 case AUDIO_ENCODING_SLINEAR_BE: 496 break; 497 case AUDIO_ENCODING_SLINEAR_LE: 498 break; 499 case AUDIO_ENCODING_ULINEAR_BE: 500 break; 501 case AUDIO_ENCODING_ULINEAR_LE: 502 break; 503 case AUDIO_ENCODING_ULAW: 504 if (mode == AUMODE_PLAY) { 505 p->sw_code = mulaw_to_slinear8; 506 } else { 507 p->sw_code = slinear8_to_mulaw; 508 } 509 break; 510 case AUDIO_ENCODING_ALAW: 511 if (mode == AUMODE_PLAY) { 512 p->sw_code = alaw_to_slinear8; 513 } else { 514 p->sw_code = slinear8_to_alaw; 515 } 516 break; 517 default: 518 return (EINVAL); 519 } 520 } 521 522 /* set sample rate */ 523 cs4281_set_dac_rate(sc, play->sample_rate); 524 cs4281_set_adc_rate(sc, rec->sample_rate); 525 return 0; 526 } 527 528 /* Confirmed 2000/12/26 */ 529 int 530 cs4281_halt_output(addr) 531 void *addr; 532 { 533 struct cs428x_softc *sc = addr; 534 535 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 536 #ifdef DIAGNOSTIC 537 sc->sc_prun = 0; 538 #endif 539 return 0; 540 } 541 542 /* Confirmed 2000/12/26 */ 543 int 544 cs4281_halt_input(addr) 545 void *addr; 546 { 547 struct cs428x_softc *sc = addr; 548 549 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 550 #ifdef DIAGNOSTIC 551 sc->sc_rrun = 0; 552 #endif 553 return 0; 554 } 555 556 /* trivial */ 557 int 558 cs4281_getdev(addr, retp) 559 void *addr; 560 struct audio_device *retp; 561 { 562 *retp = cs4281_device; 563 return 0; 564 } 565 566 567 int 568 cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 569 void *addr; 570 void *start, *end; 571 int blksize; 572 void (*intr) __P((void *)); 573 void *arg; 574 struct audio_params *param; 575 { 576 struct cs428x_softc *sc = addr; 577 u_int32_t fmt=0; 578 struct cs428x_dma *p; 579 int dma_count; 580 581 #ifdef DIAGNOSTIC 582 if (sc->sc_prun) 583 printf("cs4281_trigger_output: already running\n"); 584 sc->sc_prun = 1; 585 #endif 586 587 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 588 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 589 sc->sc_pintr = intr; 590 sc->sc_parg = arg; 591 592 /* stop playback DMA */ 593 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 594 595 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 596 param->precision, param->factor, param->channels, 597 param->encoding)); 598 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 599 ; 600 if (p == NULL) { 601 printf("cs4281_trigger_output: bad addr %p\n", start); 602 return (EINVAL); 603 } 604 605 sc->sc_pcount = blksize / sc->hw_blocksize; 606 sc->sc_ps = (char *)start; 607 sc->sc_pe = (char *)end; 608 sc->sc_pdma = p; 609 sc->sc_pbuf = KERNADDR(p); 610 sc->sc_pi = 0; 611 sc->sc_pn = sc->sc_ps; 612 if (blksize >= sc->dma_size) { 613 sc->sc_pn = sc->sc_ps + sc->dma_size; 614 memcpy(sc->sc_pbuf, start, sc->dma_size); 615 ++sc->sc_pi; 616 } else { 617 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 618 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 619 } 620 621 dma_count = sc->dma_size; 622 if (param->precision * param->factor != 8) 623 dma_count /= 2; /* 16 bit */ 624 if (param->channels > 1) 625 dma_count /= 2; /* Stereo */ 626 627 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 628 (int)DMAADDR(p), dma_count)); 629 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 630 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 631 632 /* set playback format */ 633 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 634 if (param->precision * param->factor == 8) 635 fmt |= DMRn_SIZE8; 636 if (param->channels == 1) 637 fmt |= DMRn_MONO; 638 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 639 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 640 fmt |= DMRn_BEND; 641 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 642 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 643 fmt |= DMRn_USIGN; 644 BA0WRITE4(sc, CS4281_DMR0, fmt); 645 646 /* set sample rate */ 647 cs4281_set_dac_rate(sc, param->sample_rate); 648 649 /* start DMA */ 650 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 651 /* Enable interrupts */ 652 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 653 654 #if 1 655 /* XXX 656 * I think these BA0WRITE4 should not be here 657 */ 658 BA0WRITE4(sc, CS4281_PPRVC, 7); 659 BA0WRITE4(sc, CS4281_PPLVC, 7); 660 #endif 661 662 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 663 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 664 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 665 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 666 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 667 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 668 BA0READ4(sc, CS4281_DACSR))); 669 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 670 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 671 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 672 673 return 0; 674 } 675 676 int 677 cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 678 void *addr; 679 void *start, *end; 680 int blksize; 681 void (*intr) __P((void *)); 682 void *arg; 683 struct audio_params *param; 684 { 685 struct cs428x_softc *sc = addr; 686 struct cs428x_dma *p; 687 u_int32_t fmt=0; 688 int dma_count; 689 690 printf("cs4281_trigger_input: not implemented yet\n"); 691 #ifdef DIAGNOSTIC 692 if (sc->sc_rrun) 693 printf("cs4281_trigger_input: already running\n"); 694 sc->sc_rrun = 1; 695 #endif 696 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 697 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 698 sc->sc_rintr = intr; 699 sc->sc_rarg = arg; 700 701 /* stop recording DMA */ 702 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 703 704 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 705 ; 706 if (!p) { 707 printf("cs4281_trigger_input: bad addr %p\n", start); 708 return (EINVAL); 709 } 710 711 sc->sc_rcount = blksize / sc->hw_blocksize; 712 sc->sc_rs = (char *)start; 713 sc->sc_re = (char *)end; 714 sc->sc_rdma = p; 715 sc->sc_rbuf = KERNADDR(p); 716 sc->sc_ri = 0; 717 sc->sc_rn = sc->sc_rs; 718 719 dma_count = sc->dma_size; 720 if (param->precision * param->factor == 8) 721 dma_count /= 2; 722 if (param->channels > 1) 723 dma_count /= 2; 724 725 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 726 (int)DMAADDR(p), dma_count)); 727 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 728 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 729 730 /* set recording format */ 731 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 732 if (param->precision * param->factor == 8) 733 fmt |= DMRn_SIZE8; 734 if (param->channels == 1) 735 fmt |= DMRn_MONO; 736 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 737 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 738 fmt |= DMRn_BEND; 739 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 740 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 741 fmt |= DMRn_USIGN; 742 BA0WRITE4(sc, CS4281_DMR1, fmt); 743 744 /* set sample rate */ 745 cs4281_set_adc_rate(sc, param->sample_rate); 746 747 /* Start DMA */ 748 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 749 /* Enable interrupts */ 750 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 751 752 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 753 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 754 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 755 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 756 757 return 0; 758 } 759 760 /* convert sample rate to register value */ 761 /* Confirmed 2000/12/26 */ 762 u_int8_t 763 cs4281_sr2regval(rate) 764 int rate; 765 { 766 u_int8_t retval; 767 768 /* We don't have to change here. but anyway ... */ 769 if (rate > 48000) 770 rate = 48000; 771 if (rate < 6023) 772 rate = 6023; 773 774 switch (rate) { 775 case 8000: 776 retval = 5; 777 break; 778 case 11025: 779 retval = 4; 780 break; 781 case 16000: 782 retval = 3; 783 break; 784 case 22050: 785 retval = 2; 786 break; 787 case 44100: 788 retval = 1; 789 break; 790 case 48000: 791 retval = 0; 792 break; 793 default: 794 retval = 1536000/rate; /* == 24576000/(rate*16) */ 795 } 796 return retval; 797 } 798 799 800 /* Confirmed 2000/12/26 */ 801 void 802 cs4281_set_dac_rate(sc, rate) 803 struct cs428x_softc *sc; 804 int rate; 805 { 806 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 807 } 808 809 /* Confirmed 2000/12/26 */ 810 void 811 cs4281_set_adc_rate(sc, rate) 812 struct cs428x_softc *sc; 813 int rate; 814 { 815 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 816 } 817 818 /* Confirmed 2000/12/26 */ 819 int 820 cs4281_init(sc) 821 struct cs428x_softc *sc; 822 { 823 int n; 824 u_int16_t data; 825 u_int32_t dat32; 826 827 /* set "Configuration Write Protect" register to 828 * 0x4281 to allow to write */ 829 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 830 831 /* Start PLL out in known state */ 832 BA0WRITE4(sc, CS4281_CLKCR1, 0); 833 /* Start serial ports out in known state */ 834 BA0WRITE4(sc, CS4281_SERMC, 0); 835 836 /* Reset codec */ 837 BA0WRITE4(sc, CS428X_ACCTL, 0); 838 delay(50); /* delay 50us */ 839 840 BA0WRITE4(sc, CS4281_SPMC, 0); 841 delay(100); /* delay 100us */ 842 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 843 #if defined(ENABLE_SECONDARY_CODEC) 844 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 845 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 846 #endif 847 delay(50000); /* XXX: delay 50ms */ 848 849 /* Turn on Sound System clocks based on ABITCLK */ 850 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 851 delay(50000); /* XXX: delay 50ms */ 852 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 853 854 /* Set enables for sections that are needed in the SSPM registers */ 855 BA0WRITE4(sc, CS4281_SSPM, 856 SSPM_MIXEN | /* Mixer */ 857 SSPM_CSRCEN | /* Capture SRC */ 858 SSPM_PSRCEN | /* Playback SRC */ 859 SSPM_JSEN | /* Joystick */ 860 SSPM_ACLEN | /* AC LINK */ 861 SSPM_FMEN /* FM */ 862 ); 863 864 /* Wait for clock stabilization */ 865 n = 0; 866 #if 1 867 /* what document says */ 868 while ( ( BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 869 != (CLKCR1_DLLRDY | CLKCR1_CLKON )) { 870 delay(100); 871 if ( ++n > 1000 ) 872 return -1; 873 } 874 #else 875 /* Cirrus driver for Linux does */ 876 while ( !(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 877 delay(1000); 878 if ( ++n > 1000 ) 879 return -1; 880 } 881 #endif 882 883 /* Enable ASYNC generation */ 884 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 885 886 /* Wait for Codec ready. Linux driver wait 50ms here */ 887 n = 0; 888 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 889 delay(100); 890 if (++n > 1000) 891 return -1; 892 } 893 894 #if defined(ENABLE_SECONDARY_CODEC) 895 /* secondary codec ready*/ 896 n = 0; 897 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 898 delay(100); 899 if (++n > 1000) 900 return -1; 901 } 902 #endif 903 904 /* Set the serial timing configuration */ 905 /* XXX: undocumented but the Linux driver do this */ 906 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 907 908 /* Wait for Codec ready signal */ 909 n = 0; 910 do { 911 delay(1000); 912 if (++n > 1000) { 913 printf("%s: Timeout waiting for Codec ready\n", 914 sc->sc_dev.dv_xname); 915 return -1; 916 } 917 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 918 } while (dat32 == 0); 919 920 /* Enable Valid Frame output on ASDOUT */ 921 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 922 923 /* Wait until Codec Calibration is finished. Codec register 26h */ 924 n = 0; 925 do { 926 delay(1); 927 if (++n > 1000) { 928 printf("%s: Timeout waiting for Codec calibration\n", 929 sc->sc_dev.dv_xname); 930 return -1; 931 } 932 cs4281_read_codec(sc, AC97_REG_POWER, &data); 933 } while ((data & 0x0f) != 0x0f); 934 935 /* Set the serial timing configuration again */ 936 /* XXX: undocumented but the Linux driver do this */ 937 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 938 939 /* Wait until we've sampled input slots 3 & 4 as valid */ 940 n = 0; 941 do { 942 delay(1000); 943 if (++n > 1000) { 944 printf("%s: Timeout waiting for sampled input slots as valid\n", 945 sc->sc_dev.dv_xname); 946 return -1; 947 } 948 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 949 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 950 951 /* Start digital data transfer of audio data to the codec */ 952 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 953 954 cs4281_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 955 cs4281_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 956 957 /* Power on the DAC */ 958 cs4281_read_codec(sc, AC97_REG_POWER, &data); 959 cs4281_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 960 961 /* Wait until we sample a DAC ready state. 962 * Not documented, but Linux driver does. 963 */ 964 for (n = 0; n < 32; ++n) { 965 delay(1000); 966 cs4281_read_codec(sc, AC97_REG_POWER, &data); 967 if (data & 0x02) 968 break; 969 } 970 971 /* Power on the ADC */ 972 cs4281_read_codec(sc, AC97_REG_POWER, &data); 973 cs4281_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 974 975 /* Wait until we sample ADC ready state. 976 * Not documented, but Linux driver does. 977 */ 978 for (n = 0; n < 32; ++n) { 979 delay(1000); 980 cs4281_read_codec(sc, AC97_REG_POWER, &data); 981 if (data & 0x01) 982 break; 983 } 984 985 #if 0 986 /* Initialize AC-Link features */ 987 /* variable sample-rate support */ 988 mem = BA0READ4(sc, CS4281_SERMC); 989 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 990 BA0WRITE4(sc, CS4281_SERMC, mem); 991 /* XXX: more... */ 992 993 /* Initialize SSCR register features */ 994 /* XXX: hardware volume setting */ 995 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 996 #endif 997 998 /* disable Sound Blaster Pro emulation */ 999 /* XXX: 1000 * Cannot set since the documents does not describe which bit is 1001 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1002 * we can ignore it.*/ 1003 #if 0 1004 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1005 #endif 1006 1007 /* map AC97 PCM playback to DMA Channel 0 */ 1008 /* Reset FEN bit to setup first */ 1009 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc,CS4281_FCR0) & ~FCRn_FEN)); 1010 /* 1011 *| RS[4:0]/| | 1012 *| LS[4:0] | AC97 | Slot Function 1013 *|---------+--------+-------------------- 1014 *| 0 | 3 | Left PCM Playback 1015 *| 1 | 4 | Right PCM Playback 1016 *| 2 | 5 | Phone Line 1 DAC 1017 *| 3 | 6 | Center PCM Playback 1018 *.... 1019 * quoted from Table 29(p109) 1020 */ 1021 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1022 0x00 << 16 | /* LS[4:0] = 0 see above */ 1023 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1024 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1025 BA0WRITE4(sc, CS4281_FCR0, dat32); 1026 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1027 1028 /* map AC97 PCM record to DMA Channel 1 */ 1029 /* Reset FEN bit to setup first */ 1030 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc,CS4281_FCR1) & ~FCRn_FEN)); 1031 /* 1032 *| RS[4:0]/| 1033 *| LS[4:0] | AC97 | Slot Function 1034 *|---------+------+------------------- 1035 *| 10 | 3 | Left PCM Record 1036 *| 11 | 4 | Right PCM Record 1037 *| 12 | 5 | Phone Line 1 ADC 1038 *| 13 | 6 | Mic ADC 1039 *.... 1040 * quoted from Table 30(p109) 1041 */ 1042 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1043 0x0a << 16 | /* LS[4:0] = 10 See above */ 1044 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1045 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1046 1047 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1048 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1049 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1050 1051 #if 0 1052 /* Disable DMA Channel 2, 3 */ 1053 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc,CS4281_FCR2) & ~FCRn_FEN)); 1054 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc,CS4281_FCR3) & ~FCRn_FEN)); 1055 #endif 1056 1057 /* Set the SRC Slot Assignment accordingly */ 1058 /*| PLSS[4:0]/ 1059 *| PRSS[4:0] | AC97 | Slot Function 1060 *|-----------+------+---------------- 1061 *| 0 | 3 | Left PCM Playback 1062 *| 1 | 4 | Right PCM Playback 1063 *| 2 | 5 | phone line 1 DAC 1064 *| 3 | 6 | Center PCM Playback 1065 *| 4 | 7 | Left Surround PCM Playback 1066 *| 5 | 8 | Right Surround PCM Playback 1067 *...... 1068 * 1069 *| CLSS[4:0]/ 1070 *| CRSS[4:0] | AC97 | Codec |Slot Function 1071 *|-----------+------+-------+----------------- 1072 *| 10 | 3 |Primary| Left PCM Record 1073 *| 11 | 4 |Primary| Right PCM Record 1074 *| 12 | 5 |Primary| Phone Line 1 ADC 1075 *| 13 | 6 |Primary| Mic ADC 1076 *|..... 1077 *| 20 | 3 | Sec. | Left PCM Record 1078 *| 21 | 4 | Sec. | Right PCM Record 1079 *| 22 | 5 | Sec. | Phone Line 1 ADC 1080 *| 23 | 6 | Sec. | Mic ADC 1081 */ 1082 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1083 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1084 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1085 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1086 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1087 1088 /* Set interrupt to occured at Half and Full terminal 1089 * count interrupt enable for DMA channel 0 and 1. 1090 * To keep DMA stop, set MSK. 1091 */ 1092 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1093 BA0WRITE4(sc, CS4281_DCR0, dat32); 1094 BA0WRITE4(sc, CS4281_DCR1, dat32); 1095 1096 /* Set Auto-Initialize Contorl enable */ 1097 BA0WRITE4(sc, CS4281_DMR0, 1098 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1099 BA0WRITE4(sc, CS4281_DMR1, 1100 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1101 1102 /* Clear DMA Mask in HIMR */ 1103 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1104 BA0WRITE4(sc, CS4281_HIMR, 1105 BA0READ4(sc, CS4281_HIMR) & dat32); 1106 return 0; 1107 } 1108 1109 void 1110 cs4281_power(why, v) 1111 int why; 1112 void *v; 1113 { 1114 struct cs428x_softc *sc = (struct cs428x_softc *)v; 1115 1116 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 1117 switch (why) { 1118 case PWR_SUSPEND: 1119 case PWR_STANDBY: 1120 sc->sc_suspend = why; 1121 1122 cs4281_halt_output(sc); 1123 cs4281_halt_input(sc); 1124 /* should I powerdown here ? */ 1125 cs4281_write_codec(sc, AC97_REG_POWER, CS4281_POWER_DOWN_ALL); 1126 break; 1127 case PWR_RESUME: 1128 if (sc->sc_suspend == PWR_RESUME) { 1129 printf("cs4281_power: odd, resume without suspend.\n"); 1130 sc->sc_suspend = why; 1131 return; 1132 } 1133 sc->sc_suspend = why; 1134 cs4281_init(sc); 1135 cs4281_reset_codec(sc); 1136 1137 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1138 break; 1139 case PWR_SOFTSUSPEND: 1140 case PWR_SOFTSTANDBY: 1141 case PWR_SOFTRESUME: 1142 break; 1143 } 1144 } 1145 1146 void 1147 cs4281_reset_codec(void *addr) 1148 { 1149 struct cs428x_softc *sc; 1150 u_int16_t data; 1151 u_int32_t dat32; 1152 int n; 1153 1154 sc = addr; 1155 1156 DPRINTFN(3,("cs4281_reset_codec\n")); 1157 1158 /* Reset codec */ 1159 BA0WRITE4(sc, CS428X_ACCTL, 0); 1160 delay(50); /* delay 50us */ 1161 1162 BA0WRITE4(sc, CS4281_SPMC, 0); 1163 delay(100); /* delay 100us */ 1164 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 1165 #if defined(ENABLE_SECONDARY_CODEC) 1166 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 1167 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 1168 #endif 1169 delay(50000); /* XXX: delay 50ms */ 1170 1171 /* Enable ASYNC generation */ 1172 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1173 1174 /* Wait for Codec ready. Linux driver wait 50ms here */ 1175 n = 0; 1176 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1177 delay(100); 1178 if (++n > 1000) { 1179 printf("reset_codec: AC97 codec ready timeout\n"); 1180 return; 1181 } 1182 } 1183 #if defined(ENABLE_SECONDARY_CODEC) 1184 /* secondary codec ready*/ 1185 n = 0; 1186 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1187 delay(100); 1188 if (++n > 1000) 1189 return; 1190 } 1191 #endif 1192 /* Set the serial timing configuration */ 1193 /* XXX: undocumented but the Linux driver do this */ 1194 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1195 1196 /* Wait for Codec ready signal */ 1197 n = 0; 1198 do { 1199 delay(1000); 1200 if (++n > 1000) { 1201 printf("%s: Timeout waiting for Codec ready\n", 1202 sc->sc_dev.dv_xname); 1203 return; 1204 } 1205 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1206 } while (dat32 == 0); 1207 1208 /* Enable Valid Frame output on ASDOUT */ 1209 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1210 1211 /* Wait until Codec Calibration is finished. Codec register 26h */ 1212 n = 0; 1213 do { 1214 delay(1); 1215 if (++n > 1000) { 1216 printf("%s: Timeout waiting for Codec calibration\n", 1217 sc->sc_dev.dv_xname); 1218 return ; 1219 } 1220 cs4281_read_codec(sc, AC97_REG_POWER, &data); 1221 } while ((data & 0x0f) != 0x0f); 1222 1223 /* Set the serial timing configuration again */ 1224 /* XXX: undocumented but the Linux driver do this */ 1225 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1226 1227 /* Wait until we've sampled input slots 3 & 4 as valid */ 1228 n = 0; 1229 do { 1230 delay(1000); 1231 if (++n > 1000) { 1232 printf("%s: Timeout waiting for sampled input slots as valid\n", 1233 sc->sc_dev.dv_xname); 1234 return; 1235 } 1236 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 1237 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1238 1239 /* Start digital data transfer of audio data to the codec */ 1240 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1241 } 1242 1243 #ifdef NOT_SHARED 1244 /* From here to last, all functions may shared with cs4280.c */ 1245 1246 int 1247 cs4281_open(void *addr, int flags) 1248 { 1249 return 0; 1250 } 1251 1252 void 1253 cs4281_close(void *addr) 1254 { 1255 struct cs428x_softc *sc; 1256 1257 sc = addr; 1258 1259 (*sc->halt_output)(sc); 1260 (*sc->halt_input)(sc); 1261 1262 sc->sc_pintr = 0; 1263 sc->sc_rintr = 0; 1264 } 1265 1266 int 1267 cs4281_round_blocksize(void *addr, int blk) 1268 { 1269 struct cs428x_softc *sc; 1270 int retval; 1271 1272 DPRINTFN(5,("cs4281_round_blocksize blk=%d -> ", blk)); 1273 1274 sc=addr; 1275 if (blk < sc->hw_blocksize) 1276 retval = sc->hw_blocksize; 1277 else 1278 retval = blk & -(sc->hw_blocksize); 1279 1280 DPRINTFN(5,("%d\n", retval)); 1281 1282 return retval; 1283 } 1284 1285 int 1286 cs4281_mixer_set_port(void *addr, mixer_ctrl_t *cp) 1287 { 1288 struct cs428x_softc *sc; 1289 int val; 1290 1291 sc = addr; 1292 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1293 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1294 return (val); 1295 } 1296 1297 int 1298 cs4281_mixer_get_port(void *addr, mixer_ctrl_t *cp) 1299 { 1300 struct cs428x_softc *sc; 1301 1302 sc = addr; 1303 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1304 } 1305 1306 1307 int 1308 cs4281_query_devinfo(void *addr, mixer_devinfo_t *dip) 1309 { 1310 struct cs428x_softc *sc; 1311 1312 sc = addr; 1313 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1314 } 1315 1316 void * 1317 cs4281_malloc(void *addr, int direction, size_t size, int pool, int flags) 1318 { 1319 struct cs428x_softc *sc; 1320 struct cs428x_dma *p; 1321 int error; 1322 1323 sc = addr; 1324 1325 p = malloc(sizeof(*p), pool, flags); 1326 if (!p) 1327 return 0; 1328 1329 error = cs4281_allocmem(sc, size, pool, flags, p); 1330 1331 if (error) { 1332 free(p, pool); 1333 return 0; 1334 } 1335 1336 p->next = sc->sc_dmas; 1337 sc->sc_dmas = p; 1338 return BUFADDR(p); 1339 } 1340 1341 1342 1343 void 1344 cs4281_free(void *addr, void *ptr, int pool) 1345 { 1346 struct cs428x_softc *sc; 1347 struct cs428x_dma **pp, *p; 1348 1349 sc = addr; 1350 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1351 if (BUFADDR(p) == ptr) { 1352 bus_dmamap_unload(sc->sc_dmatag, p->map); 1353 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1354 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1355 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1356 free(p->dum, pool); 1357 *pp = p->next; 1358 free(p, pool); 1359 return; 1360 } 1361 } 1362 } 1363 1364 size_t 1365 cs4281_round_buffersize(void *addr, int direction, size_t size) 1366 { 1367 /* The real dma buffersize are 4KB for CS4280 1368 * and 64kB/MAX_CHANNELS for CS4281. 1369 * But they are too small for high quality audio, 1370 * let the upper layer(audio) use a larger buffer. 1371 * (originally suggested by Lennart Augustsson.) 1372 */ 1373 return size; 1374 } 1375 1376 paddr_t 1377 cs4281_mappage(void *addr, void *mem, off_t off, int prot) 1378 { 1379 struct cs428x_softc *sc; 1380 struct cs428x_dma *p; 1381 1382 sc = addr; 1383 if (off < 0) 1384 return -1; 1385 1386 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1387 ; 1388 1389 if (!p) { 1390 DPRINTF(("cs4281_mappage: bad buffer address\n")); 1391 return -1; 1392 } 1393 1394 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1395 off, prot, BUS_DMA_WAITOK)); 1396 } 1397 1398 1399 int 1400 cs4281_get_props(void *addr) 1401 { 1402 int retval; 1403 1404 retval = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1405 #ifdef MMAP_READY 1406 retval |= AUDIO_PROP_MMAP; 1407 #endif 1408 return retval; 1409 } 1410 1411 /* AC97 */ 1412 int 1413 cs4281_attach_codec(void *addr, struct ac97_codec_if *codec_if) 1414 { 1415 struct cs428x_softc *sc; 1416 1417 DPRINTF(("cs4281_attach_codec:\n")); 1418 sc = addr; 1419 sc->codec_if = codec_if; 1420 return 0; 1421 } 1422 1423 1424 int 1425 cs4281_read_codec(void *addr, u_int8_t ac97_addr, u_int16_t *ac97_data) 1426 { 1427 struct cs428x_softc *sc; 1428 u_int32_t acctl; 1429 int n; 1430 1431 sc = addr; 1432 1433 DPRINTFN(5,("read_codec: add=0x%02x ", ac97_addr)); 1434 /* 1435 * Make sure that there is not data sitting around from a preivous 1436 * uncompleted access. 1437 */ 1438 BA0READ4(sc, CS428X_ACSDA); 1439 1440 /* Set up AC97 control registers. */ 1441 BA0WRITE4(sc, CS428X_ACCAD, ac97_addr); 1442 BA0WRITE4(sc, CS428X_ACCDA, 0); 1443 1444 acctl = ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV; 1445 if ( sc->type == TYPE_CS4280 ) 1446 acctl |= ACCTL_RSTN; 1447 BA0WRITE4(sc, CS428X_ACCTL, acctl); 1448 1449 if (cs4281_src_wait(sc) < 0) { 1450 printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 1451 sc->sc_dev.dv_xname, ac97_addr); 1452 return 1; 1453 } 1454 1455 /* wait for valid status bit is active */ 1456 n = 0; 1457 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_VSTS) == 0) { 1458 delay(1); 1459 while (++n > 1000) { 1460 printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 1461 sc->sc_dev.dv_xname, ac97_addr); 1462 return 1; 1463 } 1464 } 1465 *ac97_data = BA0READ4(sc, CS428X_ACSDA); 1466 DPRINTFN(5,("data=0x%04x\n", *ac97_data)); 1467 return 0; 1468 } 1469 1470 int 1471 cs4281_write_codec(void *addr, u_int8_t ac97_addr, u_int16_t ac97_data) 1472 { 1473 struct cs428x_softc *sc; 1474 u_int32_t acctl; 1475 1476 sc = addr; 1477 1478 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", ac97_addr, ac97_data)); 1479 BA0WRITE4(sc, CS428X_ACCAD, ac97_addr); 1480 BA0WRITE4(sc, CS428X_ACCDA, ac97_data); 1481 1482 acctl = ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV; 1483 if ( sc->type == TYPE_CS4280 ) 1484 acctl |= ACCTL_RSTN; 1485 BA0WRITE4(sc, CS428X_ACCTL, acctl); 1486 1487 if (cs4281_src_wait(sc) < 0) { 1488 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 1489 "0x%04x\n", sc->sc_dev.dv_xname, ac97_addr, ac97_data); 1490 return 1; 1491 } 1492 return 0; 1493 } 1494 1495 /* Internal functions */ 1496 int 1497 cs4281_allocmem(struct cs428x_softc *sc, 1498 size_t size, int pool, int flags, 1499 struct cs428x_dma *p) 1500 { 1501 int error; 1502 size_t align; 1503 1504 align = sc->dma_align; 1505 p->size = sc->dma_size; 1506 /* allocate memory for upper audio driver */ 1507 p->dum = malloc(size, pool, flags); 1508 if (!p->dum) 1509 return 1; 1510 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1511 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1512 &p->nsegs, BUS_DMA_NOWAIT); 1513 if (error) { 1514 printf("%s: unable to allocate dma. error=%d\n", 1515 sc->sc_dev.dv_xname, error); 1516 return error; 1517 } 1518 1519 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1520 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1521 if (error) { 1522 printf("%s: unable to map dma, error=%d\n", 1523 sc->sc_dev.dv_xname, error); 1524 goto free; 1525 } 1526 1527 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1528 0, BUS_DMA_NOWAIT, &p->map); 1529 if (error) { 1530 printf("%s: unable to create dma map, error=%d\n", 1531 sc->sc_dev.dv_xname, error); 1532 goto unmap; 1533 } 1534 1535 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1536 BUS_DMA_NOWAIT); 1537 if (error) { 1538 printf("%s: unable to load dma map, error=%d\n", 1539 sc->sc_dev.dv_xname, error); 1540 goto destroy; 1541 } 1542 return 0; 1543 1544 destroy: 1545 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1546 unmap: 1547 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1548 free: 1549 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1550 return error; 1551 } 1552 1553 1554 int 1555 cs4281_src_wait(sc) 1556 struct cs428x_softc *sc; 1557 { 1558 int n; 1559 1560 n = 0; 1561 while ((BA0READ4(sc, CS428X_ACCTL) & ACCTL_DCV)) { 1562 delay(1000); 1563 while (++n > 1000) 1564 return -1; 1565 } 1566 return 0; 1567 } 1568 1569 #endif /* NOT_SHARED */ 1570
Indexes created Wed Oct 01 07:09:59 GMT 2025