cs4281.c revision 1.10
1 /* $NetBSD: cs4281.c,v 1.10 2002/05/15 09:55:45 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.10 2002/05/15 09:55:45 simonb Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 int cs4281_match(struct device *, struct cfdata *, void *); 84 void cs4281_attach(struct device *, struct device *, void *); 85 int cs4281_intr(void *); 86 int cs4281_query_encoding(void *, struct audio_encoding *); 87 int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 88 int cs4281_halt_output(void *); 89 int cs4281_halt_input(void *); 90 int cs4281_getdev(void *, struct audio_device *); 91 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 92 void *, struct audio_params *); 93 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 94 void *, struct audio_params *); 95 96 void cs4281_reset_codec(void *); 97 98 /* Internal functions */ 99 u_int8_t cs4281_sr2regval(int); 100 void cs4281_set_dac_rate(struct cs428x_softc *, int); 101 void cs4281_set_adc_rate(struct cs428x_softc *, int); 102 int cs4281_init(struct cs428x_softc *, int); 103 104 /* Power Management */ 105 void cs4281_power(int, void *); 106 107 struct audio_hw_if cs4281_hw_if = { 108 cs428x_open, 109 cs428x_close, 110 NULL, 111 cs4281_query_encoding, 112 cs4281_set_params, 113 cs428x_round_blocksize, 114 NULL, 115 NULL, 116 NULL, 117 NULL, 118 NULL, 119 cs4281_halt_output, 120 cs4281_halt_input, 121 NULL, 122 cs4281_getdev, 123 NULL, 124 cs428x_mixer_set_port, 125 cs428x_mixer_get_port, 126 cs428x_query_devinfo, 127 cs428x_malloc, 128 cs428x_free, 129 cs428x_round_buffersize, 130 cs428x_mappage, 131 cs428x_get_props, 132 cs4281_trigger_output, 133 cs4281_trigger_input, 134 NULL, 135 }; 136 137 #if NMIDI > 0 && 0 138 /* Midi Interface */ 139 void cs4281_midi_close(void*); 140 void cs4281_midi_getinfo(void *, struct midi_info *); 141 int cs4281_midi_open(void *, int, void (*)(void *, int), 142 void (*)(void *), void *); 143 int cs4281_midi_output(void *, int); 144 145 struct midi_hw_if cs4281_midi_hw_if = { 146 cs4281_midi_open, 147 cs4281_midi_close, 148 cs4281_midi_output, 149 cs4281_midi_getinfo, 150 0, 151 }; 152 #endif 153 154 struct cfattach clct_ca = { 155 sizeof(struct cs428x_softc), cs4281_match, cs4281_attach 156 }; 157 158 struct audio_device cs4281_device = { 159 "CS4281", 160 "", 161 "cs4281" 162 }; 163 164 165 int 166 cs4281_match(parent, match, aux) 167 struct device *parent; 168 struct cfdata *match; 169 void *aux; 170 { 171 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 172 173 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 174 return 0; 175 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 176 return 1; 177 return 0; 178 } 179 180 void 181 cs4281_attach(parent, self, aux) 182 struct device *parent; 183 struct device *self; 184 void *aux; 185 { 186 struct cs428x_softc *sc = (struct cs428x_softc *)self; 187 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 char const *intrstr; 190 pci_intr_handle_t ih; 191 pcireg_t reg; 192 char devinfo[256]; 193 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 194 195 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 196 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 197 198 /* Map I/O register */ 199 if (pci_mapreg_map(pa, PCI_BA0, 200 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 201 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 202 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 203 return; 204 } 205 if (pci_mapreg_map(pa, PCI_BA1, 206 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 207 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 208 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 209 return; 210 } 211 212 sc->sc_dmatag = pa->pa_dmat; 213 214 /* 215 * Set Power State D0. 216 * Without do this, 0xffffffff is read from all registers after 217 * using Windows. 218 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 219 */ 220 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 221 &pci_pwrmgmt_cap_reg, 0)) { 222 223 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 224 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 225 pci_pwrmgmt_csr_reg); 226 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 227 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 228 (reg & ~PCI_PMCSR_STATE_MASK) | 229 PCI_PMCSR_STATE_D0); 230 } 231 } 232 233 /* Enable the device (set bus master flag) */ 234 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 235 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 236 reg | PCI_COMMAND_MASTER_ENABLE); 237 238 #if 0 239 /* LATENCY_TIMER setting */ 240 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 241 if (PCI_LATTIMER(temp1) < 32) { 242 temp1 &= 0xffff00ff; 243 temp1 |= 0x00002000; 244 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 245 } 246 #endif 247 248 /* Map and establish the interrupt. */ 249 if (pci_intr_map(pa, &ih)) { 250 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 251 return; 252 } 253 intrstr = pci_intr_string(pc, ih); 254 255 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 256 if (sc->sc_ih == NULL) { 257 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 258 if (intrstr != NULL) 259 printf(" at %s", intrstr); 260 printf("\n"); 261 return; 262 } 263 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 264 265 /* 266 * Sound System start-up 267 */ 268 if (cs4281_init(sc, 1) != 0) 269 return; 270 271 sc->type = TYPE_CS4281; 272 sc->halt_input = cs4281_halt_input; 273 sc->halt_output = cs4281_halt_output; 274 275 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 276 sc->dma_align = 0x10; 277 sc->hw_blocksize = sc->dma_size / 2; 278 279 /* AC 97 attachment */ 280 sc->host_if.arg = sc; 281 sc->host_if.attach = cs428x_attach_codec; 282 sc->host_if.read = cs428x_read_codec; 283 sc->host_if.write = cs428x_write_codec; 284 sc->host_if.reset = cs4281_reset_codec; 285 if (ac97_attach(&sc->host_if) != 0) { 286 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 287 return; 288 } 289 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 290 291 #if NMIDI > 0 && 0 292 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 293 #endif 294 295 sc->sc_suspend = PWR_RESUME; 296 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 297 } 298 299 int 300 cs4281_intr(p) 301 void *p; 302 { 303 struct cs428x_softc *sc = p; 304 u_int32_t intr, hdsr0, hdsr1; 305 char *empty_dma; 306 int handled = 0; 307 308 hdsr0 = 0; 309 hdsr1 = 0; 310 311 /* grab interrupt register */ 312 intr = BA0READ4(sc, CS4281_HISR); 313 314 DPRINTF(("cs4281_intr:")); 315 /* not for me */ 316 if ((intr & HISR_INTENA) == 0) { 317 /* clear the interrupt register */ 318 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 319 return 0; 320 } 321 322 if (intr & HISR_DMA0) 323 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 324 if (intr & HISR_DMA1) 325 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 326 /* clear the interrupt register */ 327 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 328 329 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 330 intr, hdsr0, hdsr1)); 331 332 /* Playback Interrupt */ 333 if (intr & HISR_DMA0) { 334 handled = 1; 335 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 336 (int)BA0READ4(sc, CS4281_DCC0))); 337 if (sc->sc_pintr) { 338 if ((sc->sc_pi%sc->sc_pcount) == 0) 339 sc->sc_pintr(sc->sc_parg); 340 } else { 341 printf("unexpected play intr\n"); 342 } 343 /* copy buffer */ 344 ++sc->sc_pi; 345 empty_dma = sc->sc_pdma->addr; 346 if (sc->sc_pi&1) 347 empty_dma += sc->hw_blocksize; 348 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 349 sc->sc_pn += sc->hw_blocksize; 350 if (sc->sc_pn >= sc->sc_pe) 351 sc->sc_pn = sc->sc_ps; 352 } 353 if (intr & HISR_DMA1) { 354 handled = 1; 355 /* copy from dma */ 356 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 357 (int)BA0READ4(sc, CS4281_DCC1))); 358 ++sc->sc_ri; 359 empty_dma = sc->sc_rdma->addr; 360 if ((sc->sc_ri & 1) == 0) 361 empty_dma += sc->hw_blocksize; 362 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 363 if (sc->sc_rn >= sc->sc_re) 364 sc->sc_rn = sc->sc_rs; 365 if (sc->sc_rintr) { 366 if ((sc->sc_ri % sc->sc_rcount) == 0) 367 sc->sc_rintr(sc->sc_rarg); 368 } else { 369 printf("unexpected record intr\n"); 370 } 371 } 372 DPRINTF(("\n")); 373 374 return handled; 375 } 376 377 int 378 cs4281_query_encoding(addr, fp) 379 void *addr; 380 struct audio_encoding *fp; 381 { 382 383 switch (fp->index) { 384 case 0: 385 strcpy(fp->name, AudioEulinear); 386 fp->encoding = AUDIO_ENCODING_ULINEAR; 387 fp->precision = 8; 388 fp->flags = 0; 389 break; 390 case 1: 391 strcpy(fp->name, AudioEmulaw); 392 fp->encoding = AUDIO_ENCODING_ULAW; 393 fp->precision = 8; 394 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 395 break; 396 case 2: 397 strcpy(fp->name, AudioEalaw); 398 fp->encoding = AUDIO_ENCODING_ALAW; 399 fp->precision = 8; 400 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 401 break; 402 case 3: 403 strcpy(fp->name, AudioEslinear); 404 fp->encoding = AUDIO_ENCODING_SLINEAR; 405 fp->precision = 8; 406 fp->flags = 0; 407 break; 408 case 4: 409 strcpy(fp->name, AudioEslinear_le); 410 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 411 fp->precision = 16; 412 fp->flags = 0; 413 break; 414 case 5: 415 strcpy(fp->name, AudioEulinear_le); 416 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 417 fp->precision = 16; 418 fp->flags = 0; 419 break; 420 case 6: 421 strcpy(fp->name, AudioEslinear_be); 422 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 423 fp->precision = 16; 424 fp->flags = 0; 425 break; 426 case 7: 427 strcpy(fp->name, AudioEulinear_be); 428 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 429 fp->precision = 16; 430 fp->flags = 0; 431 break; 432 default: 433 return EINVAL; 434 } 435 return 0; 436 } 437 438 int 439 cs4281_set_params(addr, setmode, usemode, play, rec) 440 void *addr; 441 int setmode, usemode; 442 struct audio_params *play, *rec; 443 { 444 struct cs428x_softc *sc = addr; 445 struct audio_params *p; 446 int mode; 447 448 for (mode = AUMODE_RECORD; mode != -1; 449 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 450 if ((setmode & mode) == 0) 451 continue; 452 453 p = mode == AUMODE_PLAY ? play : rec; 454 455 if (p == play) { 456 DPRINTFN(5, ("play: sample=%ld precision=%d channels=%d\n", 457 p->sample_rate, p->precision, p->channels)); 458 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 459 (p->precision != 8 && p->precision != 16) || 460 (p->channels != 1 && p->channels != 2)) { 461 return (EINVAL); 462 } 463 } else { 464 DPRINTFN(5, ("rec: sample=%ld precision=%d channels=%d\n", 465 p->sample_rate, p->precision, p->channels)); 466 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 467 (p->precision != 8 && p->precision != 16) || 468 (p->channels != 1 && p->channels != 2)) { 469 return (EINVAL); 470 } 471 } 472 p->factor = 1; 473 p->sw_code = 0; 474 475 switch (p->encoding) { 476 case AUDIO_ENCODING_SLINEAR_BE: 477 break; 478 case AUDIO_ENCODING_SLINEAR_LE: 479 break; 480 case AUDIO_ENCODING_ULINEAR_BE: 481 break; 482 case AUDIO_ENCODING_ULINEAR_LE: 483 break; 484 case AUDIO_ENCODING_ULAW: 485 if (mode == AUMODE_PLAY) { 486 p->sw_code = mulaw_to_slinear8; 487 } else { 488 p->sw_code = slinear8_to_mulaw; 489 } 490 break; 491 case AUDIO_ENCODING_ALAW: 492 if (mode == AUMODE_PLAY) { 493 p->sw_code = alaw_to_slinear8; 494 } else { 495 p->sw_code = slinear8_to_alaw; 496 } 497 break; 498 default: 499 return (EINVAL); 500 } 501 } 502 503 /* set sample rate */ 504 cs4281_set_dac_rate(sc, play->sample_rate); 505 cs4281_set_adc_rate(sc, rec->sample_rate); 506 return 0; 507 } 508 509 int 510 cs4281_halt_output(addr) 511 void *addr; 512 { 513 struct cs428x_softc *sc = addr; 514 515 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 516 sc->sc_prun = 0; 517 return 0; 518 } 519 520 int 521 cs4281_halt_input(addr) 522 void *addr; 523 { 524 struct cs428x_softc *sc = addr; 525 526 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 527 sc->sc_rrun = 0; 528 return 0; 529 } 530 531 int 532 cs4281_getdev(addr, retp) 533 void *addr; 534 struct audio_device *retp; 535 { 536 537 *retp = cs4281_device; 538 return 0; 539 } 540 541 int 542 cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 543 void *addr; 544 void *start, *end; 545 int blksize; 546 void (*intr) __P((void *)); 547 void *arg; 548 struct audio_params *param; 549 { 550 struct cs428x_softc *sc = addr; 551 u_int32_t fmt=0; 552 struct cs428x_dma *p; 553 int dma_count; 554 555 #ifdef DIAGNOSTIC 556 if (sc->sc_prun) 557 printf("cs4281_trigger_output: already running\n"); 558 #endif 559 sc->sc_prun = 1; 560 561 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 562 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 563 sc->sc_pintr = intr; 564 sc->sc_parg = arg; 565 566 /* stop playback DMA */ 567 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 568 569 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 570 param->precision, param->factor, param->channels, 571 param->encoding)); 572 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 573 ; 574 if (p == NULL) { 575 printf("cs4281_trigger_output: bad addr %p\n", start); 576 return (EINVAL); 577 } 578 579 sc->sc_pcount = blksize / sc->hw_blocksize; 580 sc->sc_ps = (char *)start; 581 sc->sc_pe = (char *)end; 582 sc->sc_pdma = p; 583 sc->sc_pbuf = KERNADDR(p); 584 sc->sc_pi = 0; 585 sc->sc_pn = sc->sc_ps; 586 if (blksize >= sc->dma_size) { 587 sc->sc_pn = sc->sc_ps + sc->dma_size; 588 memcpy(sc->sc_pbuf, start, sc->dma_size); 589 ++sc->sc_pi; 590 } else { 591 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 592 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 593 } 594 595 dma_count = sc->dma_size; 596 if (param->precision * param->factor != 8) 597 dma_count /= 2; /* 16 bit */ 598 if (param->channels > 1) 599 dma_count /= 2; /* Stereo */ 600 601 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 602 (int)DMAADDR(p), dma_count)); 603 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 604 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 605 606 /* set playback format */ 607 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 608 if (param->precision * param->factor == 8) 609 fmt |= DMRn_SIZE8; 610 if (param->channels == 1) 611 fmt |= DMRn_MONO; 612 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 613 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 614 fmt |= DMRn_BEND; 615 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 616 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 617 fmt |= DMRn_USIGN; 618 BA0WRITE4(sc, CS4281_DMR0, fmt); 619 620 /* set sample rate */ 621 sc->sc_prate = param->sample_rate; 622 cs4281_set_dac_rate(sc, param->sample_rate); 623 624 /* start DMA */ 625 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 626 /* Enable interrupts */ 627 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 628 629 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 630 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 631 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 632 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 633 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 634 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 635 BA0READ4(sc, CS4281_DACSR))); 636 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 637 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 638 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 639 640 return 0; 641 } 642 643 int 644 cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 645 void *addr; 646 void *start, *end; 647 int blksize; 648 void (*intr) __P((void *)); 649 void *arg; 650 struct audio_params *param; 651 { 652 struct cs428x_softc *sc = addr; 653 struct cs428x_dma *p; 654 u_int32_t fmt=0; 655 int dma_count; 656 657 #ifdef DIAGNOSTIC 658 if (sc->sc_rrun) 659 printf("cs4281_trigger_input: already running\n"); 660 #endif 661 sc->sc_rrun = 1; 662 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 663 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 664 sc->sc_rintr = intr; 665 sc->sc_rarg = arg; 666 667 /* stop recording DMA */ 668 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 669 670 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 671 ; 672 if (!p) { 673 printf("cs4281_trigger_input: bad addr %p\n", start); 674 return (EINVAL); 675 } 676 677 sc->sc_rcount = blksize / sc->hw_blocksize; 678 sc->sc_rs = (char *)start; 679 sc->sc_re = (char *)end; 680 sc->sc_rdma = p; 681 sc->sc_rbuf = KERNADDR(p); 682 sc->sc_ri = 0; 683 sc->sc_rn = sc->sc_rs; 684 685 dma_count = sc->dma_size; 686 if (param->precision * param->factor == 8) 687 dma_count /= 2; 688 if (param->channels > 1) 689 dma_count /= 2; 690 691 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 692 (int)DMAADDR(p), dma_count)); 693 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 694 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 695 696 /* set recording format */ 697 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 698 if (param->precision * param->factor == 8) 699 fmt |= DMRn_SIZE8; 700 if (param->channels == 1) 701 fmt |= DMRn_MONO; 702 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 703 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 704 fmt |= DMRn_BEND; 705 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 706 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 707 fmt |= DMRn_USIGN; 708 BA0WRITE4(sc, CS4281_DMR1, fmt); 709 710 /* set sample rate */ 711 sc->sc_rrate = param->sample_rate; 712 cs4281_set_adc_rate(sc, param->sample_rate); 713 714 /* Start DMA */ 715 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 716 /* Enable interrupts */ 717 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 718 719 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 720 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 721 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 722 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 723 724 return 0; 725 } 726 727 /* Power Hook */ 728 void 729 cs4281_power(why, v) 730 int why; 731 void *v; 732 { 733 struct cs428x_softc *sc = (struct cs428x_softc *)v; 734 static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 735 static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 736 737 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 738 switch (why) { 739 case PWR_SUSPEND: 740 case PWR_STANDBY: 741 sc->sc_suspend = why; 742 743 /* save current playback status */ 744 if (sc->sc_prun) { 745 dcr0 = BA0READ4(sc, CS4281_DCR0); 746 dmr0 = BA0READ4(sc, CS4281_DMR0); 747 dbc0 = BA0READ4(sc, CS4281_DBC0); 748 dba0 = BA0READ4(sc, CS4281_DBA0); 749 } 750 751 /* save current capture status */ 752 if (sc->sc_rrun) { 753 dcr1 = BA0READ4(sc, CS4281_DCR1); 754 dmr1 = BA0READ4(sc, CS4281_DMR1); 755 dbc1 = BA0READ4(sc, CS4281_DBC1); 756 dba1 = BA0READ4(sc, CS4281_DBA1); 757 } 758 /* Stop DMA */ 759 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 760 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 761 break; 762 case PWR_RESUME: 763 if (sc->sc_suspend == PWR_RESUME) { 764 printf("cs4281_power: odd, resume without suspend.\n"); 765 sc->sc_suspend = why; 766 return; 767 } 768 sc->sc_suspend = why; 769 cs4281_init(sc, 0); 770 cs4281_reset_codec(sc); 771 772 /* restore ac97 registers */ 773 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 774 775 /* restore DMA related status */ 776 if (sc->sc_prun) { 777 cs4281_set_dac_rate(sc, sc->sc_prate); 778 BA0WRITE4(sc, CS4281_DBA0, dba0); 779 BA0WRITE4(sc, CS4281_DBC0, dbc0); 780 BA0WRITE4(sc, CS4281_DMR0, dmr0); 781 BA0WRITE4(sc, CS4281_DCR0, dcr0); 782 } 783 if (sc->sc_rrun) { 784 cs4281_set_adc_rate(sc, sc->sc_rrate); 785 BA0WRITE4(sc, CS4281_DBA1, dba1); 786 BA0WRITE4(sc, CS4281_DBC1, dbc1); 787 BA0WRITE4(sc, CS4281_DMR1, dmr1); 788 BA0WRITE4(sc, CS4281_DCR1, dcr1); 789 } 790 /* enable intterupts */ 791 if (sc->sc_prun || sc->sc_rrun) 792 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 793 break; 794 case PWR_SOFTSUSPEND: 795 case PWR_SOFTSTANDBY: 796 case PWR_SOFTRESUME: 797 break; 798 } 799 } 800 801 /* control AC97 codec */ 802 void 803 cs4281_reset_codec(void *addr) 804 { 805 struct cs428x_softc *sc; 806 u_int16_t data; 807 u_int32_t dat32; 808 int n; 809 810 sc = addr; 811 812 DPRINTFN(3, ("cs4281_reset_codec\n")); 813 814 /* Reset codec */ 815 BA0WRITE4(sc, CS428X_ACCTL, 0); 816 delay(50); /* delay 50us */ 817 818 BA0WRITE4(sc, CS4281_SPMC, 0); 819 delay(100); /* delay 100us */ 820 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 821 #if defined(ENABLE_SECONDARY_CODEC) 822 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 823 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 824 #endif 825 delay(50000); /* XXX: delay 50ms */ 826 827 /* Enable ASYNC generation */ 828 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 829 830 /* Wait for codec ready. Linux driver waits 50ms here */ 831 n = 0; 832 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 833 delay(100); 834 if (++n > 1000) { 835 printf("reset_codec: AC97 codec ready timeout\n"); 836 return; 837 } 838 } 839 #if defined(ENABLE_SECONDARY_CODEC) 840 /* secondary codec ready*/ 841 n = 0; 842 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 843 delay(100); 844 if (++n > 1000) 845 return; 846 } 847 #endif 848 /* Set the serial timing configuration */ 849 /* XXX: undocumented but the Linux driver do this */ 850 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 851 852 /* Wait for codec ready signal */ 853 n = 0; 854 do { 855 delay(1000); 856 if (++n > 1000) { 857 printf("%s: timeout waiting for codec ready\n", 858 sc->sc_dev.dv_xname); 859 return; 860 } 861 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 862 } while (dat32 == 0); 863 864 /* Enable Valid Frame output on ASDOUT */ 865 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 866 867 /* Wait until codec calibration is finished. Codec register 26h */ 868 n = 0; 869 do { 870 delay(1); 871 if (++n > 1000) { 872 printf("%s: timeout waiting for codec calibration\n", 873 sc->sc_dev.dv_xname); 874 return ; 875 } 876 cs428x_read_codec(sc, AC97_REG_POWER, &data); 877 } while ((data & 0x0f) != 0x0f); 878 879 /* Set the serial timing configuration again */ 880 /* XXX: undocumented but the Linux driver do this */ 881 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 882 883 /* Wait until we've sampled input slots 3 & 4 as valid */ 884 n = 0; 885 do { 886 delay(1000); 887 if (++n > 1000) { 888 printf("%s: timeout waiting for sampled input slots as valid\n", 889 sc->sc_dev.dv_xname); 890 return; 891 } 892 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 893 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 894 895 /* Start digital data transfer of audio data to the codec */ 896 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 897 } 898 899 900 /* Internal functions */ 901 902 /* convert sample rate to register value */ 903 u_int8_t 904 cs4281_sr2regval(rate) 905 int rate; 906 { 907 u_int8_t retval; 908 909 /* We don't have to change here. but anyway ... */ 910 if (rate > 48000) 911 rate = 48000; 912 if (rate < 6023) 913 rate = 6023; 914 915 switch (rate) { 916 case 8000: 917 retval = 5; 918 break; 919 case 11025: 920 retval = 4; 921 break; 922 case 16000: 923 retval = 3; 924 break; 925 case 22050: 926 retval = 2; 927 break; 928 case 44100: 929 retval = 1; 930 break; 931 case 48000: 932 retval = 0; 933 break; 934 default: 935 retval = 1536000/rate; /* == 24576000/(rate*16) */ 936 } 937 return retval; 938 } 939 940 void 941 cs4281_set_adc_rate(sc, rate) 942 struct cs428x_softc *sc; 943 int rate; 944 { 945 946 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 947 } 948 949 void 950 cs4281_set_dac_rate(sc, rate) 951 struct cs428x_softc *sc; 952 int rate; 953 { 954 955 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 956 } 957 958 int 959 cs4281_init(sc, init) 960 struct cs428x_softc *sc; 961 int init; 962 { 963 int n; 964 u_int16_t data; 965 u_int32_t dat32; 966 967 /* set "Configuration Write Protect" register to 968 * 0x4281 to allow to write */ 969 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 970 971 /* 972 * Unset "Full Power-Down bit of Extended PCI Power Management 973 * Control" register to release the reset state. 974 */ 975 dat32 = BA0READ4(sc, CS4281_EPPMC); 976 if (dat32 & EPPMC_FPDN) { 977 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 978 } 979 980 /* Start PLL out in known state */ 981 BA0WRITE4(sc, CS4281_CLKCR1, 0); 982 /* Start serial ports out in known state */ 983 BA0WRITE4(sc, CS4281_SERMC, 0); 984 985 /* Reset codec */ 986 BA0WRITE4(sc, CS428X_ACCTL, 0); 987 delay(50); /* delay 50us */ 988 989 BA0WRITE4(sc, CS4281_SPMC, 0); 990 delay(100); /* delay 100us */ 991 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 992 #if defined(ENABLE_SECONDARY_CODEC) 993 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 994 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 995 #endif 996 delay(50000); /* XXX: delay 50ms */ 997 998 /* Turn on Sound System clocks based on ABITCLK */ 999 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 1000 delay(50000); /* XXX: delay 50ms */ 1001 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1002 1003 /* Set enables for sections that are needed in the SSPM registers */ 1004 BA0WRITE4(sc, CS4281_SSPM, 1005 SSPM_MIXEN | /* Mixer */ 1006 SSPM_CSRCEN | /* Capture SRC */ 1007 SSPM_PSRCEN | /* Playback SRC */ 1008 SSPM_JSEN | /* Joystick */ 1009 SSPM_ACLEN | /* AC LINK */ 1010 SSPM_FMEN /* FM */ 1011 ); 1012 1013 /* Wait for clock stabilization */ 1014 n = 0; 1015 #if 1 1016 /* what document says */ 1017 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1018 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1019 delay(100); 1020 if (++n > 1000) { 1021 printf("%s: timeout waiting for clock stabilization\n", 1022 sc->sc_dev.dv_xname); 1023 return -1; 1024 } 1025 } 1026 #else 1027 /* Cirrus driver for Linux does */ 1028 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1029 delay(1000); 1030 if (++n > 1000) { 1031 printf("%s: timeout waiting for clock stabilization\n", 1032 sc->sc_dev.dv_xname); 1033 return -1; 1034 } 1035 } 1036 #endif 1037 1038 /* Enable ASYNC generation */ 1039 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1040 1041 /* Wait for codec ready. Linux driver waits 50ms here */ 1042 n = 0; 1043 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1044 delay(100); 1045 if (++n > 1000) { 1046 printf("%s: timeout waiting for codec ready\n", 1047 sc->sc_dev.dv_xname); 1048 return -1; 1049 } 1050 } 1051 1052 #if defined(ENABLE_SECONDARY_CODEC) 1053 /* secondary codec ready*/ 1054 n = 0; 1055 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1056 delay(100); 1057 if (++n > 1000) { 1058 printf("%s: timeout waiting for secondary codec ready\n", 1059 sc->sc_dev.dv_xname); 1060 return -1; 1061 } 1062 } 1063 #endif 1064 1065 /* Set the serial timing configuration */ 1066 /* XXX: undocumented but the Linux driver do this */ 1067 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1068 1069 /* Wait for codec ready signal */ 1070 n = 0; 1071 do { 1072 delay(1000); 1073 if (++n > 1000) { 1074 printf("%s: timeout waiting for codec ready\n", 1075 sc->sc_dev.dv_xname); 1076 return -1; 1077 } 1078 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1079 } while (dat32 == 0); 1080 1081 /* Enable Valid Frame output on ASDOUT */ 1082 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1083 1084 /* Wait until codec calibration is finished. codec register 26h */ 1085 n = 0; 1086 do { 1087 delay(1); 1088 if (++n > 1000) { 1089 printf("%s: timeout waiting for codec calibration\n", 1090 sc->sc_dev.dv_xname); 1091 return -1; 1092 } 1093 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1094 } while ((data & 0x0f) != 0x0f); 1095 1096 /* Set the serial timing configuration again */ 1097 /* XXX: undocumented but the Linux driver do this */ 1098 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1099 1100 /* Wait until we've sampled input slots 3 & 4 as valid */ 1101 n = 0; 1102 do { 1103 delay(1000); 1104 if (++n > 1000) { 1105 printf("%s: timeout waiting for sampled input slots as valid\n", 1106 sc->sc_dev.dv_xname); 1107 return -1; 1108 } 1109 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1110 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1111 1112 /* Start digital data transfer of audio data to the codec */ 1113 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1114 1115 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1116 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1117 1118 /* Power on the DAC */ 1119 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1120 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1121 1122 /* Wait until we sample a DAC ready state. 1123 * Not documented, but Linux driver does. 1124 */ 1125 for (n = 0; n < 32; ++n) { 1126 delay(1000); 1127 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1128 if (data & 0x02) 1129 break; 1130 } 1131 1132 /* Power on the ADC */ 1133 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1134 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1135 1136 /* Wait until we sample ADC ready state. 1137 * Not documented, but Linux driver does. 1138 */ 1139 for (n = 0; n < 32; ++n) { 1140 delay(1000); 1141 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1142 if (data & 0x01) 1143 break; 1144 } 1145 1146 #if 0 1147 /* Initialize AC-Link features */ 1148 /* variable sample-rate support */ 1149 mem = BA0READ4(sc, CS4281_SERMC); 1150 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1151 BA0WRITE4(sc, CS4281_SERMC, mem); 1152 /* XXX: more... */ 1153 1154 /* Initialize SSCR register features */ 1155 /* XXX: hardware volume setting */ 1156 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1157 #endif 1158 1159 /* disable Sound Blaster Pro emulation */ 1160 /* XXX: 1161 * Cannot set since the documents does not describe which bit is 1162 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1163 * we can ignore it.*/ 1164 #if 0 1165 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1166 #endif 1167 1168 /* map AC97 PCM playback to DMA Channel 0 */ 1169 /* Reset FEN bit to setup first */ 1170 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1171 /* 1172 *| RS[4:0]/| | 1173 *| LS[4:0] | AC97 | Slot Function 1174 *|---------+--------+-------------------- 1175 *| 0 | 3 | Left PCM Playback 1176 *| 1 | 4 | Right PCM Playback 1177 *| 2 | 5 | Phone Line 1 DAC 1178 *| 3 | 6 | Center PCM Playback 1179 *.... 1180 * quoted from Table 29(p109) 1181 */ 1182 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1183 0x00 << 16 | /* LS[4:0] = 0 see above */ 1184 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1185 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1186 BA0WRITE4(sc, CS4281_FCR0, dat32); 1187 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1188 1189 /* map AC97 PCM record to DMA Channel 1 */ 1190 /* Reset FEN bit to setup first */ 1191 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1192 /* 1193 *| RS[4:0]/| 1194 *| LS[4:0] | AC97 | Slot Function 1195 *|---------+------+------------------- 1196 *| 10 | 3 | Left PCM Record 1197 *| 11 | 4 | Right PCM Record 1198 *| 12 | 5 | Phone Line 1 ADC 1199 *| 13 | 6 | Mic ADC 1200 *.... 1201 * quoted from Table 30(p109) 1202 */ 1203 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1204 0x0a << 16 | /* LS[4:0] = 10 See above */ 1205 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1206 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1207 1208 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1209 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1210 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1211 1212 #if 0 1213 /* Disable DMA Channel 2, 3 */ 1214 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1215 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1216 #endif 1217 1218 /* Set the SRC Slot Assignment accordingly */ 1219 /*| PLSS[4:0]/ 1220 *| PRSS[4:0] | AC97 | Slot Function 1221 *|-----------+------+---------------- 1222 *| 0 | 3 | Left PCM Playback 1223 *| 1 | 4 | Right PCM Playback 1224 *| 2 | 5 | phone line 1 DAC 1225 *| 3 | 6 | Center PCM Playback 1226 *| 4 | 7 | Left Surround PCM Playback 1227 *| 5 | 8 | Right Surround PCM Playback 1228 *...... 1229 * 1230 *| CLSS[4:0]/ 1231 *| CRSS[4:0] | AC97 | Codec |Slot Function 1232 *|-----------+------+-------+----------------- 1233 *| 10 | 3 |Primary| Left PCM Record 1234 *| 11 | 4 |Primary| Right PCM Record 1235 *| 12 | 5 |Primary| Phone Line 1 ADC 1236 *| 13 | 6 |Primary| Mic ADC 1237 *|..... 1238 *| 20 | 3 | Sec. | Left PCM Record 1239 *| 21 | 4 | Sec. | Right PCM Record 1240 *| 22 | 5 | Sec. | Phone Line 1 ADC 1241 *| 23 | 6 | Sec. | Mic ADC 1242 */ 1243 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1244 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1245 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1246 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1247 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1248 1249 /* Set interrupt to occurred at Half and Full terminal 1250 * count interrupt enable for DMA channel 0 and 1. 1251 * To keep DMA stop, set MSK. 1252 */ 1253 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1254 BA0WRITE4(sc, CS4281_DCR0, dat32); 1255 BA0WRITE4(sc, CS4281_DCR1, dat32); 1256 1257 /* Set Auto-Initialize Contorl enable */ 1258 BA0WRITE4(sc, CS4281_DMR0, 1259 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1260 BA0WRITE4(sc, CS4281_DMR1, 1261 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1262 1263 /* Clear DMA Mask in HIMR */ 1264 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1265 BA0WRITE4(sc, CS4281_HIMR, 1266 BA0READ4(sc, CS4281_HIMR) & dat32); 1267 1268 /* set current status */ 1269 if (init != 0) { 1270 sc->sc_prun = 0; 1271 sc->sc_rrun = 0; 1272 } 1273 1274 /* setup playback volume */ 1275 BA0WRITE4(sc, CS4281_PPRVC, 7); 1276 BA0WRITE4(sc, CS4281_PPLVC, 7); 1277 1278 return 0; 1279 } 1280
Indexes created Wed Oct 01 07:09:59 GMT 2025