cs4281.c revision 1.12
1 /* $NetBSD: cs4281.c,v 1.12 2002/09/30 20:37:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.12 2002/09/30 20:37:14 thorpej Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 int cs4281_match(struct device *, struct cfdata *, void *); 84 void cs4281_attach(struct device *, struct device *, void *); 85 int cs4281_intr(void *); 86 int cs4281_query_encoding(void *, struct audio_encoding *); 87 int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 88 int cs4281_halt_output(void *); 89 int cs4281_halt_input(void *); 90 int cs4281_getdev(void *, struct audio_device *); 91 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 92 void *, struct audio_params *); 93 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 94 void *, struct audio_params *); 95 96 void cs4281_reset_codec(void *); 97 98 /* Internal functions */ 99 u_int8_t cs4281_sr2regval(int); 100 void cs4281_set_dac_rate(struct cs428x_softc *, int); 101 void cs4281_set_adc_rate(struct cs428x_softc *, int); 102 int cs4281_init(struct cs428x_softc *, int); 103 104 /* Power Management */ 105 void cs4281_power(int, void *); 106 107 struct audio_hw_if cs4281_hw_if = { 108 cs428x_open, 109 cs428x_close, 110 NULL, 111 cs4281_query_encoding, 112 cs4281_set_params, 113 cs428x_round_blocksize, 114 NULL, 115 NULL, 116 NULL, 117 NULL, 118 NULL, 119 cs4281_halt_output, 120 cs4281_halt_input, 121 NULL, 122 cs4281_getdev, 123 NULL, 124 cs428x_mixer_set_port, 125 cs428x_mixer_get_port, 126 cs428x_query_devinfo, 127 cs428x_malloc, 128 cs428x_free, 129 cs428x_round_buffersize, 130 cs428x_mappage, 131 cs428x_get_props, 132 cs4281_trigger_output, 133 cs4281_trigger_input, 134 NULL, 135 }; 136 137 #if NMIDI > 0 && 0 138 /* Midi Interface */ 139 void cs4281_midi_close(void*); 140 void cs4281_midi_getinfo(void *, struct midi_info *); 141 int cs4281_midi_open(void *, int, void (*)(void *, int), 142 void (*)(void *), void *); 143 int cs4281_midi_output(void *, int); 144 145 struct midi_hw_if cs4281_midi_hw_if = { 146 cs4281_midi_open, 147 cs4281_midi_close, 148 cs4281_midi_output, 149 cs4281_midi_getinfo, 150 0, 151 }; 152 #endif 153 154 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 155 cs4281_match, cs4281_attach, NULL, NULL) 156 157 struct audio_device cs4281_device = { 158 "CS4281", 159 "", 160 "cs4281" 161 }; 162 163 164 int 165 cs4281_match(parent, match, aux) 166 struct device *parent; 167 struct cfdata *match; 168 void *aux; 169 { 170 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 171 172 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 173 return 0; 174 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 175 return 1; 176 return 0; 177 } 178 179 void 180 cs4281_attach(parent, self, aux) 181 struct device *parent; 182 struct device *self; 183 void *aux; 184 { 185 struct cs428x_softc *sc = (struct cs428x_softc *)self; 186 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 187 pci_chipset_tag_t pc = pa->pa_pc; 188 char const *intrstr; 189 pci_intr_handle_t ih; 190 pcireg_t reg; 191 char devinfo[256]; 192 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 193 194 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 195 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 196 197 /* Map I/O register */ 198 if (pci_mapreg_map(pa, PCI_BA0, 199 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 200 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 201 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 202 return; 203 } 204 if (pci_mapreg_map(pa, PCI_BA1, 205 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 206 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 207 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 208 return; 209 } 210 211 sc->sc_dmatag = pa->pa_dmat; 212 213 /* 214 * Set Power State D0. 215 * Without do this, 0xffffffff is read from all registers after 216 * using Windows. 217 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 218 */ 219 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 220 &pci_pwrmgmt_cap_reg, 0)) { 221 222 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 223 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 224 pci_pwrmgmt_csr_reg); 225 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 226 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 227 (reg & ~PCI_PMCSR_STATE_MASK) | 228 PCI_PMCSR_STATE_D0); 229 } 230 } 231 232 /* Enable the device (set bus master flag) */ 233 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 234 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 235 reg | PCI_COMMAND_MASTER_ENABLE); 236 237 #if 0 238 /* LATENCY_TIMER setting */ 239 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 240 if (PCI_LATTIMER(temp1) < 32) { 241 temp1 &= 0xffff00ff; 242 temp1 |= 0x00002000; 243 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 244 } 245 #endif 246 247 /* Map and establish the interrupt. */ 248 if (pci_intr_map(pa, &ih)) { 249 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 250 return; 251 } 252 intrstr = pci_intr_string(pc, ih); 253 254 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 255 if (sc->sc_ih == NULL) { 256 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 257 if (intrstr != NULL) 258 printf(" at %s", intrstr); 259 printf("\n"); 260 return; 261 } 262 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 263 264 /* 265 * Sound System start-up 266 */ 267 if (cs4281_init(sc, 1) != 0) 268 return; 269 270 sc->type = TYPE_CS4281; 271 sc->halt_input = cs4281_halt_input; 272 sc->halt_output = cs4281_halt_output; 273 274 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 275 sc->dma_align = 0x10; 276 sc->hw_blocksize = sc->dma_size / 2; 277 278 /* AC 97 attachment */ 279 sc->host_if.arg = sc; 280 sc->host_if.attach = cs428x_attach_codec; 281 sc->host_if.read = cs428x_read_codec; 282 sc->host_if.write = cs428x_write_codec; 283 sc->host_if.reset = cs4281_reset_codec; 284 if (ac97_attach(&sc->host_if) != 0) { 285 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 286 return; 287 } 288 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 289 290 #if NMIDI > 0 && 0 291 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 292 #endif 293 294 sc->sc_suspend = PWR_RESUME; 295 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 296 } 297 298 int 299 cs4281_intr(p) 300 void *p; 301 { 302 struct cs428x_softc *sc = p; 303 u_int32_t intr, hdsr0, hdsr1; 304 char *empty_dma; 305 int handled = 0; 306 307 hdsr0 = 0; 308 hdsr1 = 0; 309 310 /* grab interrupt register */ 311 intr = BA0READ4(sc, CS4281_HISR); 312 313 DPRINTF(("cs4281_intr:")); 314 /* not for me */ 315 if ((intr & HISR_INTENA) == 0) { 316 /* clear the interrupt register */ 317 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 318 return 0; 319 } 320 321 if (intr & HISR_DMA0) 322 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 323 if (intr & HISR_DMA1) 324 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 325 /* clear the interrupt register */ 326 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 327 328 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 329 intr, hdsr0, hdsr1)); 330 331 /* Playback Interrupt */ 332 if (intr & HISR_DMA0) { 333 handled = 1; 334 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 335 (int)BA0READ4(sc, CS4281_DCC0))); 336 if (sc->sc_pintr) { 337 if ((sc->sc_pi%sc->sc_pcount) == 0) 338 sc->sc_pintr(sc->sc_parg); 339 } else { 340 printf("unexpected play intr\n"); 341 } 342 /* copy buffer */ 343 ++sc->sc_pi; 344 empty_dma = sc->sc_pdma->addr; 345 if (sc->sc_pi&1) 346 empty_dma += sc->hw_blocksize; 347 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 348 sc->sc_pn += sc->hw_blocksize; 349 if (sc->sc_pn >= sc->sc_pe) 350 sc->sc_pn = sc->sc_ps; 351 } 352 if (intr & HISR_DMA1) { 353 handled = 1; 354 /* copy from dma */ 355 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 356 (int)BA0READ4(sc, CS4281_DCC1))); 357 ++sc->sc_ri; 358 empty_dma = sc->sc_rdma->addr; 359 if ((sc->sc_ri & 1) == 0) 360 empty_dma += sc->hw_blocksize; 361 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 362 if (sc->sc_rn >= sc->sc_re) 363 sc->sc_rn = sc->sc_rs; 364 if (sc->sc_rintr) { 365 if ((sc->sc_ri % sc->sc_rcount) == 0) 366 sc->sc_rintr(sc->sc_rarg); 367 } else { 368 printf("unexpected record intr\n"); 369 } 370 } 371 DPRINTF(("\n")); 372 373 return handled; 374 } 375 376 int 377 cs4281_query_encoding(addr, fp) 378 void *addr; 379 struct audio_encoding *fp; 380 { 381 382 switch (fp->index) { 383 case 0: 384 strcpy(fp->name, AudioEulinear); 385 fp->encoding = AUDIO_ENCODING_ULINEAR; 386 fp->precision = 8; 387 fp->flags = 0; 388 break; 389 case 1: 390 strcpy(fp->name, AudioEmulaw); 391 fp->encoding = AUDIO_ENCODING_ULAW; 392 fp->precision = 8; 393 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 394 break; 395 case 2: 396 strcpy(fp->name, AudioEalaw); 397 fp->encoding = AUDIO_ENCODING_ALAW; 398 fp->precision = 8; 399 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 400 break; 401 case 3: 402 strcpy(fp->name, AudioEslinear); 403 fp->encoding = AUDIO_ENCODING_SLINEAR; 404 fp->precision = 8; 405 fp->flags = 0; 406 break; 407 case 4: 408 strcpy(fp->name, AudioEslinear_le); 409 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 410 fp->precision = 16; 411 fp->flags = 0; 412 break; 413 case 5: 414 strcpy(fp->name, AudioEulinear_le); 415 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 416 fp->precision = 16; 417 fp->flags = 0; 418 break; 419 case 6: 420 strcpy(fp->name, AudioEslinear_be); 421 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 422 fp->precision = 16; 423 fp->flags = 0; 424 break; 425 case 7: 426 strcpy(fp->name, AudioEulinear_be); 427 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 428 fp->precision = 16; 429 fp->flags = 0; 430 break; 431 default: 432 return EINVAL; 433 } 434 return 0; 435 } 436 437 int 438 cs4281_set_params(addr, setmode, usemode, play, rec) 439 void *addr; 440 int setmode, usemode; 441 struct audio_params *play, *rec; 442 { 443 struct cs428x_softc *sc = addr; 444 struct audio_params *p; 445 int mode; 446 447 for (mode = AUMODE_RECORD; mode != -1; 448 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 449 if ((setmode & mode) == 0) 450 continue; 451 452 p = mode == AUMODE_PLAY ? play : rec; 453 454 if (p == play) { 455 DPRINTFN(5, ("play: sample=%ld precision=%d channels=%d\n", 456 p->sample_rate, p->precision, p->channels)); 457 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 458 (p->precision != 8 && p->precision != 16) || 459 (p->channels != 1 && p->channels != 2)) { 460 return (EINVAL); 461 } 462 } else { 463 DPRINTFN(5, ("rec: sample=%ld precision=%d channels=%d\n", 464 p->sample_rate, p->precision, p->channels)); 465 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 466 (p->precision != 8 && p->precision != 16) || 467 (p->channels != 1 && p->channels != 2)) { 468 return (EINVAL); 469 } 470 } 471 p->factor = 1; 472 p->sw_code = 0; 473 474 switch (p->encoding) { 475 case AUDIO_ENCODING_SLINEAR_BE: 476 break; 477 case AUDIO_ENCODING_SLINEAR_LE: 478 break; 479 case AUDIO_ENCODING_ULINEAR_BE: 480 break; 481 case AUDIO_ENCODING_ULINEAR_LE: 482 break; 483 case AUDIO_ENCODING_ULAW: 484 if (mode == AUMODE_PLAY) { 485 p->sw_code = mulaw_to_slinear8; 486 } else { 487 p->sw_code = slinear8_to_mulaw; 488 } 489 break; 490 case AUDIO_ENCODING_ALAW: 491 if (mode == AUMODE_PLAY) { 492 p->sw_code = alaw_to_slinear8; 493 } else { 494 p->sw_code = slinear8_to_alaw; 495 } 496 break; 497 default: 498 return (EINVAL); 499 } 500 } 501 502 /* set sample rate */ 503 cs4281_set_dac_rate(sc, play->sample_rate); 504 cs4281_set_adc_rate(sc, rec->sample_rate); 505 return 0; 506 } 507 508 int 509 cs4281_halt_output(addr) 510 void *addr; 511 { 512 struct cs428x_softc *sc = addr; 513 514 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 515 sc->sc_prun = 0; 516 return 0; 517 } 518 519 int 520 cs4281_halt_input(addr) 521 void *addr; 522 { 523 struct cs428x_softc *sc = addr; 524 525 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 526 sc->sc_rrun = 0; 527 return 0; 528 } 529 530 int 531 cs4281_getdev(addr, retp) 532 void *addr; 533 struct audio_device *retp; 534 { 535 536 *retp = cs4281_device; 537 return 0; 538 } 539 540 int 541 cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 542 void *addr; 543 void *start, *end; 544 int blksize; 545 void (*intr) __P((void *)); 546 void *arg; 547 struct audio_params *param; 548 { 549 struct cs428x_softc *sc = addr; 550 u_int32_t fmt=0; 551 struct cs428x_dma *p; 552 int dma_count; 553 554 #ifdef DIAGNOSTIC 555 if (sc->sc_prun) 556 printf("cs4281_trigger_output: already running\n"); 557 #endif 558 sc->sc_prun = 1; 559 560 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 561 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 562 sc->sc_pintr = intr; 563 sc->sc_parg = arg; 564 565 /* stop playback DMA */ 566 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 567 568 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 569 param->precision, param->factor, param->channels, 570 param->encoding)); 571 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 572 ; 573 if (p == NULL) { 574 printf("cs4281_trigger_output: bad addr %p\n", start); 575 return (EINVAL); 576 } 577 578 sc->sc_pcount = blksize / sc->hw_blocksize; 579 sc->sc_ps = (char *)start; 580 sc->sc_pe = (char *)end; 581 sc->sc_pdma = p; 582 sc->sc_pbuf = KERNADDR(p); 583 sc->sc_pi = 0; 584 sc->sc_pn = sc->sc_ps; 585 if (blksize >= sc->dma_size) { 586 sc->sc_pn = sc->sc_ps + sc->dma_size; 587 memcpy(sc->sc_pbuf, start, sc->dma_size); 588 ++sc->sc_pi; 589 } else { 590 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 591 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 592 } 593 594 dma_count = sc->dma_size; 595 if (param->precision * param->factor != 8) 596 dma_count /= 2; /* 16 bit */ 597 if (param->channels > 1) 598 dma_count /= 2; /* Stereo */ 599 600 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 601 (int)DMAADDR(p), dma_count)); 602 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 603 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 604 605 /* set playback format */ 606 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 607 if (param->precision * param->factor == 8) 608 fmt |= DMRn_SIZE8; 609 if (param->channels == 1) 610 fmt |= DMRn_MONO; 611 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 612 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 613 fmt |= DMRn_BEND; 614 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 615 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 616 fmt |= DMRn_USIGN; 617 BA0WRITE4(sc, CS4281_DMR0, fmt); 618 619 /* set sample rate */ 620 sc->sc_prate = param->sample_rate; 621 cs4281_set_dac_rate(sc, param->sample_rate); 622 623 /* start DMA */ 624 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 625 /* Enable interrupts */ 626 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 627 628 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 629 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 630 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 631 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 632 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 633 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 634 BA0READ4(sc, CS4281_DACSR))); 635 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 636 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 637 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 638 639 return 0; 640 } 641 642 int 643 cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 644 void *addr; 645 void *start, *end; 646 int blksize; 647 void (*intr) __P((void *)); 648 void *arg; 649 struct audio_params *param; 650 { 651 struct cs428x_softc *sc = addr; 652 struct cs428x_dma *p; 653 u_int32_t fmt=0; 654 int dma_count; 655 656 #ifdef DIAGNOSTIC 657 if (sc->sc_rrun) 658 printf("cs4281_trigger_input: already running\n"); 659 #endif 660 sc->sc_rrun = 1; 661 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 662 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 663 sc->sc_rintr = intr; 664 sc->sc_rarg = arg; 665 666 /* stop recording DMA */ 667 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 668 669 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 670 ; 671 if (!p) { 672 printf("cs4281_trigger_input: bad addr %p\n", start); 673 return (EINVAL); 674 } 675 676 sc->sc_rcount = blksize / sc->hw_blocksize; 677 sc->sc_rs = (char *)start; 678 sc->sc_re = (char *)end; 679 sc->sc_rdma = p; 680 sc->sc_rbuf = KERNADDR(p); 681 sc->sc_ri = 0; 682 sc->sc_rn = sc->sc_rs; 683 684 dma_count = sc->dma_size; 685 if (param->precision * param->factor == 8) 686 dma_count /= 2; 687 if (param->channels > 1) 688 dma_count /= 2; 689 690 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 691 (int)DMAADDR(p), dma_count)); 692 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 693 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 694 695 /* set recording format */ 696 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 697 if (param->precision * param->factor == 8) 698 fmt |= DMRn_SIZE8; 699 if (param->channels == 1) 700 fmt |= DMRn_MONO; 701 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 702 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 703 fmt |= DMRn_BEND; 704 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 705 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 706 fmt |= DMRn_USIGN; 707 BA0WRITE4(sc, CS4281_DMR1, fmt); 708 709 /* set sample rate */ 710 sc->sc_rrate = param->sample_rate; 711 cs4281_set_adc_rate(sc, param->sample_rate); 712 713 /* Start DMA */ 714 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 715 /* Enable interrupts */ 716 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 717 718 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 719 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 720 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 721 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 722 723 return 0; 724 } 725 726 /* Power Hook */ 727 void 728 cs4281_power(why, v) 729 int why; 730 void *v; 731 { 732 struct cs428x_softc *sc = (struct cs428x_softc *)v; 733 static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 734 static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 735 736 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 737 switch (why) { 738 case PWR_SUSPEND: 739 case PWR_STANDBY: 740 sc->sc_suspend = why; 741 742 /* save current playback status */ 743 if (sc->sc_prun) { 744 dcr0 = BA0READ4(sc, CS4281_DCR0); 745 dmr0 = BA0READ4(sc, CS4281_DMR0); 746 dbc0 = BA0READ4(sc, CS4281_DBC0); 747 dba0 = BA0READ4(sc, CS4281_DBA0); 748 } 749 750 /* save current capture status */ 751 if (sc->sc_rrun) { 752 dcr1 = BA0READ4(sc, CS4281_DCR1); 753 dmr1 = BA0READ4(sc, CS4281_DMR1); 754 dbc1 = BA0READ4(sc, CS4281_DBC1); 755 dba1 = BA0READ4(sc, CS4281_DBA1); 756 } 757 /* Stop DMA */ 758 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 759 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 760 break; 761 case PWR_RESUME: 762 if (sc->sc_suspend == PWR_RESUME) { 763 printf("cs4281_power: odd, resume without suspend.\n"); 764 sc->sc_suspend = why; 765 return; 766 } 767 sc->sc_suspend = why; 768 cs4281_init(sc, 0); 769 cs4281_reset_codec(sc); 770 771 /* restore ac97 registers */ 772 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 773 774 /* restore DMA related status */ 775 if (sc->sc_prun) { 776 cs4281_set_dac_rate(sc, sc->sc_prate); 777 BA0WRITE4(sc, CS4281_DBA0, dba0); 778 BA0WRITE4(sc, CS4281_DBC0, dbc0); 779 BA0WRITE4(sc, CS4281_DMR0, dmr0); 780 BA0WRITE4(sc, CS4281_DCR0, dcr0); 781 } 782 if (sc->sc_rrun) { 783 cs4281_set_adc_rate(sc, sc->sc_rrate); 784 BA0WRITE4(sc, CS4281_DBA1, dba1); 785 BA0WRITE4(sc, CS4281_DBC1, dbc1); 786 BA0WRITE4(sc, CS4281_DMR1, dmr1); 787 BA0WRITE4(sc, CS4281_DCR1, dcr1); 788 } 789 /* enable intterupts */ 790 if (sc->sc_prun || sc->sc_rrun) 791 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 792 break; 793 case PWR_SOFTSUSPEND: 794 case PWR_SOFTSTANDBY: 795 case PWR_SOFTRESUME: 796 break; 797 } 798 } 799 800 /* control AC97 codec */ 801 void 802 cs4281_reset_codec(void *addr) 803 { 804 struct cs428x_softc *sc; 805 u_int16_t data; 806 u_int32_t dat32; 807 int n; 808 809 sc = addr; 810 811 DPRINTFN(3, ("cs4281_reset_codec\n")); 812 813 /* Reset codec */ 814 BA0WRITE4(sc, CS428X_ACCTL, 0); 815 delay(50); /* delay 50us */ 816 817 BA0WRITE4(sc, CS4281_SPMC, 0); 818 delay(100); /* delay 100us */ 819 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 820 #if defined(ENABLE_SECONDARY_CODEC) 821 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 822 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 823 #endif 824 delay(50000); /* XXX: delay 50ms */ 825 826 /* Enable ASYNC generation */ 827 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 828 829 /* Wait for codec ready. Linux driver waits 50ms here */ 830 n = 0; 831 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 832 delay(100); 833 if (++n > 1000) { 834 printf("reset_codec: AC97 codec ready timeout\n"); 835 return; 836 } 837 } 838 #if defined(ENABLE_SECONDARY_CODEC) 839 /* secondary codec ready*/ 840 n = 0; 841 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 842 delay(100); 843 if (++n > 1000) 844 return; 845 } 846 #endif 847 /* Set the serial timing configuration */ 848 /* XXX: undocumented but the Linux driver do this */ 849 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 850 851 /* Wait for codec ready signal */ 852 n = 0; 853 do { 854 delay(1000); 855 if (++n > 1000) { 856 printf("%s: timeout waiting for codec ready\n", 857 sc->sc_dev.dv_xname); 858 return; 859 } 860 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 861 } while (dat32 == 0); 862 863 /* Enable Valid Frame output on ASDOUT */ 864 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 865 866 /* Wait until codec calibration is finished. Codec register 26h */ 867 n = 0; 868 do { 869 delay(1); 870 if (++n > 1000) { 871 printf("%s: timeout waiting for codec calibration\n", 872 sc->sc_dev.dv_xname); 873 return ; 874 } 875 cs428x_read_codec(sc, AC97_REG_POWER, &data); 876 } while ((data & 0x0f) != 0x0f); 877 878 /* Set the serial timing configuration again */ 879 /* XXX: undocumented but the Linux driver do this */ 880 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 881 882 /* Wait until we've sampled input slots 3 & 4 as valid */ 883 n = 0; 884 do { 885 delay(1000); 886 if (++n > 1000) { 887 printf("%s: timeout waiting for sampled input slots as valid\n", 888 sc->sc_dev.dv_xname); 889 return; 890 } 891 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 892 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 893 894 /* Start digital data transfer of audio data to the codec */ 895 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 896 } 897 898 899 /* Internal functions */ 900 901 /* convert sample rate to register value */ 902 u_int8_t 903 cs4281_sr2regval(rate) 904 int rate; 905 { 906 u_int8_t retval; 907 908 /* We don't have to change here. but anyway ... */ 909 if (rate > 48000) 910 rate = 48000; 911 if (rate < 6023) 912 rate = 6023; 913 914 switch (rate) { 915 case 8000: 916 retval = 5; 917 break; 918 case 11025: 919 retval = 4; 920 break; 921 case 16000: 922 retval = 3; 923 break; 924 case 22050: 925 retval = 2; 926 break; 927 case 44100: 928 retval = 1; 929 break; 930 case 48000: 931 retval = 0; 932 break; 933 default: 934 retval = 1536000/rate; /* == 24576000/(rate*16) */ 935 } 936 return retval; 937 } 938 939 void 940 cs4281_set_adc_rate(sc, rate) 941 struct cs428x_softc *sc; 942 int rate; 943 { 944 945 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 946 } 947 948 void 949 cs4281_set_dac_rate(sc, rate) 950 struct cs428x_softc *sc; 951 int rate; 952 { 953 954 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 955 } 956 957 int 958 cs4281_init(sc, init) 959 struct cs428x_softc *sc; 960 int init; 961 { 962 int n; 963 u_int16_t data; 964 u_int32_t dat32; 965 966 /* set "Configuration Write Protect" register to 967 * 0x4281 to allow to write */ 968 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 969 970 /* 971 * Unset "Full Power-Down bit of Extended PCI Power Management 972 * Control" register to release the reset state. 973 */ 974 dat32 = BA0READ4(sc, CS4281_EPPMC); 975 if (dat32 & EPPMC_FPDN) { 976 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 977 } 978 979 /* Start PLL out in known state */ 980 BA0WRITE4(sc, CS4281_CLKCR1, 0); 981 /* Start serial ports out in known state */ 982 BA0WRITE4(sc, CS4281_SERMC, 0); 983 984 /* Reset codec */ 985 BA0WRITE4(sc, CS428X_ACCTL, 0); 986 delay(50); /* delay 50us */ 987 988 BA0WRITE4(sc, CS4281_SPMC, 0); 989 delay(100); /* delay 100us */ 990 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 991 #if defined(ENABLE_SECONDARY_CODEC) 992 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 993 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 994 #endif 995 delay(50000); /* XXX: delay 50ms */ 996 997 /* Turn on Sound System clocks based on ABITCLK */ 998 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 999 delay(50000); /* XXX: delay 50ms */ 1000 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1001 1002 /* Set enables for sections that are needed in the SSPM registers */ 1003 BA0WRITE4(sc, CS4281_SSPM, 1004 SSPM_MIXEN | /* Mixer */ 1005 SSPM_CSRCEN | /* Capture SRC */ 1006 SSPM_PSRCEN | /* Playback SRC */ 1007 SSPM_JSEN | /* Joystick */ 1008 SSPM_ACLEN | /* AC LINK */ 1009 SSPM_FMEN /* FM */ 1010 ); 1011 1012 /* Wait for clock stabilization */ 1013 n = 0; 1014 #if 1 1015 /* what document says */ 1016 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1017 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1018 delay(100); 1019 if (++n > 1000) { 1020 printf("%s: timeout waiting for clock stabilization\n", 1021 sc->sc_dev.dv_xname); 1022 return -1; 1023 } 1024 } 1025 #else 1026 /* Cirrus driver for Linux does */ 1027 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1028 delay(1000); 1029 if (++n > 1000) { 1030 printf("%s: timeout waiting for clock stabilization\n", 1031 sc->sc_dev.dv_xname); 1032 return -1; 1033 } 1034 } 1035 #endif 1036 1037 /* Enable ASYNC generation */ 1038 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1039 1040 /* Wait for codec ready. Linux driver waits 50ms here */ 1041 n = 0; 1042 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1043 delay(100); 1044 if (++n > 1000) { 1045 printf("%s: timeout waiting for codec ready\n", 1046 sc->sc_dev.dv_xname); 1047 return -1; 1048 } 1049 } 1050 1051 #if defined(ENABLE_SECONDARY_CODEC) 1052 /* secondary codec ready*/ 1053 n = 0; 1054 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1055 delay(100); 1056 if (++n > 1000) { 1057 printf("%s: timeout waiting for secondary codec ready\n", 1058 sc->sc_dev.dv_xname); 1059 return -1; 1060 } 1061 } 1062 #endif 1063 1064 /* Set the serial timing configuration */ 1065 /* XXX: undocumented but the Linux driver do this */ 1066 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1067 1068 /* Wait for codec ready signal */ 1069 n = 0; 1070 do { 1071 delay(1000); 1072 if (++n > 1000) { 1073 printf("%s: timeout waiting for codec ready\n", 1074 sc->sc_dev.dv_xname); 1075 return -1; 1076 } 1077 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1078 } while (dat32 == 0); 1079 1080 /* Enable Valid Frame output on ASDOUT */ 1081 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1082 1083 /* Wait until codec calibration is finished. codec register 26h */ 1084 n = 0; 1085 do { 1086 delay(1); 1087 if (++n > 1000) { 1088 printf("%s: timeout waiting for codec calibration\n", 1089 sc->sc_dev.dv_xname); 1090 return -1; 1091 } 1092 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1093 } while ((data & 0x0f) != 0x0f); 1094 1095 /* Set the serial timing configuration again */ 1096 /* XXX: undocumented but the Linux driver do this */ 1097 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1098 1099 /* Wait until we've sampled input slots 3 & 4 as valid */ 1100 n = 0; 1101 do { 1102 delay(1000); 1103 if (++n > 1000) { 1104 printf("%s: timeout waiting for sampled input slots as valid\n", 1105 sc->sc_dev.dv_xname); 1106 return -1; 1107 } 1108 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1109 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1110 1111 /* Start digital data transfer of audio data to the codec */ 1112 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1113 1114 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1115 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1116 1117 /* Power on the DAC */ 1118 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1119 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1120 1121 /* Wait until we sample a DAC ready state. 1122 * Not documented, but Linux driver does. 1123 */ 1124 for (n = 0; n < 32; ++n) { 1125 delay(1000); 1126 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1127 if (data & 0x02) 1128 break; 1129 } 1130 1131 /* Power on the ADC */ 1132 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1133 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1134 1135 /* Wait until we sample ADC ready state. 1136 * Not documented, but Linux driver does. 1137 */ 1138 for (n = 0; n < 32; ++n) { 1139 delay(1000); 1140 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1141 if (data & 0x01) 1142 break; 1143 } 1144 1145 #if 0 1146 /* Initialize AC-Link features */ 1147 /* variable sample-rate support */ 1148 mem = BA0READ4(sc, CS4281_SERMC); 1149 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1150 BA0WRITE4(sc, CS4281_SERMC, mem); 1151 /* XXX: more... */ 1152 1153 /* Initialize SSCR register features */ 1154 /* XXX: hardware volume setting */ 1155 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1156 #endif 1157 1158 /* disable Sound Blaster Pro emulation */ 1159 /* XXX: 1160 * Cannot set since the documents does not describe which bit is 1161 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1162 * we can ignore it.*/ 1163 #if 0 1164 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1165 #endif 1166 1167 /* map AC97 PCM playback to DMA Channel 0 */ 1168 /* Reset FEN bit to setup first */ 1169 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1170 /* 1171 *| RS[4:0]/| | 1172 *| LS[4:0] | AC97 | Slot Function 1173 *|---------+--------+-------------------- 1174 *| 0 | 3 | Left PCM Playback 1175 *| 1 | 4 | Right PCM Playback 1176 *| 2 | 5 | Phone Line 1 DAC 1177 *| 3 | 6 | Center PCM Playback 1178 *.... 1179 * quoted from Table 29(p109) 1180 */ 1181 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1182 0x00 << 16 | /* LS[4:0] = 0 see above */ 1183 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1184 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1185 BA0WRITE4(sc, CS4281_FCR0, dat32); 1186 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1187 1188 /* map AC97 PCM record to DMA Channel 1 */ 1189 /* Reset FEN bit to setup first */ 1190 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1191 /* 1192 *| RS[4:0]/| 1193 *| LS[4:0] | AC97 | Slot Function 1194 *|---------+------+------------------- 1195 *| 10 | 3 | Left PCM Record 1196 *| 11 | 4 | Right PCM Record 1197 *| 12 | 5 | Phone Line 1 ADC 1198 *| 13 | 6 | Mic ADC 1199 *.... 1200 * quoted from Table 30(p109) 1201 */ 1202 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1203 0x0a << 16 | /* LS[4:0] = 10 See above */ 1204 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1205 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1206 1207 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1208 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1209 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1210 1211 #if 0 1212 /* Disable DMA Channel 2, 3 */ 1213 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1214 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1215 #endif 1216 1217 /* Set the SRC Slot Assignment accordingly */ 1218 /*| PLSS[4:0]/ 1219 *| PRSS[4:0] | AC97 | Slot Function 1220 *|-----------+------+---------------- 1221 *| 0 | 3 | Left PCM Playback 1222 *| 1 | 4 | Right PCM Playback 1223 *| 2 | 5 | phone line 1 DAC 1224 *| 3 | 6 | Center PCM Playback 1225 *| 4 | 7 | Left Surround PCM Playback 1226 *| 5 | 8 | Right Surround PCM Playback 1227 *...... 1228 * 1229 *| CLSS[4:0]/ 1230 *| CRSS[4:0] | AC97 | Codec |Slot Function 1231 *|-----------+------+-------+----------------- 1232 *| 10 | 3 |Primary| Left PCM Record 1233 *| 11 | 4 |Primary| Right PCM Record 1234 *| 12 | 5 |Primary| Phone Line 1 ADC 1235 *| 13 | 6 |Primary| Mic ADC 1236 *|..... 1237 *| 20 | 3 | Sec. | Left PCM Record 1238 *| 21 | 4 | Sec. | Right PCM Record 1239 *| 22 | 5 | Sec. | Phone Line 1 ADC 1240 *| 23 | 6 | Sec. | Mic ADC 1241 */ 1242 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1243 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1244 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1245 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1246 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1247 1248 /* Set interrupt to occurred at Half and Full terminal 1249 * count interrupt enable for DMA channel 0 and 1. 1250 * To keep DMA stop, set MSK. 1251 */ 1252 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1253 BA0WRITE4(sc, CS4281_DCR0, dat32); 1254 BA0WRITE4(sc, CS4281_DCR1, dat32); 1255 1256 /* Set Auto-Initialize Contorl enable */ 1257 BA0WRITE4(sc, CS4281_DMR0, 1258 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1259 BA0WRITE4(sc, CS4281_DMR1, 1260 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1261 1262 /* Clear DMA Mask in HIMR */ 1263 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1264 BA0WRITE4(sc, CS4281_HIMR, 1265 BA0READ4(sc, CS4281_HIMR) & dat32); 1266 1267 /* set current status */ 1268 if (init != 0) { 1269 sc->sc_prun = 0; 1270 sc->sc_rrun = 0; 1271 } 1272 1273 /* setup playback volume */ 1274 BA0WRITE4(sc, CS4281_PPRVC, 7); 1275 BA0WRITE4(sc, CS4281_PPLVC, 7); 1276 1277 return 0; 1278 } 1279
Indexes created Tue Sep 30 20:09:53 GMT 2025