cs4281.c revision 1.21.2.1
1 /* $NetBSD: cs4281.c,v 1.21.2.1 2005/01/02 20:03:11 kent Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.21.2.1 2005/01/02 20:03:11 kent Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 int cs4281_match(struct device *, struct cfdata *, void *); 84 void cs4281_attach(struct device *, struct device *, void *); 85 int cs4281_intr(void *); 86 int cs4281_query_encoding(void *, struct audio_encoding *); 87 int cs4281_set_params(void *, int, int, audio_params_t *, audio_params_t *, 88 stream_filter_list_t *, stream_filter_list_t *); 89 int cs4281_halt_output(void *); 90 int cs4281_halt_input(void *); 91 int cs4281_getdev(void *, struct audio_device *); 92 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 93 void *, const audio_params_t *); 94 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 95 void *, const audio_params_t *); 96 97 int cs4281_reset_codec(void *); 98 99 /* Internal functions */ 100 u_int8_t cs4281_sr2regval(int); 101 void cs4281_set_dac_rate(struct cs428x_softc *, int); 102 void cs4281_set_adc_rate(struct cs428x_softc *, int); 103 int cs4281_init(struct cs428x_softc *, int); 104 105 /* Power Management */ 106 void cs4281_power(int, void *); 107 108 const struct audio_hw_if cs4281_hw_if = { 109 cs428x_open, 110 cs428x_close, 111 NULL, 112 cs4281_query_encoding, 113 cs4281_set_params, 114 cs428x_round_blocksize, 115 NULL, 116 NULL, 117 NULL, 118 NULL, 119 NULL, 120 cs4281_halt_output, 121 cs4281_halt_input, 122 NULL, 123 cs4281_getdev, 124 NULL, 125 cs428x_mixer_set_port, 126 cs428x_mixer_get_port, 127 cs428x_query_devinfo, 128 cs428x_malloc, 129 cs428x_free, 130 cs428x_round_buffersize, 131 cs428x_mappage, 132 cs428x_get_props, 133 cs4281_trigger_output, 134 cs4281_trigger_input, 135 NULL, 136 }; 137 138 #if NMIDI > 0 && 0 139 /* Midi Interface */ 140 void cs4281_midi_close(void*); 141 void cs4281_midi_getinfo(void *, struct midi_info *); 142 int cs4281_midi_open(void *, int, void (*)(void *, int), 143 void (*)(void *), void *); 144 int cs4281_midi_output(void *, int); 145 146 const struct midi_hw_if cs4281_midi_hw_if = { 147 cs4281_midi_open, 148 cs4281_midi_close, 149 cs4281_midi_output, 150 cs4281_midi_getinfo, 151 0, 152 }; 153 #endif 154 155 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 156 cs4281_match, cs4281_attach, NULL, NULL); 157 158 struct audio_device cs4281_device = { 159 "CS4281", 160 "", 161 "cs4281" 162 }; 163 164 165 int 166 cs4281_match(parent, match, aux) 167 struct device *parent; 168 struct cfdata *match; 169 void *aux; 170 { 171 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 172 173 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 174 return 0; 175 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 176 return 1; 177 return 0; 178 } 179 180 void 181 cs4281_attach(parent, self, aux) 182 struct device *parent; 183 struct device *self; 184 void *aux; 185 { 186 struct cs428x_softc *sc = (struct cs428x_softc *)self; 187 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 char const *intrstr; 190 pci_intr_handle_t ih; 191 pcireg_t reg; 192 char devinfo[256]; 193 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 194 195 aprint_naive(": Audio controller\n"); 196 197 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 198 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 199 PCI_REVISION(pa->pa_class)); 200 201 /* Map I/O register */ 202 if (pci_mapreg_map(pa, PCI_BA0, 203 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 204 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 205 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 206 return; 207 } 208 if (pci_mapreg_map(pa, PCI_BA1, 209 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 210 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 211 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 212 return; 213 } 214 215 sc->sc_dmatag = pa->pa_dmat; 216 217 /* 218 * Set Power State D0. 219 * Without do this, 0xffffffff is read from all registers after 220 * using Windows. 221 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 222 */ 223 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 224 &pci_pwrmgmt_cap_reg, 0)) { 225 226 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 227 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 228 pci_pwrmgmt_csr_reg); 229 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 230 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 231 (reg & ~PCI_PMCSR_STATE_MASK) | 232 PCI_PMCSR_STATE_D0); 233 } 234 } 235 236 /* Enable the device (set bus master flag) */ 237 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 238 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 239 reg | PCI_COMMAND_MASTER_ENABLE); 240 241 #if 0 242 /* LATENCY_TIMER setting */ 243 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 244 if (PCI_LATTIMER(temp1) < 32) { 245 temp1 &= 0xffff00ff; 246 temp1 |= 0x00002000; 247 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 248 } 249 #endif 250 251 /* Map and establish the interrupt. */ 252 if (pci_intr_map(pa, &ih)) { 253 aprint_error("%s: couldn't map interrupt\n", 254 sc->sc_dev.dv_xname); 255 return; 256 } 257 intrstr = pci_intr_string(pc, ih); 258 259 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 260 if (sc->sc_ih == NULL) { 261 aprint_error("%s: couldn't establish interrupt", 262 sc->sc_dev.dv_xname); 263 if (intrstr != NULL) 264 aprint_normal(" at %s", intrstr); 265 aprint_normal("\n"); 266 return; 267 } 268 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 269 270 /* 271 * Sound System start-up 272 */ 273 if (cs4281_init(sc, 1) != 0) 274 return; 275 276 sc->type = TYPE_CS4281; 277 sc->halt_input = cs4281_halt_input; 278 sc->halt_output = cs4281_halt_output; 279 280 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 281 sc->dma_align = 0x10; 282 sc->hw_blocksize = sc->dma_size / 2; 283 284 /* AC 97 attachment */ 285 sc->host_if.arg = sc; 286 sc->host_if.attach = cs428x_attach_codec; 287 sc->host_if.read = cs428x_read_codec; 288 sc->host_if.write = cs428x_write_codec; 289 sc->host_if.reset = cs4281_reset_codec; 290 if (ac97_attach(&sc->host_if, self) != 0) { 291 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 292 return; 293 } 294 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 295 296 #if NMIDI > 0 && 0 297 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 298 #endif 299 300 sc->sc_suspend = PWR_RESUME; 301 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 302 } 303 304 int 305 cs4281_intr(p) 306 void *p; 307 { 308 struct cs428x_softc *sc = p; 309 u_int32_t intr, hdsr0, hdsr1; 310 char *empty_dma; 311 int handled = 0; 312 313 hdsr0 = 0; 314 hdsr1 = 0; 315 316 /* grab interrupt register */ 317 intr = BA0READ4(sc, CS4281_HISR); 318 319 DPRINTF(("cs4281_intr:")); 320 /* not for me */ 321 if ((intr & HISR_INTENA) == 0) { 322 /* clear the interrupt register */ 323 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 324 return 0; 325 } 326 327 if (intr & HISR_DMA0) 328 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 329 if (intr & HISR_DMA1) 330 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 331 /* clear the interrupt register */ 332 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 333 334 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 335 intr, hdsr0, hdsr1)); 336 337 /* Playback Interrupt */ 338 if (intr & HISR_DMA0) { 339 handled = 1; 340 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 341 (int)BA0READ4(sc, CS4281_DCC0))); 342 if (sc->sc_prun) { 343 if ((sc->sc_pi%sc->sc_pcount) == 0) 344 sc->sc_pintr(sc->sc_parg); 345 } else { 346 printf("unexpected play intr\n"); 347 } 348 /* copy buffer */ 349 ++sc->sc_pi; 350 empty_dma = sc->sc_pdma->addr; 351 if (sc->sc_pi&1) 352 empty_dma += sc->hw_blocksize; 353 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 354 sc->sc_pn += sc->hw_blocksize; 355 if (sc->sc_pn >= sc->sc_pe) 356 sc->sc_pn = sc->sc_ps; 357 } 358 if (intr & HISR_DMA1) { 359 handled = 1; 360 /* copy from DMA */ 361 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 362 (int)BA0READ4(sc, CS4281_DCC1))); 363 ++sc->sc_ri; 364 empty_dma = sc->sc_rdma->addr; 365 if ((sc->sc_ri & 1) == 0) 366 empty_dma += sc->hw_blocksize; 367 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 368 sc->sc_rn += sc->hw_blocksize; 369 if (sc->sc_rn >= sc->sc_re) 370 sc->sc_rn = sc->sc_rs; 371 if (sc->sc_rrun) { 372 if ((sc->sc_ri % sc->sc_rcount) == 0) 373 sc->sc_rintr(sc->sc_rarg); 374 } else { 375 printf("unexpected record intr\n"); 376 } 377 } 378 DPRINTF(("\n")); 379 380 return handled; 381 } 382 383 int 384 cs4281_query_encoding(addr, fp) 385 void *addr; 386 struct audio_encoding *fp; 387 { 388 389 switch (fp->index) { 390 case 0: 391 strcpy(fp->name, AudioEulinear); 392 fp->encoding = AUDIO_ENCODING_ULINEAR; 393 fp->precision = 8; 394 fp->flags = 0; 395 break; 396 case 1: 397 strcpy(fp->name, AudioEmulaw); 398 fp->encoding = AUDIO_ENCODING_ULAW; 399 fp->precision = 8; 400 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 401 break; 402 case 2: 403 strcpy(fp->name, AudioEalaw); 404 fp->encoding = AUDIO_ENCODING_ALAW; 405 fp->precision = 8; 406 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 407 break; 408 case 3: 409 strcpy(fp->name, AudioEslinear); 410 fp->encoding = AUDIO_ENCODING_SLINEAR; 411 fp->precision = 8; 412 fp->flags = 0; 413 break; 414 case 4: 415 strcpy(fp->name, AudioEslinear_le); 416 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 417 fp->precision = 16; 418 fp->flags = 0; 419 break; 420 case 5: 421 strcpy(fp->name, AudioEulinear_le); 422 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 423 fp->precision = 16; 424 fp->flags = 0; 425 break; 426 case 6: 427 strcpy(fp->name, AudioEslinear_be); 428 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 429 fp->precision = 16; 430 fp->flags = 0; 431 break; 432 case 7: 433 strcpy(fp->name, AudioEulinear_be); 434 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 435 fp->precision = 16; 436 fp->flags = 0; 437 break; 438 default: 439 return EINVAL; 440 } 441 return 0; 442 } 443 444 int 445 cs4281_set_params(void *addr, int setmode, int usemode, 446 audio_params_t *play, audio_params_t *rec, 447 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 448 { 449 audio_params_t hw; 450 struct cs428x_softc *sc = addr; 451 audio_params_t *p; 452 stream_filter_list_t *fil; 453 int mode; 454 455 for (mode = AUMODE_RECORD; mode != -1; 456 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 457 if ((setmode & mode) == 0) 458 continue; 459 460 p = mode == AUMODE_PLAY ? play : rec; 461 462 if (p == play) { 463 DPRINTFN(5, ("play: sample=%ld precision=%d channels=%d\n", 464 p->sample_rate, p->precision, p->channels)); 465 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 466 (p->precision != 8 && p->precision != 16) || 467 (p->channels != 1 && p->channels != 2)) { 468 return (EINVAL); 469 } 470 } else { 471 DPRINTFN(5, ("rec: sample=%ld precision=%d channels=%d\n", 472 p->sample_rate, p->precision, p->channels)); 473 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 474 (p->precision != 8 && p->precision != 16) || 475 (p->channels != 1 && p->channels != 2)) { 476 return (EINVAL); 477 } 478 } 479 hw = *p; 480 fil = mode == AUMODE_PLAY ? pfil : rfil; 481 482 switch (p->encoding) { 483 case AUDIO_ENCODING_SLINEAR_BE: 484 break; 485 case AUDIO_ENCODING_SLINEAR_LE: 486 break; 487 case AUDIO_ENCODING_ULINEAR_BE: 488 break; 489 case AUDIO_ENCODING_ULINEAR_LE: 490 break; 491 case AUDIO_ENCODING_ULAW: 492 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 493 stream_filter_list_append 494 (fil, mode == AUMODE_PLAY ? mulaw_to_linear8 495 : linear8_to_mulaw, &hw); 496 break; 497 case AUDIO_ENCODING_ALAW: 498 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 499 stream_filter_list_append 500 (fil, mode == AUMODE_PLAY ? alaw_to_linear8 501 : linear8_to_alaw, &hw); 502 break; 503 default: 504 return (EINVAL); 505 } 506 } 507 508 /* set sample rate */ 509 cs4281_set_dac_rate(sc, play->sample_rate); 510 cs4281_set_adc_rate(sc, rec->sample_rate); 511 return 0; 512 } 513 514 int 515 cs4281_halt_output(addr) 516 void *addr; 517 { 518 struct cs428x_softc *sc = addr; 519 520 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 521 sc->sc_prun = 0; 522 return 0; 523 } 524 525 int 526 cs4281_halt_input(addr) 527 void *addr; 528 { 529 struct cs428x_softc *sc = addr; 530 531 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 532 sc->sc_rrun = 0; 533 return 0; 534 } 535 536 int 537 cs4281_getdev(addr, retp) 538 void *addr; 539 struct audio_device *retp; 540 { 541 542 *retp = cs4281_device; 543 return 0; 544 } 545 546 int 547 cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 548 void *addr; 549 void *start, *end; 550 int blksize; 551 void (*intr) __P((void *)); 552 void *arg; 553 const audio_params_t *param; 554 { 555 struct cs428x_softc *sc = addr; 556 u_int32_t fmt=0; 557 struct cs428x_dma *p; 558 int dma_count; 559 560 #ifdef DIAGNOSTIC 561 if (sc->sc_prun) 562 printf("cs4281_trigger_output: already running\n"); 563 #endif 564 sc->sc_prun = 1; 565 566 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 567 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 568 sc->sc_pintr = intr; 569 sc->sc_parg = arg; 570 571 /* stop playback DMA */ 572 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 573 574 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 575 param->precision, param->channels, param->encoding)); 576 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 577 ; 578 if (p == NULL) { 579 printf("cs4281_trigger_output: bad addr %p\n", start); 580 return (EINVAL); 581 } 582 583 sc->sc_pcount = blksize / sc->hw_blocksize; 584 sc->sc_ps = (char *)start; 585 sc->sc_pe = (char *)end; 586 sc->sc_pdma = p; 587 sc->sc_pbuf = KERNADDR(p); 588 sc->sc_pi = 0; 589 sc->sc_pn = sc->sc_ps; 590 if (blksize >= sc->dma_size) { 591 sc->sc_pn = sc->sc_ps + sc->dma_size; 592 memcpy(sc->sc_pbuf, start, sc->dma_size); 593 ++sc->sc_pi; 594 } else { 595 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 596 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 597 } 598 599 dma_count = sc->dma_size; 600 if (param->precision != 8) 601 dma_count /= 2; /* 16 bit */ 602 if (param->channels > 1) 603 dma_count /= 2; /* Stereo */ 604 605 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 606 (int)DMAADDR(p), dma_count)); 607 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 608 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 609 610 /* set playback format */ 611 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 612 if (param->precision == 8) 613 fmt |= DMRn_SIZE8; 614 if (param->channels == 1) 615 fmt |= DMRn_MONO; 616 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 617 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 618 fmt |= DMRn_BEND; 619 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 620 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 621 fmt |= DMRn_USIGN; 622 BA0WRITE4(sc, CS4281_DMR0, fmt); 623 624 /* set sample rate */ 625 sc->sc_prate = param->sample_rate; 626 cs4281_set_dac_rate(sc, param->sample_rate); 627 628 /* start DMA */ 629 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 630 /* Enable interrupts */ 631 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 632 633 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 634 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 635 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 636 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 637 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 638 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 639 BA0READ4(sc, CS4281_DACSR))); 640 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 641 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 642 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 643 644 return 0; 645 } 646 647 int 648 cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 649 void *addr; 650 void *start, *end; 651 int blksize; 652 void (*intr) __P((void *)); 653 void *arg; 654 const audio_params_t *param; 655 { 656 struct cs428x_softc *sc = addr; 657 struct cs428x_dma *p; 658 u_int32_t fmt=0; 659 int dma_count; 660 661 #ifdef DIAGNOSTIC 662 if (sc->sc_rrun) 663 printf("cs4281_trigger_input: already running\n"); 664 #endif 665 sc->sc_rrun = 1; 666 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 667 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 668 sc->sc_rintr = intr; 669 sc->sc_rarg = arg; 670 671 /* stop recording DMA */ 672 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 673 674 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 675 ; 676 if (!p) { 677 printf("cs4281_trigger_input: bad addr %p\n", start); 678 return (EINVAL); 679 } 680 681 sc->sc_rcount = blksize / sc->hw_blocksize; 682 sc->sc_rs = (char *)start; 683 sc->sc_re = (char *)end; 684 sc->sc_rdma = p; 685 sc->sc_rbuf = KERNADDR(p); 686 sc->sc_ri = 0; 687 sc->sc_rn = sc->sc_rs; 688 689 dma_count = sc->dma_size; 690 if (param->precision != 8) 691 dma_count /= 2; 692 if (param->channels > 1) 693 dma_count /= 2; 694 695 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 696 (int)DMAADDR(p), dma_count)); 697 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 698 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 699 700 /* set recording format */ 701 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 702 if (param->precision == 8) 703 fmt |= DMRn_SIZE8; 704 if (param->channels == 1) 705 fmt |= DMRn_MONO; 706 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 707 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 708 fmt |= DMRn_BEND; 709 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 710 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 711 fmt |= DMRn_USIGN; 712 BA0WRITE4(sc, CS4281_DMR1, fmt); 713 714 /* set sample rate */ 715 sc->sc_rrate = param->sample_rate; 716 cs4281_set_adc_rate(sc, param->sample_rate); 717 718 /* Start DMA */ 719 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 720 /* Enable interrupts */ 721 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 722 723 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 724 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 725 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 726 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 727 728 return 0; 729 } 730 731 /* Power Hook */ 732 void 733 cs4281_power(why, v) 734 int why; 735 void *v; 736 { 737 struct cs428x_softc *sc = (struct cs428x_softc *)v; 738 static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 739 static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 740 741 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 742 switch (why) { 743 case PWR_SUSPEND: 744 case PWR_STANDBY: 745 sc->sc_suspend = why; 746 747 /* save current playback status */ 748 if (sc->sc_prun) { 749 dcr0 = BA0READ4(sc, CS4281_DCR0); 750 dmr0 = BA0READ4(sc, CS4281_DMR0); 751 dbc0 = BA0READ4(sc, CS4281_DBC0); 752 dba0 = BA0READ4(sc, CS4281_DBA0); 753 } 754 755 /* save current capture status */ 756 if (sc->sc_rrun) { 757 dcr1 = BA0READ4(sc, CS4281_DCR1); 758 dmr1 = BA0READ4(sc, CS4281_DMR1); 759 dbc1 = BA0READ4(sc, CS4281_DBC1); 760 dba1 = BA0READ4(sc, CS4281_DBA1); 761 } 762 /* Stop DMA */ 763 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 764 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 765 break; 766 case PWR_RESUME: 767 if (sc->sc_suspend == PWR_RESUME) { 768 printf("cs4281_power: odd, resume without suspend.\n"); 769 sc->sc_suspend = why; 770 return; 771 } 772 sc->sc_suspend = why; 773 cs4281_init(sc, 0); 774 cs4281_reset_codec(sc); 775 776 /* restore ac97 registers */ 777 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 778 779 /* restore DMA related status */ 780 if (sc->sc_prun) { 781 cs4281_set_dac_rate(sc, sc->sc_prate); 782 BA0WRITE4(sc, CS4281_DBA0, dba0); 783 BA0WRITE4(sc, CS4281_DBC0, dbc0); 784 BA0WRITE4(sc, CS4281_DMR0, dmr0); 785 BA0WRITE4(sc, CS4281_DCR0, dcr0); 786 } 787 if (sc->sc_rrun) { 788 cs4281_set_adc_rate(sc, sc->sc_rrate); 789 BA0WRITE4(sc, CS4281_DBA1, dba1); 790 BA0WRITE4(sc, CS4281_DBC1, dbc1); 791 BA0WRITE4(sc, CS4281_DMR1, dmr1); 792 BA0WRITE4(sc, CS4281_DCR1, dcr1); 793 } 794 /* enable intterupts */ 795 if (sc->sc_prun || sc->sc_rrun) 796 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 797 break; 798 case PWR_SOFTSUSPEND: 799 case PWR_SOFTSTANDBY: 800 case PWR_SOFTRESUME: 801 break; 802 } 803 } 804 805 /* control AC97 codec */ 806 int 807 cs4281_reset_codec(void *addr) 808 { 809 struct cs428x_softc *sc; 810 u_int16_t data; 811 u_int32_t dat32; 812 int n; 813 814 sc = addr; 815 816 DPRINTFN(3, ("cs4281_reset_codec\n")); 817 818 /* Reset codec */ 819 BA0WRITE4(sc, CS428X_ACCTL, 0); 820 delay(50); /* delay 50us */ 821 822 BA0WRITE4(sc, CS4281_SPMC, 0); 823 delay(100); /* delay 100us */ 824 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 825 #if defined(ENABLE_SECONDARY_CODEC) 826 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 827 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 828 #endif 829 delay(50000); /* XXX: delay 50ms */ 830 831 /* Enable ASYNC generation */ 832 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 833 834 /* Wait for codec ready. Linux driver waits 50ms here */ 835 n = 0; 836 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 837 delay(100); 838 if (++n > 1000) { 839 printf("reset_codec: AC97 codec ready timeout\n"); 840 return ETIMEDOUT; 841 } 842 } 843 #if defined(ENABLE_SECONDARY_CODEC) 844 /* secondary codec ready*/ 845 n = 0; 846 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 847 delay(100); 848 if (++n > 1000) 849 return 0; 850 } 851 #endif 852 /* Set the serial timing configuration */ 853 /* XXX: undocumented but the Linux driver do this */ 854 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 855 856 /* Wait for codec ready signal */ 857 n = 0; 858 do { 859 delay(1000); 860 if (++n > 1000) { 861 printf("%s: timeout waiting for codec ready\n", 862 sc->sc_dev.dv_xname); 863 return ETIMEDOUT; 864 } 865 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 866 } while (dat32 == 0); 867 868 /* Enable Valid Frame output on ASDOUT */ 869 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 870 871 /* Wait until codec calibration is finished. Codec register 26h */ 872 n = 0; 873 do { 874 delay(1); 875 if (++n > 1000) { 876 printf("%s: timeout waiting for codec calibration\n", 877 sc->sc_dev.dv_xname); 878 return ETIMEDOUT; 879 } 880 cs428x_read_codec(sc, AC97_REG_POWER, &data); 881 } while ((data & 0x0f) != 0x0f); 882 883 /* Set the serial timing configuration again */ 884 /* XXX: undocumented but the Linux driver do this */ 885 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 886 887 /* Wait until we've sampled input slots 3 & 4 as valid */ 888 n = 0; 889 do { 890 delay(1000); 891 if (++n > 1000) { 892 printf("%s: timeout waiting for sampled input slots as valid\n", 893 sc->sc_dev.dv_xname); 894 return ETIMEDOUT; 895 } 896 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 897 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 898 899 /* Start digital data transfer of audio data to the codec */ 900 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 901 return 0; 902 } 903 904 905 /* Internal functions */ 906 907 /* convert sample rate to register value */ 908 u_int8_t 909 cs4281_sr2regval(rate) 910 int rate; 911 { 912 u_int8_t retval; 913 914 /* We don't have to change here. but anyway ... */ 915 if (rate > 48000) 916 rate = 48000; 917 if (rate < 6023) 918 rate = 6023; 919 920 switch (rate) { 921 case 8000: 922 retval = 5; 923 break; 924 case 11025: 925 retval = 4; 926 break; 927 case 16000: 928 retval = 3; 929 break; 930 case 22050: 931 retval = 2; 932 break; 933 case 44100: 934 retval = 1; 935 break; 936 case 48000: 937 retval = 0; 938 break; 939 default: 940 retval = 1536000/rate; /* == 24576000/(rate*16) */ 941 } 942 return retval; 943 } 944 945 void 946 cs4281_set_adc_rate(sc, rate) 947 struct cs428x_softc *sc; 948 int rate; 949 { 950 951 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 952 } 953 954 void 955 cs4281_set_dac_rate(sc, rate) 956 struct cs428x_softc *sc; 957 int rate; 958 { 959 960 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 961 } 962 963 int 964 cs4281_init(sc, init) 965 struct cs428x_softc *sc; 966 int init; 967 { 968 int n; 969 u_int16_t data; 970 u_int32_t dat32; 971 972 /* set "Configuration Write Protect" register to 973 * 0x4281 to allow to write */ 974 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 975 976 /* 977 * Unset "Full Power-Down bit of Extended PCI Power Management 978 * Control" register to release the reset state. 979 */ 980 dat32 = BA0READ4(sc, CS4281_EPPMC); 981 if (dat32 & EPPMC_FPDN) { 982 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 983 } 984 985 /* Start PLL out in known state */ 986 BA0WRITE4(sc, CS4281_CLKCR1, 0); 987 /* Start serial ports out in known state */ 988 BA0WRITE4(sc, CS4281_SERMC, 0); 989 990 /* Reset codec */ 991 BA0WRITE4(sc, CS428X_ACCTL, 0); 992 delay(50); /* delay 50us */ 993 994 BA0WRITE4(sc, CS4281_SPMC, 0); 995 delay(100); /* delay 100us */ 996 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 997 #if defined(ENABLE_SECONDARY_CODEC) 998 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 999 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 1000 #endif 1001 delay(50000); /* XXX: delay 50ms */ 1002 1003 /* Turn on Sound System clocks based on ABITCLK */ 1004 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 1005 delay(50000); /* XXX: delay 50ms */ 1006 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1007 1008 /* Set enables for sections that are needed in the SSPM registers */ 1009 BA0WRITE4(sc, CS4281_SSPM, 1010 SSPM_MIXEN | /* Mixer */ 1011 SSPM_CSRCEN | /* Capture SRC */ 1012 SSPM_PSRCEN | /* Playback SRC */ 1013 SSPM_JSEN | /* Joystick */ 1014 SSPM_ACLEN | /* AC LINK */ 1015 SSPM_FMEN /* FM */ 1016 ); 1017 1018 /* Wait for clock stabilization */ 1019 n = 0; 1020 #if 1 1021 /* what document says */ 1022 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1023 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1024 delay(100); 1025 if (++n > 1000) { 1026 printf("%s: timeout waiting for clock stabilization\n", 1027 sc->sc_dev.dv_xname); 1028 return -1; 1029 } 1030 } 1031 #else 1032 /* Cirrus driver for Linux does */ 1033 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1034 delay(1000); 1035 if (++n > 1000) { 1036 printf("%s: timeout waiting for clock stabilization\n", 1037 sc->sc_dev.dv_xname); 1038 return -1; 1039 } 1040 } 1041 #endif 1042 1043 /* Enable ASYNC generation */ 1044 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1045 1046 /* Wait for codec ready. Linux driver waits 50ms here */ 1047 n = 0; 1048 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1049 delay(100); 1050 if (++n > 1000) { 1051 printf("%s: timeout waiting for codec ready\n", 1052 sc->sc_dev.dv_xname); 1053 return -1; 1054 } 1055 } 1056 1057 #if defined(ENABLE_SECONDARY_CODEC) 1058 /* secondary codec ready*/ 1059 n = 0; 1060 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1061 delay(100); 1062 if (++n > 1000) { 1063 printf("%s: timeout waiting for secondary codec ready\n", 1064 sc->sc_dev.dv_xname); 1065 return -1; 1066 } 1067 } 1068 #endif 1069 1070 /* Set the serial timing configuration */ 1071 /* XXX: undocumented but the Linux driver do this */ 1072 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1073 1074 /* Wait for codec ready signal */ 1075 n = 0; 1076 do { 1077 delay(1000); 1078 if (++n > 1000) { 1079 printf("%s: timeout waiting for codec ready\n", 1080 sc->sc_dev.dv_xname); 1081 return -1; 1082 } 1083 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1084 } while (dat32 == 0); 1085 1086 /* Enable Valid Frame output on ASDOUT */ 1087 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1088 1089 /* Wait until codec calibration is finished. codec register 26h */ 1090 n = 0; 1091 do { 1092 delay(1); 1093 if (++n > 1000) { 1094 printf("%s: timeout waiting for codec calibration\n", 1095 sc->sc_dev.dv_xname); 1096 return -1; 1097 } 1098 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1099 } while ((data & 0x0f) != 0x0f); 1100 1101 /* Set the serial timing configuration again */ 1102 /* XXX: undocumented but the Linux driver do this */ 1103 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1104 1105 /* Wait until we've sampled input slots 3 & 4 as valid */ 1106 n = 0; 1107 do { 1108 delay(1000); 1109 if (++n > 1000) { 1110 printf("%s: timeout waiting for sampled input slots as valid\n", 1111 sc->sc_dev.dv_xname); 1112 return -1; 1113 } 1114 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1115 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1116 1117 /* Start digital data transfer of audio data to the codec */ 1118 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1119 1120 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1121 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1122 1123 /* Power on the DAC */ 1124 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1125 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1126 1127 /* Wait until we sample a DAC ready state. 1128 * Not documented, but Linux driver does. 1129 */ 1130 for (n = 0; n < 32; ++n) { 1131 delay(1000); 1132 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1133 if (data & 0x02) 1134 break; 1135 } 1136 1137 /* Power on the ADC */ 1138 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1139 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1140 1141 /* Wait until we sample ADC ready state. 1142 * Not documented, but Linux driver does. 1143 */ 1144 for (n = 0; n < 32; ++n) { 1145 delay(1000); 1146 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1147 if (data & 0x01) 1148 break; 1149 } 1150 1151 #if 0 1152 /* Initialize AC-Link features */ 1153 /* variable sample-rate support */ 1154 mem = BA0READ4(sc, CS4281_SERMC); 1155 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1156 BA0WRITE4(sc, CS4281_SERMC, mem); 1157 /* XXX: more... */ 1158 1159 /* Initialize SSCR register features */ 1160 /* XXX: hardware volume setting */ 1161 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1162 #endif 1163 1164 /* disable Sound Blaster Pro emulation */ 1165 /* XXX: 1166 * Cannot set since the documents does not describe which bit is 1167 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1168 * we can ignore it.*/ 1169 #if 0 1170 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1171 #endif 1172 1173 /* map AC97 PCM playback to DMA Channel 0 */ 1174 /* Reset FEN bit to setup first */ 1175 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1176 /* 1177 *| RS[4:0]/| | 1178 *| LS[4:0] | AC97 | Slot Function 1179 *|---------+--------+-------------------- 1180 *| 0 | 3 | Left PCM Playback 1181 *| 1 | 4 | Right PCM Playback 1182 *| 2 | 5 | Phone Line 1 DAC 1183 *| 3 | 6 | Center PCM Playback 1184 *.... 1185 * quoted from Table 29(p109) 1186 */ 1187 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1188 0x00 << 16 | /* LS[4:0] = 0 see above */ 1189 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1190 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1191 BA0WRITE4(sc, CS4281_FCR0, dat32); 1192 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1193 1194 /* map AC97 PCM record to DMA Channel 1 */ 1195 /* Reset FEN bit to setup first */ 1196 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1197 /* 1198 *| RS[4:0]/| 1199 *| LS[4:0] | AC97 | Slot Function 1200 *|---------+------+------------------- 1201 *| 10 | 3 | Left PCM Record 1202 *| 11 | 4 | Right PCM Record 1203 *| 12 | 5 | Phone Line 1 ADC 1204 *| 13 | 6 | Mic ADC 1205 *.... 1206 * quoted from Table 30(p109) 1207 */ 1208 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1209 0x0a << 16 | /* LS[4:0] = 10 See above */ 1210 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1211 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1212 1213 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1214 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1215 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1216 1217 #if 0 1218 /* Disable DMA Channel 2, 3 */ 1219 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1220 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1221 #endif 1222 1223 /* Set the SRC Slot Assignment accordingly */ 1224 /*| PLSS[4:0]/ 1225 *| PRSS[4:0] | AC97 | Slot Function 1226 *|-----------+------+---------------- 1227 *| 0 | 3 | Left PCM Playback 1228 *| 1 | 4 | Right PCM Playback 1229 *| 2 | 5 | phone line 1 DAC 1230 *| 3 | 6 | Center PCM Playback 1231 *| 4 | 7 | Left Surround PCM Playback 1232 *| 5 | 8 | Right Surround PCM Playback 1233 *...... 1234 * 1235 *| CLSS[4:0]/ 1236 *| CRSS[4:0] | AC97 | Codec |Slot Function 1237 *|-----------+------+-------+----------------- 1238 *| 10 | 3 |Primary| Left PCM Record 1239 *| 11 | 4 |Primary| Right PCM Record 1240 *| 12 | 5 |Primary| Phone Line 1 ADC 1241 *| 13 | 6 |Primary| Mic ADC 1242 *|..... 1243 *| 20 | 3 | Sec. | Left PCM Record 1244 *| 21 | 4 | Sec. | Right PCM Record 1245 *| 22 | 5 | Sec. | Phone Line 1 ADC 1246 *| 23 | 6 | Sec. | Mic ADC 1247 */ 1248 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1249 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1250 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1251 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1252 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1253 1254 /* Set interrupt to occurred at Half and Full terminal 1255 * count interrupt enable for DMA channel 0 and 1. 1256 * To keep DMA stop, set MSK. 1257 */ 1258 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1259 BA0WRITE4(sc, CS4281_DCR0, dat32); 1260 BA0WRITE4(sc, CS4281_DCR1, dat32); 1261 1262 /* Set Auto-Initialize Contorl enable */ 1263 BA0WRITE4(sc, CS4281_DMR0, 1264 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1265 BA0WRITE4(sc, CS4281_DMR1, 1266 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1267 1268 /* Clear DMA Mask in HIMR */ 1269 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1270 BA0WRITE4(sc, CS4281_HIMR, 1271 BA0READ4(sc, CS4281_HIMR) & dat32); 1272 1273 /* set current status */ 1274 if (init != 0) { 1275 sc->sc_prun = 0; 1276 sc->sc_rrun = 0; 1277 } 1278 1279 /* setup playback volume */ 1280 BA0WRITE4(sc, CS4281_PPRVC, 7); 1281 BA0WRITE4(sc, CS4281_PPLVC, 7); 1282 1283 return 0; 1284 } 1285
Indexes created Thu Oct 02 10:09:58 GMT 2025