cs4281.c revision 1.23
1 /* $NetBSD: cs4281.c,v 1.23 2005/01/15 15:19:52 kent Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.23 2005/01/15 15:19:52 kent Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 int cs4281_match(struct device *, struct cfdata *, void *); 84 void cs4281_attach(struct device *, struct device *, void *); 85 int cs4281_intr(void *); 86 int cs4281_query_encoding(void *, struct audio_encoding *); 87 int cs4281_set_params(void *, int, int, audio_params_t *, audio_params_t *, 88 stream_filter_list_t *, stream_filter_list_t *); 89 int cs4281_halt_output(void *); 90 int cs4281_halt_input(void *); 91 int cs4281_getdev(void *, struct audio_device *); 92 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 93 void *, const audio_params_t *); 94 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 95 void *, const audio_params_t *); 96 97 int cs4281_reset_codec(void *); 98 99 /* Internal functions */ 100 uint8_t cs4281_sr2regval(int); 101 void cs4281_set_dac_rate(struct cs428x_softc *, int); 102 void cs4281_set_adc_rate(struct cs428x_softc *, int); 103 int cs4281_init(struct cs428x_softc *, int); 104 105 /* Power Management */ 106 void cs4281_power(int, void *); 107 108 const struct audio_hw_if cs4281_hw_if = { 109 NULL, /* open */ 110 NULL, /* close */ 111 NULL, 112 cs4281_query_encoding, 113 cs4281_set_params, 114 cs428x_round_blocksize, 115 NULL, 116 NULL, 117 NULL, 118 NULL, 119 NULL, 120 cs4281_halt_output, 121 cs4281_halt_input, 122 NULL, 123 cs4281_getdev, 124 NULL, 125 cs428x_mixer_set_port, 126 cs428x_mixer_get_port, 127 cs428x_query_devinfo, 128 cs428x_malloc, 129 cs428x_free, 130 cs428x_round_buffersize, 131 cs428x_mappage, 132 cs428x_get_props, 133 cs4281_trigger_output, 134 cs4281_trigger_input, 135 NULL, 136 }; 137 138 #if NMIDI > 0 && 0 139 /* Midi Interface */ 140 void cs4281_midi_close(void*); 141 void cs4281_midi_getinfo(void *, struct midi_info *); 142 int cs4281_midi_open(void *, int, void (*)(void *, int), 143 void (*)(void *), void *); 144 int cs4281_midi_output(void *, int); 145 146 const struct midi_hw_if cs4281_midi_hw_if = { 147 cs4281_midi_open, 148 cs4281_midi_close, 149 cs4281_midi_output, 150 cs4281_midi_getinfo, 151 0, 152 }; 153 #endif 154 155 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 156 cs4281_match, cs4281_attach, NULL, NULL); 157 158 struct audio_device cs4281_device = { 159 "CS4281", 160 "", 161 "cs4281" 162 }; 163 164 165 int 166 cs4281_match(struct device *parent, struct cfdata *match, void *aux) 167 { 168 struct pci_attach_args *pa; 169 170 pa = (struct pci_attach_args *)aux; 171 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 172 return 0; 173 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 174 return 1; 175 return 0; 176 } 177 178 void 179 cs4281_attach(struct device *parent, struct device *self, void *aux) 180 { 181 struct cs428x_softc *sc; 182 struct pci_attach_args *pa; 183 pci_chipset_tag_t pc; 184 char const *intrstr; 185 pci_intr_handle_t ih; 186 pcireg_t reg; 187 char devinfo[256]; 188 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 189 190 sc = (struct cs428x_softc *)self; 191 pa = (struct pci_attach_args *)aux; 192 pc = pa->pa_pc; 193 aprint_naive(": Audio controller\n"); 194 195 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 196 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 197 PCI_REVISION(pa->pa_class)); 198 199 /* Map I/O register */ 200 if (pci_mapreg_map(pa, PCI_BA0, 201 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 202 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 203 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 204 return; 205 } 206 if (pci_mapreg_map(pa, PCI_BA1, 207 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 208 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 209 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 210 return; 211 } 212 213 sc->sc_dmatag = pa->pa_dmat; 214 215 /* 216 * Set Power State D0. 217 * Without do this, 0xffffffff is read from all registers after 218 * using Windows. 219 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 220 */ 221 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 222 &pci_pwrmgmt_cap_reg, 0)) { 223 224 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 225 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 226 pci_pwrmgmt_csr_reg); 227 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 228 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 229 (reg & ~PCI_PMCSR_STATE_MASK) | 230 PCI_PMCSR_STATE_D0); 231 } 232 } 233 234 /* Enable the device (set bus master flag) */ 235 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 236 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 237 reg | PCI_COMMAND_MASTER_ENABLE); 238 239 #if 0 240 /* LATENCY_TIMER setting */ 241 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 242 if (PCI_LATTIMER(temp1) < 32) { 243 temp1 &= 0xffff00ff; 244 temp1 |= 0x00002000; 245 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 246 } 247 #endif 248 249 /* Map and establish the interrupt. */ 250 if (pci_intr_map(pa, &ih)) { 251 aprint_error("%s: couldn't map interrupt\n", 252 sc->sc_dev.dv_xname); 253 return; 254 } 255 intrstr = pci_intr_string(pc, ih); 256 257 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 258 if (sc->sc_ih == NULL) { 259 aprint_error("%s: couldn't establish interrupt", 260 sc->sc_dev.dv_xname); 261 if (intrstr != NULL) 262 aprint_normal(" at %s", intrstr); 263 aprint_normal("\n"); 264 return; 265 } 266 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 267 268 /* 269 * Sound System start-up 270 */ 271 if (cs4281_init(sc, 1) != 0) 272 return; 273 274 sc->type = TYPE_CS4281; 275 sc->halt_input = cs4281_halt_input; 276 sc->halt_output = cs4281_halt_output; 277 278 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 279 sc->dma_align = 0x10; 280 sc->hw_blocksize = sc->dma_size / 2; 281 282 /* AC 97 attachment */ 283 sc->host_if.arg = sc; 284 sc->host_if.attach = cs428x_attach_codec; 285 sc->host_if.read = cs428x_read_codec; 286 sc->host_if.write = cs428x_write_codec; 287 sc->host_if.reset = cs4281_reset_codec; 288 if (ac97_attach(&sc->host_if, self) != 0) { 289 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 290 return; 291 } 292 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 293 294 #if NMIDI > 0 && 0 295 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 296 #endif 297 298 sc->sc_suspend = PWR_RESUME; 299 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 300 } 301 302 int 303 cs4281_intr(void *p) 304 { 305 struct cs428x_softc *sc; 306 uint32_t intr, hdsr0, hdsr1; 307 char *empty_dma; 308 int handled; 309 310 sc = p; 311 handled = 0; 312 hdsr0 = 0; 313 hdsr1 = 0; 314 315 /* grab interrupt register */ 316 intr = BA0READ4(sc, CS4281_HISR); 317 318 DPRINTF(("cs4281_intr:")); 319 /* not for me */ 320 if ((intr & HISR_INTENA) == 0) { 321 /* clear the interrupt register */ 322 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 323 return 0; 324 } 325 326 if (intr & HISR_DMA0) 327 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 328 if (intr & HISR_DMA1) 329 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 330 /* clear the interrupt register */ 331 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 332 333 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 334 intr, hdsr0, hdsr1)); 335 336 /* Playback Interrupt */ 337 if (intr & HISR_DMA0) { 338 handled = 1; 339 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 340 (int)BA0READ4(sc, CS4281_DCC0))); 341 if (sc->sc_prun) { 342 if ((sc->sc_pi%sc->sc_pcount) == 0) 343 sc->sc_pintr(sc->sc_parg); 344 } else { 345 printf("unexpected play intr\n"); 346 } 347 /* copy buffer */ 348 ++sc->sc_pi; 349 empty_dma = sc->sc_pdma->addr; 350 if (sc->sc_pi&1) 351 empty_dma += sc->hw_blocksize; 352 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 353 sc->sc_pn += sc->hw_blocksize; 354 if (sc->sc_pn >= sc->sc_pe) 355 sc->sc_pn = sc->sc_ps; 356 } 357 if (intr & HISR_DMA1) { 358 handled = 1; 359 /* copy from DMA */ 360 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 361 (int)BA0READ4(sc, CS4281_DCC1))); 362 ++sc->sc_ri; 363 empty_dma = sc->sc_rdma->addr; 364 if ((sc->sc_ri & 1) == 0) 365 empty_dma += sc->hw_blocksize; 366 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 367 sc->sc_rn += sc->hw_blocksize; 368 if (sc->sc_rn >= sc->sc_re) 369 sc->sc_rn = sc->sc_rs; 370 if (sc->sc_rrun) { 371 if ((sc->sc_ri % sc->sc_rcount) == 0) 372 sc->sc_rintr(sc->sc_rarg); 373 } else { 374 printf("unexpected record intr\n"); 375 } 376 } 377 DPRINTF(("\n")); 378 379 return handled; 380 } 381 382 int 383 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 384 { 385 386 switch (fp->index) { 387 case 0: 388 strcpy(fp->name, AudioEulinear); 389 fp->encoding = AUDIO_ENCODING_ULINEAR; 390 fp->precision = 8; 391 fp->flags = 0; 392 break; 393 case 1: 394 strcpy(fp->name, AudioEmulaw); 395 fp->encoding = AUDIO_ENCODING_ULAW; 396 fp->precision = 8; 397 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 398 break; 399 case 2: 400 strcpy(fp->name, AudioEalaw); 401 fp->encoding = AUDIO_ENCODING_ALAW; 402 fp->precision = 8; 403 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 404 break; 405 case 3: 406 strcpy(fp->name, AudioEslinear); 407 fp->encoding = AUDIO_ENCODING_SLINEAR; 408 fp->precision = 8; 409 fp->flags = 0; 410 break; 411 case 4: 412 strcpy(fp->name, AudioEslinear_le); 413 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 414 fp->precision = 16; 415 fp->flags = 0; 416 break; 417 case 5: 418 strcpy(fp->name, AudioEulinear_le); 419 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 420 fp->precision = 16; 421 fp->flags = 0; 422 break; 423 case 6: 424 strcpy(fp->name, AudioEslinear_be); 425 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 426 fp->precision = 16; 427 fp->flags = 0; 428 break; 429 case 7: 430 strcpy(fp->name, AudioEulinear_be); 431 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 432 fp->precision = 16; 433 fp->flags = 0; 434 break; 435 default: 436 return EINVAL; 437 } 438 return 0; 439 } 440 441 int 442 cs4281_set_params(void *addr, int setmode, int usemode, 443 audio_params_t *play, audio_params_t *rec, 444 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 445 { 446 audio_params_t hw; 447 struct cs428x_softc *sc; 448 audio_params_t *p; 449 stream_filter_list_t *fil; 450 int mode; 451 452 sc = addr; 453 for (mode = AUMODE_RECORD; mode != -1; 454 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 455 if ((setmode & mode) == 0) 456 continue; 457 458 p = mode == AUMODE_PLAY ? play : rec; 459 460 if (p == play) { 461 DPRINTFN(5, ("play: sample=%ld precision=%d channels=%d\n", 462 p->sample_rate, p->precision, p->channels)); 463 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 464 (p->precision != 8 && p->precision != 16) || 465 (p->channels != 1 && p->channels != 2)) { 466 return EINVAL; 467 } 468 } else { 469 DPRINTFN(5, ("rec: sample=%ld precision=%d channels=%d\n", 470 p->sample_rate, p->precision, p->channels)); 471 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 472 (p->precision != 8 && p->precision != 16) || 473 (p->channels != 1 && p->channels != 2)) { 474 return EINVAL; 475 } 476 } 477 hw = *p; 478 fil = mode == AUMODE_PLAY ? pfil : rfil; 479 480 switch (p->encoding) { 481 case AUDIO_ENCODING_SLINEAR_BE: 482 break; 483 case AUDIO_ENCODING_SLINEAR_LE: 484 break; 485 case AUDIO_ENCODING_ULINEAR_BE: 486 break; 487 case AUDIO_ENCODING_ULINEAR_LE: 488 break; 489 case AUDIO_ENCODING_ULAW: 490 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 491 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 492 : linear8_to_mulaw, &hw); 493 break; 494 case AUDIO_ENCODING_ALAW: 495 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 496 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 497 : linear8_to_alaw, &hw); 498 break; 499 default: 500 return EINVAL; 501 } 502 } 503 504 /* set sample rate */ 505 cs4281_set_dac_rate(sc, play->sample_rate); 506 cs4281_set_adc_rate(sc, rec->sample_rate); 507 return 0; 508 } 509 510 int 511 cs4281_halt_output(void *addr) 512 { 513 struct cs428x_softc *sc; 514 515 sc = addr; 516 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 517 sc->sc_prun = 0; 518 return 0; 519 } 520 521 int 522 cs4281_halt_input(void *addr) 523 { 524 struct cs428x_softc *sc; 525 526 sc = addr; 527 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 528 sc->sc_rrun = 0; 529 return 0; 530 } 531 532 int 533 cs4281_getdev(void *addr, struct audio_device *retp) 534 { 535 536 *retp = cs4281_device; 537 return 0; 538 } 539 540 int 541 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 542 void (*intr)(void *), void *arg, 543 const audio_params_t *param) 544 { 545 struct cs428x_softc *sc; 546 uint32_t fmt; 547 struct cs428x_dma *p; 548 int dma_count; 549 550 sc = addr; 551 fmt = 0; 552 #ifdef DIAGNOSTIC 553 if (sc->sc_prun) 554 printf("cs4281_trigger_output: already running\n"); 555 #endif 556 sc->sc_prun = 1; 557 558 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 559 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 560 sc->sc_pintr = intr; 561 sc->sc_parg = arg; 562 563 /* stop playback DMA */ 564 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 565 566 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 567 param->precision, param->channels, param->encoding)); 568 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 569 continue; 570 if (p == NULL) { 571 printf("cs4281_trigger_output: bad addr %p\n", start); 572 return EINVAL; 573 } 574 575 sc->sc_pcount = blksize / sc->hw_blocksize; 576 sc->sc_ps = (char *)start; 577 sc->sc_pe = (char *)end; 578 sc->sc_pdma = p; 579 sc->sc_pbuf = KERNADDR(p); 580 sc->sc_pi = 0; 581 sc->sc_pn = sc->sc_ps; 582 if (blksize >= sc->dma_size) { 583 sc->sc_pn = sc->sc_ps + sc->dma_size; 584 memcpy(sc->sc_pbuf, start, sc->dma_size); 585 ++sc->sc_pi; 586 } else { 587 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 588 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 589 } 590 591 dma_count = sc->dma_size; 592 if (param->precision != 8) 593 dma_count /= 2; /* 16 bit */ 594 if (param->channels > 1) 595 dma_count /= 2; /* Stereo */ 596 597 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 598 (int)DMAADDR(p), dma_count)); 599 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 600 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 601 602 /* set playback format */ 603 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 604 if (param->precision == 8) 605 fmt |= DMRn_SIZE8; 606 if (param->channels == 1) 607 fmt |= DMRn_MONO; 608 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 609 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 610 fmt |= DMRn_BEND; 611 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 612 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 613 fmt |= DMRn_USIGN; 614 BA0WRITE4(sc, CS4281_DMR0, fmt); 615 616 /* set sample rate */ 617 sc->sc_prate = param->sample_rate; 618 cs4281_set_dac_rate(sc, param->sample_rate); 619 620 /* start DMA */ 621 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 622 /* Enable interrupts */ 623 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 624 625 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 626 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 627 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 628 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 629 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 630 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 631 BA0READ4(sc, CS4281_DACSR))); 632 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 633 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 634 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 635 636 return 0; 637 } 638 639 int 640 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 641 void (*intr)(void *), void *arg, 642 const audio_params_t *param) 643 { 644 struct cs428x_softc *sc; 645 struct cs428x_dma *p; 646 uint32_t fmt; 647 int dma_count; 648 649 sc = addr; 650 fmt = 0; 651 #ifdef DIAGNOSTIC 652 if (sc->sc_rrun) 653 printf("cs4281_trigger_input: already running\n"); 654 #endif 655 sc->sc_rrun = 1; 656 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 657 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 658 sc->sc_rintr = intr; 659 sc->sc_rarg = arg; 660 661 /* stop recording DMA */ 662 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 663 664 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 665 continue; 666 if (!p) { 667 printf("cs4281_trigger_input: bad addr %p\n", start); 668 return EINVAL; 669 } 670 671 sc->sc_rcount = blksize / sc->hw_blocksize; 672 sc->sc_rs = (char *)start; 673 sc->sc_re = (char *)end; 674 sc->sc_rdma = p; 675 sc->sc_rbuf = KERNADDR(p); 676 sc->sc_ri = 0; 677 sc->sc_rn = sc->sc_rs; 678 679 dma_count = sc->dma_size; 680 if (param->precision != 8) 681 dma_count /= 2; 682 if (param->channels > 1) 683 dma_count /= 2; 684 685 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 686 (int)DMAADDR(p), dma_count)); 687 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 688 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 689 690 /* set recording format */ 691 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 692 if (param->precision == 8) 693 fmt |= DMRn_SIZE8; 694 if (param->channels == 1) 695 fmt |= DMRn_MONO; 696 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 697 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 698 fmt |= DMRn_BEND; 699 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 700 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 701 fmt |= DMRn_USIGN; 702 BA0WRITE4(sc, CS4281_DMR1, fmt); 703 704 /* set sample rate */ 705 sc->sc_rrate = param->sample_rate; 706 cs4281_set_adc_rate(sc, param->sample_rate); 707 708 /* Start DMA */ 709 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 710 /* Enable interrupts */ 711 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 712 713 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 714 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 715 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 716 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 717 718 return 0; 719 } 720 721 /* Power Hook */ 722 void 723 cs4281_power(int why, void *v) 724 { 725 static uint32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 726 static uint32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 727 struct cs428x_softc *sc; 728 729 sc = (struct cs428x_softc *)v; 730 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 731 switch (why) { 732 case PWR_SUSPEND: 733 case PWR_STANDBY: 734 sc->sc_suspend = why; 735 736 /* save current playback status */ 737 if (sc->sc_prun) { 738 dcr0 = BA0READ4(sc, CS4281_DCR0); 739 dmr0 = BA0READ4(sc, CS4281_DMR0); 740 dbc0 = BA0READ4(sc, CS4281_DBC0); 741 dba0 = BA0READ4(sc, CS4281_DBA0); 742 } 743 744 /* save current capture status */ 745 if (sc->sc_rrun) { 746 dcr1 = BA0READ4(sc, CS4281_DCR1); 747 dmr1 = BA0READ4(sc, CS4281_DMR1); 748 dbc1 = BA0READ4(sc, CS4281_DBC1); 749 dba1 = BA0READ4(sc, CS4281_DBA1); 750 } 751 /* Stop DMA */ 752 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 753 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 754 break; 755 case PWR_RESUME: 756 if (sc->sc_suspend == PWR_RESUME) { 757 printf("cs4281_power: odd, resume without suspend.\n"); 758 sc->sc_suspend = why; 759 return; 760 } 761 sc->sc_suspend = why; 762 cs4281_init(sc, 0); 763 cs4281_reset_codec(sc); 764 765 /* restore ac97 registers */ 766 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 767 768 /* restore DMA related status */ 769 if (sc->sc_prun) { 770 cs4281_set_dac_rate(sc, sc->sc_prate); 771 BA0WRITE4(sc, CS4281_DBA0, dba0); 772 BA0WRITE4(sc, CS4281_DBC0, dbc0); 773 BA0WRITE4(sc, CS4281_DMR0, dmr0); 774 BA0WRITE4(sc, CS4281_DCR0, dcr0); 775 } 776 if (sc->sc_rrun) { 777 cs4281_set_adc_rate(sc, sc->sc_rrate); 778 BA0WRITE4(sc, CS4281_DBA1, dba1); 779 BA0WRITE4(sc, CS4281_DBC1, dbc1); 780 BA0WRITE4(sc, CS4281_DMR1, dmr1); 781 BA0WRITE4(sc, CS4281_DCR1, dcr1); 782 } 783 /* enable intterupts */ 784 if (sc->sc_prun || sc->sc_rrun) 785 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 786 break; 787 case PWR_SOFTSUSPEND: 788 case PWR_SOFTSTANDBY: 789 case PWR_SOFTRESUME: 790 break; 791 } 792 } 793 794 /* control AC97 codec */ 795 int 796 cs4281_reset_codec(void *addr) 797 { 798 struct cs428x_softc *sc; 799 uint16_t data; 800 uint32_t dat32; 801 int n; 802 803 sc = addr; 804 805 DPRINTFN(3, ("cs4281_reset_codec\n")); 806 807 /* Reset codec */ 808 BA0WRITE4(sc, CS428X_ACCTL, 0); 809 delay(50); /* delay 50us */ 810 811 BA0WRITE4(sc, CS4281_SPMC, 0); 812 delay(100); /* delay 100us */ 813 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 814 #if defined(ENABLE_SECONDARY_CODEC) 815 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 816 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 817 #endif 818 delay(50000); /* XXX: delay 50ms */ 819 820 /* Enable ASYNC generation */ 821 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 822 823 /* Wait for codec ready. Linux driver waits 50ms here */ 824 n = 0; 825 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 826 delay(100); 827 if (++n > 1000) { 828 printf("reset_codec: AC97 codec ready timeout\n"); 829 return ETIMEDOUT; 830 } 831 } 832 #if defined(ENABLE_SECONDARY_CODEC) 833 /* secondary codec ready*/ 834 n = 0; 835 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 836 delay(100); 837 if (++n > 1000) 838 return 0; 839 } 840 #endif 841 /* Set the serial timing configuration */ 842 /* XXX: undocumented but the Linux driver do this */ 843 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 844 845 /* Wait for codec ready signal */ 846 n = 0; 847 do { 848 delay(1000); 849 if (++n > 1000) { 850 printf("%s: timeout waiting for codec ready\n", 851 sc->sc_dev.dv_xname); 852 return ETIMEDOUT; 853 } 854 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 855 } while (dat32 == 0); 856 857 /* Enable Valid Frame output on ASDOUT */ 858 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 859 860 /* Wait until codec calibration is finished. Codec register 26h */ 861 n = 0; 862 do { 863 delay(1); 864 if (++n > 1000) { 865 printf("%s: timeout waiting for codec calibration\n", 866 sc->sc_dev.dv_xname); 867 return ETIMEDOUT; 868 } 869 cs428x_read_codec(sc, AC97_REG_POWER, &data); 870 } while ((data & 0x0f) != 0x0f); 871 872 /* Set the serial timing configuration again */ 873 /* XXX: undocumented but the Linux driver do this */ 874 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 875 876 /* Wait until we've sampled input slots 3 & 4 as valid */ 877 n = 0; 878 do { 879 delay(1000); 880 if (++n > 1000) { 881 printf("%s: timeout waiting for sampled input slots as valid\n", 882 sc->sc_dev.dv_xname); 883 return ETIMEDOUT; 884 } 885 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 886 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 887 888 /* Start digital data transfer of audio data to the codec */ 889 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 890 return 0; 891 } 892 893 894 /* Internal functions */ 895 896 /* convert sample rate to register value */ 897 uint8_t 898 cs4281_sr2regval(int rate) 899 { 900 uint8_t retval; 901 902 /* We don't have to change here. but anyway ... */ 903 if (rate > 48000) 904 rate = 48000; 905 if (rate < 6023) 906 rate = 6023; 907 908 switch (rate) { 909 case 8000: 910 retval = 5; 911 break; 912 case 11025: 913 retval = 4; 914 break; 915 case 16000: 916 retval = 3; 917 break; 918 case 22050: 919 retval = 2; 920 break; 921 case 44100: 922 retval = 1; 923 break; 924 case 48000: 925 retval = 0; 926 break; 927 default: 928 retval = 1536000/rate; /* == 24576000/(rate*16) */ 929 } 930 return retval; 931 } 932 933 void 934 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 935 { 936 937 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 938 } 939 940 void 941 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 942 { 943 944 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 945 } 946 947 int 948 cs4281_init(struct cs428x_softc *sc, int init) 949 { 950 int n; 951 uint16_t data; 952 uint32_t dat32; 953 954 /* set "Configuration Write Protect" register to 955 * 0x4281 to allow to write */ 956 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 957 958 /* 959 * Unset "Full Power-Down bit of Extended PCI Power Management 960 * Control" register to release the reset state. 961 */ 962 dat32 = BA0READ4(sc, CS4281_EPPMC); 963 if (dat32 & EPPMC_FPDN) { 964 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 965 } 966 967 /* Start PLL out in known state */ 968 BA0WRITE4(sc, CS4281_CLKCR1, 0); 969 /* Start serial ports out in known state */ 970 BA0WRITE4(sc, CS4281_SERMC, 0); 971 972 /* Reset codec */ 973 BA0WRITE4(sc, CS428X_ACCTL, 0); 974 delay(50); /* delay 50us */ 975 976 BA0WRITE4(sc, CS4281_SPMC, 0); 977 delay(100); /* delay 100us */ 978 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 979 #if defined(ENABLE_SECONDARY_CODEC) 980 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 981 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 982 #endif 983 delay(50000); /* XXX: delay 50ms */ 984 985 /* Turn on Sound System clocks based on ABITCLK */ 986 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 987 delay(50000); /* XXX: delay 50ms */ 988 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 989 990 /* Set enables for sections that are needed in the SSPM registers */ 991 BA0WRITE4(sc, CS4281_SSPM, 992 SSPM_MIXEN | /* Mixer */ 993 SSPM_CSRCEN | /* Capture SRC */ 994 SSPM_PSRCEN | /* Playback SRC */ 995 SSPM_JSEN | /* Joystick */ 996 SSPM_ACLEN | /* AC LINK */ 997 SSPM_FMEN /* FM */ 998 ); 999 1000 /* Wait for clock stabilization */ 1001 n = 0; 1002 #if 1 1003 /* what document says */ 1004 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1005 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1006 delay(100); 1007 if (++n > 1000) { 1008 printf("%s: timeout waiting for clock stabilization\n", 1009 sc->sc_dev.dv_xname); 1010 return -1; 1011 } 1012 } 1013 #else 1014 /* Cirrus driver for Linux does */ 1015 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1016 delay(1000); 1017 if (++n > 1000) { 1018 printf("%s: timeout waiting for clock stabilization\n", 1019 sc->sc_dev.dv_xname); 1020 return -1; 1021 } 1022 } 1023 #endif 1024 1025 /* Enable ASYNC generation */ 1026 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1027 1028 /* Wait for codec ready. Linux driver waits 50ms here */ 1029 n = 0; 1030 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1031 delay(100); 1032 if (++n > 1000) { 1033 printf("%s: timeout waiting for codec ready\n", 1034 sc->sc_dev.dv_xname); 1035 return -1; 1036 } 1037 } 1038 1039 #if defined(ENABLE_SECONDARY_CODEC) 1040 /* secondary codec ready*/ 1041 n = 0; 1042 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1043 delay(100); 1044 if (++n > 1000) { 1045 printf("%s: timeout waiting for secondary codec ready\n", 1046 sc->sc_dev.dv_xname); 1047 return -1; 1048 } 1049 } 1050 #endif 1051 1052 /* Set the serial timing configuration */ 1053 /* XXX: undocumented but the Linux driver do this */ 1054 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1055 1056 /* Wait for codec ready signal */ 1057 n = 0; 1058 do { 1059 delay(1000); 1060 if (++n > 1000) { 1061 printf("%s: timeout waiting for codec ready\n", 1062 sc->sc_dev.dv_xname); 1063 return -1; 1064 } 1065 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1066 } while (dat32 == 0); 1067 1068 /* Enable Valid Frame output on ASDOUT */ 1069 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1070 1071 /* Wait until codec calibration is finished. codec register 26h */ 1072 n = 0; 1073 do { 1074 delay(1); 1075 if (++n > 1000) { 1076 printf("%s: timeout waiting for codec calibration\n", 1077 sc->sc_dev.dv_xname); 1078 return -1; 1079 } 1080 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1081 } while ((data & 0x0f) != 0x0f); 1082 1083 /* Set the serial timing configuration again */ 1084 /* XXX: undocumented but the Linux driver do this */ 1085 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1086 1087 /* Wait until we've sampled input slots 3 & 4 as valid */ 1088 n = 0; 1089 do { 1090 delay(1000); 1091 if (++n > 1000) { 1092 printf("%s: timeout waiting for sampled input slots as valid\n", 1093 sc->sc_dev.dv_xname); 1094 return -1; 1095 } 1096 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1097 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1098 1099 /* Start digital data transfer of audio data to the codec */ 1100 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1101 1102 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1103 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1104 1105 /* Power on the DAC */ 1106 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1107 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1108 1109 /* Wait until we sample a DAC ready state. 1110 * Not documented, but Linux driver does. 1111 */ 1112 for (n = 0; n < 32; ++n) { 1113 delay(1000); 1114 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1115 if (data & 0x02) 1116 break; 1117 } 1118 1119 /* Power on the ADC */ 1120 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1121 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1122 1123 /* Wait until we sample ADC ready state. 1124 * Not documented, but Linux driver does. 1125 */ 1126 for (n = 0; n < 32; ++n) { 1127 delay(1000); 1128 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1129 if (data & 0x01) 1130 break; 1131 } 1132 1133 #if 0 1134 /* Initialize AC-Link features */ 1135 /* variable sample-rate support */ 1136 mem = BA0READ4(sc, CS4281_SERMC); 1137 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1138 BA0WRITE4(sc, CS4281_SERMC, mem); 1139 /* XXX: more... */ 1140 1141 /* Initialize SSCR register features */ 1142 /* XXX: hardware volume setting */ 1143 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1144 #endif 1145 1146 /* disable Sound Blaster Pro emulation */ 1147 /* XXX: 1148 * Cannot set since the documents does not describe which bit is 1149 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1150 * we can ignore it.*/ 1151 #if 0 1152 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1153 #endif 1154 1155 /* map AC97 PCM playback to DMA Channel 0 */ 1156 /* Reset FEN bit to setup first */ 1157 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1158 /* 1159 *| RS[4:0]/| | 1160 *| LS[4:0] | AC97 | Slot Function 1161 *|---------+--------+-------------------- 1162 *| 0 | 3 | Left PCM Playback 1163 *| 1 | 4 | Right PCM Playback 1164 *| 2 | 5 | Phone Line 1 DAC 1165 *| 3 | 6 | Center PCM Playback 1166 *.... 1167 * quoted from Table 29(p109) 1168 */ 1169 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1170 0x00 << 16 | /* LS[4:0] = 0 see above */ 1171 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1172 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1173 BA0WRITE4(sc, CS4281_FCR0, dat32); 1174 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1175 1176 /* map AC97 PCM record to DMA Channel 1 */ 1177 /* Reset FEN bit to setup first */ 1178 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1179 /* 1180 *| RS[4:0]/| 1181 *| LS[4:0] | AC97 | Slot Function 1182 *|---------+------+------------------- 1183 *| 10 | 3 | Left PCM Record 1184 *| 11 | 4 | Right PCM Record 1185 *| 12 | 5 | Phone Line 1 ADC 1186 *| 13 | 6 | Mic ADC 1187 *.... 1188 * quoted from Table 30(p109) 1189 */ 1190 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1191 0x0a << 16 | /* LS[4:0] = 10 See above */ 1192 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1193 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1194 1195 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1196 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1197 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1198 1199 #if 0 1200 /* Disable DMA Channel 2, 3 */ 1201 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1202 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1203 #endif 1204 1205 /* Set the SRC Slot Assignment accordingly */ 1206 /*| PLSS[4:0]/ 1207 *| PRSS[4:0] | AC97 | Slot Function 1208 *|-----------+------+---------------- 1209 *| 0 | 3 | Left PCM Playback 1210 *| 1 | 4 | Right PCM Playback 1211 *| 2 | 5 | phone line 1 DAC 1212 *| 3 | 6 | Center PCM Playback 1213 *| 4 | 7 | Left Surround PCM Playback 1214 *| 5 | 8 | Right Surround PCM Playback 1215 *...... 1216 * 1217 *| CLSS[4:0]/ 1218 *| CRSS[4:0] | AC97 | Codec |Slot Function 1219 *|-----------+------+-------+----------------- 1220 *| 10 | 3 |Primary| Left PCM Record 1221 *| 11 | 4 |Primary| Right PCM Record 1222 *| 12 | 5 |Primary| Phone Line 1 ADC 1223 *| 13 | 6 |Primary| Mic ADC 1224 *|..... 1225 *| 20 | 3 | Sec. | Left PCM Record 1226 *| 21 | 4 | Sec. | Right PCM Record 1227 *| 22 | 5 | Sec. | Phone Line 1 ADC 1228 *| 23 | 6 | Sec. | Mic ADC 1229 */ 1230 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1231 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1232 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1233 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1234 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1235 1236 /* Set interrupt to occurred at Half and Full terminal 1237 * count interrupt enable for DMA channel 0 and 1. 1238 * To keep DMA stop, set MSK. 1239 */ 1240 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1241 BA0WRITE4(sc, CS4281_DCR0, dat32); 1242 BA0WRITE4(sc, CS4281_DCR1, dat32); 1243 1244 /* Set Auto-Initialize Contorl enable */ 1245 BA0WRITE4(sc, CS4281_DMR0, 1246 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1247 BA0WRITE4(sc, CS4281_DMR1, 1248 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1249 1250 /* Clear DMA Mask in HIMR */ 1251 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1252 BA0WRITE4(sc, CS4281_HIMR, 1253 BA0READ4(sc, CS4281_HIMR) & dat32); 1254 1255 /* set current status */ 1256 if (init != 0) { 1257 sc->sc_prun = 0; 1258 sc->sc_rrun = 0; 1259 } 1260 1261 /* setup playback volume */ 1262 BA0WRITE4(sc, CS4281_PPRVC, 7); 1263 BA0WRITE4(sc, CS4281_PPLVC, 7); 1264 1265 return 0; 1266 } 1267
Indexes created Wed Oct 01 07:09:59 GMT 2025