cs4281.c revision 1.26
1 /* $NetBSD: cs4281.c,v 1.26 2005/06/28 00:28:41 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.26 2005/06/28 00:28:41 thorpej Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(struct device *, struct cfdata *, void *); 84 static void cs4281_attach(struct device *, struct device *, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static void cs4281_power(int, void *); 110 111 static const struct audio_hw_if cs4281_hw_if = { 112 NULL, /* open */ 113 NULL, /* close */ 114 NULL, 115 cs4281_query_encoding, 116 cs4281_set_params, 117 cs428x_round_blocksize, 118 NULL, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 cs4281_halt_output, 124 cs4281_halt_input, 125 NULL, 126 cs4281_getdev, 127 NULL, 128 cs428x_mixer_set_port, 129 cs428x_mixer_get_port, 130 cs428x_query_devinfo, 131 cs428x_malloc, 132 cs428x_free, 133 cs428x_round_buffersize, 134 cs428x_mappage, 135 cs428x_get_props, 136 cs4281_trigger_output, 137 cs4281_trigger_input, 138 NULL, 139 }; 140 141 #if NMIDI > 0 && 0 142 /* Midi Interface */ 143 static void cs4281_midi_close(void*); 144 static void cs4281_midi_getinfo(void *, struct midi_info *); 145 static int cs4281_midi_open(void *, int, void (*)(void *, int), 146 void (*)(void *), void *); 147 static int cs4281_midi_output(void *, int); 148 149 static const struct midi_hw_if cs4281_midi_hw_if = { 150 cs4281_midi_open, 151 cs4281_midi_close, 152 cs4281_midi_output, 153 cs4281_midi_getinfo, 154 0, 155 }; 156 #endif 157 158 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 159 cs4281_match, cs4281_attach, NULL, NULL); 160 161 static struct audio_device cs4281_device = { 162 "CS4281", 163 "", 164 "cs4281" 165 }; 166 167 168 static int 169 cs4281_match(struct device *parent, struct cfdata *match, void *aux) 170 { 171 struct pci_attach_args *pa; 172 173 pa = (struct pci_attach_args *)aux; 174 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 175 return 0; 176 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 177 return 1; 178 return 0; 179 } 180 181 static void 182 cs4281_attach(struct device *parent, struct device *self, void *aux) 183 { 184 struct cs428x_softc *sc; 185 struct pci_attach_args *pa; 186 pci_chipset_tag_t pc; 187 char const *intrstr; 188 pci_intr_handle_t ih; 189 pcireg_t reg; 190 char devinfo[256]; 191 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 192 193 sc = (struct cs428x_softc *)self; 194 pa = (struct pci_attach_args *)aux; 195 pc = pa->pa_pc; 196 aprint_naive(": Audio controller\n"); 197 198 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 199 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 200 PCI_REVISION(pa->pa_class)); 201 202 /* Map I/O register */ 203 if (pci_mapreg_map(pa, PCI_BA0, 204 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 205 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 206 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 207 return; 208 } 209 if (pci_mapreg_map(pa, PCI_BA1, 210 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 211 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 212 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 213 return; 214 } 215 216 sc->sc_dmatag = pa->pa_dmat; 217 218 /* 219 * Set Power State D0. 220 * Without do this, 0xffffffff is read from all registers after 221 * using Windows. 222 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 223 */ 224 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 225 &pci_pwrmgmt_cap_reg, 0)) { 226 227 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 228 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 229 pci_pwrmgmt_csr_reg); 230 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 231 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 232 (reg & ~PCI_PMCSR_STATE_MASK) | 233 PCI_PMCSR_STATE_D0); 234 } 235 } 236 237 /* Enable the device (set bus master flag) */ 238 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 239 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 240 reg | PCI_COMMAND_MASTER_ENABLE); 241 242 #if 0 243 /* LATENCY_TIMER setting */ 244 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 245 if (PCI_LATTIMER(temp1) < 32) { 246 temp1 &= 0xffff00ff; 247 temp1 |= 0x00002000; 248 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 249 } 250 #endif 251 252 /* Map and establish the interrupt. */ 253 if (pci_intr_map(pa, &ih)) { 254 aprint_error("%s: couldn't map interrupt\n", 255 sc->sc_dev.dv_xname); 256 return; 257 } 258 intrstr = pci_intr_string(pc, ih); 259 260 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 261 if (sc->sc_ih == NULL) { 262 aprint_error("%s: couldn't establish interrupt", 263 sc->sc_dev.dv_xname); 264 if (intrstr != NULL) 265 aprint_normal(" at %s", intrstr); 266 aprint_normal("\n"); 267 return; 268 } 269 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 270 271 /* 272 * Sound System start-up 273 */ 274 if (cs4281_init(sc, 1) != 0) 275 return; 276 277 sc->type = TYPE_CS4281; 278 sc->halt_input = cs4281_halt_input; 279 sc->halt_output = cs4281_halt_output; 280 281 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 282 sc->dma_align = 0x10; 283 sc->hw_blocksize = sc->dma_size / 2; 284 285 /* AC 97 attachment */ 286 sc->host_if.arg = sc; 287 sc->host_if.attach = cs428x_attach_codec; 288 sc->host_if.read = cs428x_read_codec; 289 sc->host_if.write = cs428x_write_codec; 290 sc->host_if.reset = cs4281_reset_codec; 291 if (ac97_attach(&sc->host_if, self) != 0) { 292 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 293 return; 294 } 295 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 296 297 #if NMIDI > 0 && 0 298 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 299 #endif 300 301 sc->sc_suspend = PWR_RESUME; 302 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 303 } 304 305 static int 306 cs4281_intr(void *p) 307 { 308 struct cs428x_softc *sc; 309 uint32_t intr, hdsr0, hdsr1; 310 char *empty_dma; 311 int handled; 312 313 sc = p; 314 handled = 0; 315 hdsr0 = 0; 316 hdsr1 = 0; 317 318 /* grab interrupt register */ 319 intr = BA0READ4(sc, CS4281_HISR); 320 321 DPRINTF(("cs4281_intr:")); 322 /* not for me */ 323 if ((intr & HISR_INTENA) == 0) { 324 /* clear the interrupt register */ 325 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 326 return 0; 327 } 328 329 if (intr & HISR_DMA0) 330 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 331 if (intr & HISR_DMA1) 332 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 333 /* clear the interrupt register */ 334 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 335 336 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 337 intr, hdsr0, hdsr1)); 338 339 /* Playback Interrupt */ 340 if (intr & HISR_DMA0) { 341 handled = 1; 342 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 343 (int)BA0READ4(sc, CS4281_DCC0))); 344 if (sc->sc_prun) { 345 if ((sc->sc_pi%sc->sc_pcount) == 0) 346 sc->sc_pintr(sc->sc_parg); 347 } else { 348 printf("unexpected play intr\n"); 349 } 350 /* copy buffer */ 351 ++sc->sc_pi; 352 empty_dma = sc->sc_pdma->addr; 353 if (sc->sc_pi&1) 354 empty_dma += sc->hw_blocksize; 355 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 356 sc->sc_pn += sc->hw_blocksize; 357 if (sc->sc_pn >= sc->sc_pe) 358 sc->sc_pn = sc->sc_ps; 359 } 360 if (intr & HISR_DMA1) { 361 handled = 1; 362 /* copy from DMA */ 363 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 364 (int)BA0READ4(sc, CS4281_DCC1))); 365 ++sc->sc_ri; 366 empty_dma = sc->sc_rdma->addr; 367 if ((sc->sc_ri & 1) == 0) 368 empty_dma += sc->hw_blocksize; 369 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 370 sc->sc_rn += sc->hw_blocksize; 371 if (sc->sc_rn >= sc->sc_re) 372 sc->sc_rn = sc->sc_rs; 373 if (sc->sc_rrun) { 374 if ((sc->sc_ri % sc->sc_rcount) == 0) 375 sc->sc_rintr(sc->sc_rarg); 376 } else { 377 printf("unexpected record intr\n"); 378 } 379 } 380 DPRINTF(("\n")); 381 382 return handled; 383 } 384 385 static int 386 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 387 { 388 389 switch (fp->index) { 390 case 0: 391 strcpy(fp->name, AudioEulinear); 392 fp->encoding = AUDIO_ENCODING_ULINEAR; 393 fp->precision = 8; 394 fp->flags = 0; 395 break; 396 case 1: 397 strcpy(fp->name, AudioEmulaw); 398 fp->encoding = AUDIO_ENCODING_ULAW; 399 fp->precision = 8; 400 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 401 break; 402 case 2: 403 strcpy(fp->name, AudioEalaw); 404 fp->encoding = AUDIO_ENCODING_ALAW; 405 fp->precision = 8; 406 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 407 break; 408 case 3: 409 strcpy(fp->name, AudioEslinear); 410 fp->encoding = AUDIO_ENCODING_SLINEAR; 411 fp->precision = 8; 412 fp->flags = 0; 413 break; 414 case 4: 415 strcpy(fp->name, AudioEslinear_le); 416 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 417 fp->precision = 16; 418 fp->flags = 0; 419 break; 420 case 5: 421 strcpy(fp->name, AudioEulinear_le); 422 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 423 fp->precision = 16; 424 fp->flags = 0; 425 break; 426 case 6: 427 strcpy(fp->name, AudioEslinear_be); 428 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 429 fp->precision = 16; 430 fp->flags = 0; 431 break; 432 case 7: 433 strcpy(fp->name, AudioEulinear_be); 434 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 435 fp->precision = 16; 436 fp->flags = 0; 437 break; 438 default: 439 return EINVAL; 440 } 441 return 0; 442 } 443 444 static int 445 cs4281_set_params(void *addr, int setmode, int usemode, 446 audio_params_t *play, audio_params_t *rec, 447 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 448 { 449 audio_params_t hw; 450 struct cs428x_softc *sc; 451 audio_params_t *p; 452 stream_filter_list_t *fil; 453 int mode; 454 455 sc = addr; 456 for (mode = AUMODE_RECORD; mode != -1; 457 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 458 if ((setmode & mode) == 0) 459 continue; 460 461 p = mode == AUMODE_PLAY ? play : rec; 462 463 if (p == play) { 464 DPRINTFN(5, 465 ("play: sample=%u precision=%u channels=%u\n", 466 p->sample_rate, p->precision, p->channels)); 467 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 468 (p->precision != 8 && p->precision != 16) || 469 (p->channels != 1 && p->channels != 2)) { 470 return EINVAL; 471 } 472 } else { 473 DPRINTFN(5, 474 ("rec: sample=%u precision=%u channels=%u\n", 475 p->sample_rate, p->precision, p->channels)); 476 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 477 (p->precision != 8 && p->precision != 16) || 478 (p->channels != 1 && p->channels != 2)) { 479 return EINVAL; 480 } 481 } 482 hw = *p; 483 fil = mode == AUMODE_PLAY ? pfil : rfil; 484 485 switch (p->encoding) { 486 case AUDIO_ENCODING_SLINEAR_BE: 487 break; 488 case AUDIO_ENCODING_SLINEAR_LE: 489 break; 490 case AUDIO_ENCODING_ULINEAR_BE: 491 break; 492 case AUDIO_ENCODING_ULINEAR_LE: 493 break; 494 case AUDIO_ENCODING_ULAW: 495 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 496 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 497 : linear8_to_mulaw, &hw); 498 break; 499 case AUDIO_ENCODING_ALAW: 500 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 501 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 502 : linear8_to_alaw, &hw); 503 break; 504 default: 505 return EINVAL; 506 } 507 } 508 509 /* set sample rate */ 510 cs4281_set_dac_rate(sc, play->sample_rate); 511 cs4281_set_adc_rate(sc, rec->sample_rate); 512 return 0; 513 } 514 515 static int 516 cs4281_halt_output(void *addr) 517 { 518 struct cs428x_softc *sc; 519 520 sc = addr; 521 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 522 sc->sc_prun = 0; 523 return 0; 524 } 525 526 static int 527 cs4281_halt_input(void *addr) 528 { 529 struct cs428x_softc *sc; 530 531 sc = addr; 532 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 533 sc->sc_rrun = 0; 534 return 0; 535 } 536 537 static int 538 cs4281_getdev(void *addr, struct audio_device *retp) 539 { 540 541 *retp = cs4281_device; 542 return 0; 543 } 544 545 static int 546 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 547 void (*intr)(void *), void *arg, 548 const audio_params_t *param) 549 { 550 struct cs428x_softc *sc; 551 uint32_t fmt; 552 struct cs428x_dma *p; 553 int dma_count; 554 555 sc = addr; 556 fmt = 0; 557 #ifdef DIAGNOSTIC 558 if (sc->sc_prun) 559 printf("cs4281_trigger_output: already running\n"); 560 #endif 561 sc->sc_prun = 1; 562 563 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 564 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 565 sc->sc_pintr = intr; 566 sc->sc_parg = arg; 567 568 /* stop playback DMA */ 569 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 570 571 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 572 param->precision, param->channels, param->encoding)); 573 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 574 continue; 575 if (p == NULL) { 576 printf("cs4281_trigger_output: bad addr %p\n", start); 577 return EINVAL; 578 } 579 580 sc->sc_pcount = blksize / sc->hw_blocksize; 581 sc->sc_ps = (char *)start; 582 sc->sc_pe = (char *)end; 583 sc->sc_pdma = p; 584 sc->sc_pbuf = KERNADDR(p); 585 sc->sc_pi = 0; 586 sc->sc_pn = sc->sc_ps; 587 if (blksize >= sc->dma_size) { 588 sc->sc_pn = sc->sc_ps + sc->dma_size; 589 memcpy(sc->sc_pbuf, start, sc->dma_size); 590 ++sc->sc_pi; 591 } else { 592 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 593 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 594 } 595 596 dma_count = sc->dma_size; 597 if (param->precision != 8) 598 dma_count /= 2; /* 16 bit */ 599 if (param->channels > 1) 600 dma_count /= 2; /* Stereo */ 601 602 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 603 (int)DMAADDR(p), dma_count)); 604 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 605 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 606 607 /* set playback format */ 608 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 609 if (param->precision == 8) 610 fmt |= DMRn_SIZE8; 611 if (param->channels == 1) 612 fmt |= DMRn_MONO; 613 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 614 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 615 fmt |= DMRn_BEND; 616 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 617 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 618 fmt |= DMRn_USIGN; 619 BA0WRITE4(sc, CS4281_DMR0, fmt); 620 621 /* set sample rate */ 622 sc->sc_prate = param->sample_rate; 623 cs4281_set_dac_rate(sc, param->sample_rate); 624 625 /* start DMA */ 626 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 627 /* Enable interrupts */ 628 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 629 630 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 631 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 632 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 633 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 634 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 635 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 636 BA0READ4(sc, CS4281_DACSR))); 637 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 638 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 639 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 640 641 return 0; 642 } 643 644 static int 645 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 646 void (*intr)(void *), void *arg, 647 const audio_params_t *param) 648 { 649 struct cs428x_softc *sc; 650 struct cs428x_dma *p; 651 uint32_t fmt; 652 int dma_count; 653 654 sc = addr; 655 fmt = 0; 656 #ifdef DIAGNOSTIC 657 if (sc->sc_rrun) 658 printf("cs4281_trigger_input: already running\n"); 659 #endif 660 sc->sc_rrun = 1; 661 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 662 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 663 sc->sc_rintr = intr; 664 sc->sc_rarg = arg; 665 666 /* stop recording DMA */ 667 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 668 669 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 670 continue; 671 if (!p) { 672 printf("cs4281_trigger_input: bad addr %p\n", start); 673 return EINVAL; 674 } 675 676 sc->sc_rcount = blksize / sc->hw_blocksize; 677 sc->sc_rs = (char *)start; 678 sc->sc_re = (char *)end; 679 sc->sc_rdma = p; 680 sc->sc_rbuf = KERNADDR(p); 681 sc->sc_ri = 0; 682 sc->sc_rn = sc->sc_rs; 683 684 dma_count = sc->dma_size; 685 if (param->precision != 8) 686 dma_count /= 2; 687 if (param->channels > 1) 688 dma_count /= 2; 689 690 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 691 (int)DMAADDR(p), dma_count)); 692 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 693 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 694 695 /* set recording format */ 696 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 697 if (param->precision == 8) 698 fmt |= DMRn_SIZE8; 699 if (param->channels == 1) 700 fmt |= DMRn_MONO; 701 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 702 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 703 fmt |= DMRn_BEND; 704 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 705 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 706 fmt |= DMRn_USIGN; 707 BA0WRITE4(sc, CS4281_DMR1, fmt); 708 709 /* set sample rate */ 710 sc->sc_rrate = param->sample_rate; 711 cs4281_set_adc_rate(sc, param->sample_rate); 712 713 /* Start DMA */ 714 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 715 /* Enable interrupts */ 716 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 717 718 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 719 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 720 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 721 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 722 723 return 0; 724 } 725 726 /* Power Hook */ 727 static void 728 cs4281_power(int why, void *v) 729 { 730 static uint32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 731 static uint32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 732 struct cs428x_softc *sc; 733 734 sc = (struct cs428x_softc *)v; 735 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 736 switch (why) { 737 case PWR_SUSPEND: 738 case PWR_STANDBY: 739 sc->sc_suspend = why; 740 741 /* save current playback status */ 742 if (sc->sc_prun) { 743 dcr0 = BA0READ4(sc, CS4281_DCR0); 744 dmr0 = BA0READ4(sc, CS4281_DMR0); 745 dbc0 = BA0READ4(sc, CS4281_DBC0); 746 dba0 = BA0READ4(sc, CS4281_DBA0); 747 } 748 749 /* save current capture status */ 750 if (sc->sc_rrun) { 751 dcr1 = BA0READ4(sc, CS4281_DCR1); 752 dmr1 = BA0READ4(sc, CS4281_DMR1); 753 dbc1 = BA0READ4(sc, CS4281_DBC1); 754 dba1 = BA0READ4(sc, CS4281_DBA1); 755 } 756 /* Stop DMA */ 757 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 758 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 759 break; 760 case PWR_RESUME: 761 if (sc->sc_suspend == PWR_RESUME) { 762 printf("cs4281_power: odd, resume without suspend.\n"); 763 sc->sc_suspend = why; 764 return; 765 } 766 sc->sc_suspend = why; 767 cs4281_init(sc, 0); 768 cs4281_reset_codec(sc); 769 770 /* restore ac97 registers */ 771 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 772 773 /* restore DMA related status */ 774 if (sc->sc_prun) { 775 cs4281_set_dac_rate(sc, sc->sc_prate); 776 BA0WRITE4(sc, CS4281_DBA0, dba0); 777 BA0WRITE4(sc, CS4281_DBC0, dbc0); 778 BA0WRITE4(sc, CS4281_DMR0, dmr0); 779 BA0WRITE4(sc, CS4281_DCR0, dcr0); 780 } 781 if (sc->sc_rrun) { 782 cs4281_set_adc_rate(sc, sc->sc_rrate); 783 BA0WRITE4(sc, CS4281_DBA1, dba1); 784 BA0WRITE4(sc, CS4281_DBC1, dbc1); 785 BA0WRITE4(sc, CS4281_DMR1, dmr1); 786 BA0WRITE4(sc, CS4281_DCR1, dcr1); 787 } 788 /* enable intterupts */ 789 if (sc->sc_prun || sc->sc_rrun) 790 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 791 break; 792 case PWR_SOFTSUSPEND: 793 case PWR_SOFTSTANDBY: 794 case PWR_SOFTRESUME: 795 break; 796 } 797 } 798 799 /* control AC97 codec */ 800 static int 801 cs4281_reset_codec(void *addr) 802 { 803 struct cs428x_softc *sc; 804 uint16_t data; 805 uint32_t dat32; 806 int n; 807 808 sc = addr; 809 810 DPRINTFN(3, ("cs4281_reset_codec\n")); 811 812 /* Reset codec */ 813 BA0WRITE4(sc, CS428X_ACCTL, 0); 814 delay(50); /* delay 50us */ 815 816 BA0WRITE4(sc, CS4281_SPMC, 0); 817 delay(100); /* delay 100us */ 818 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 819 #if defined(ENABLE_SECONDARY_CODEC) 820 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 821 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 822 #endif 823 delay(50000); /* XXX: delay 50ms */ 824 825 /* Enable ASYNC generation */ 826 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 827 828 /* Wait for codec ready. Linux driver waits 50ms here */ 829 n = 0; 830 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 831 delay(100); 832 if (++n > 1000) { 833 printf("reset_codec: AC97 codec ready timeout\n"); 834 return ETIMEDOUT; 835 } 836 } 837 #if defined(ENABLE_SECONDARY_CODEC) 838 /* secondary codec ready*/ 839 n = 0; 840 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 841 delay(100); 842 if (++n > 1000) 843 return 0; 844 } 845 #endif 846 /* Set the serial timing configuration */ 847 /* XXX: undocumented but the Linux driver do this */ 848 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 849 850 /* Wait for codec ready signal */ 851 n = 0; 852 do { 853 delay(1000); 854 if (++n > 1000) { 855 printf("%s: timeout waiting for codec ready\n", 856 sc->sc_dev.dv_xname); 857 return ETIMEDOUT; 858 } 859 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 860 } while (dat32 == 0); 861 862 /* Enable Valid Frame output on ASDOUT */ 863 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 864 865 /* Wait until codec calibration is finished. Codec register 26h */ 866 n = 0; 867 do { 868 delay(1); 869 if (++n > 1000) { 870 printf("%s: timeout waiting for codec calibration\n", 871 sc->sc_dev.dv_xname); 872 return ETIMEDOUT; 873 } 874 cs428x_read_codec(sc, AC97_REG_POWER, &data); 875 } while ((data & 0x0f) != 0x0f); 876 877 /* Set the serial timing configuration again */ 878 /* XXX: undocumented but the Linux driver do this */ 879 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 880 881 /* Wait until we've sampled input slots 3 & 4 as valid */ 882 n = 0; 883 do { 884 delay(1000); 885 if (++n > 1000) { 886 printf("%s: timeout waiting for sampled input slots as valid\n", 887 sc->sc_dev.dv_xname); 888 return ETIMEDOUT; 889 } 890 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 891 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 892 893 /* Start digital data transfer of audio data to the codec */ 894 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 895 return 0; 896 } 897 898 899 /* Internal functions */ 900 901 /* convert sample rate to register value */ 902 static uint8_t 903 cs4281_sr2regval(int rate) 904 { 905 uint8_t retval; 906 907 /* We don't have to change here. but anyway ... */ 908 if (rate > 48000) 909 rate = 48000; 910 if (rate < 6023) 911 rate = 6023; 912 913 switch (rate) { 914 case 8000: 915 retval = 5; 916 break; 917 case 11025: 918 retval = 4; 919 break; 920 case 16000: 921 retval = 3; 922 break; 923 case 22050: 924 retval = 2; 925 break; 926 case 44100: 927 retval = 1; 928 break; 929 case 48000: 930 retval = 0; 931 break; 932 default: 933 retval = 1536000/rate; /* == 24576000/(rate*16) */ 934 } 935 return retval; 936 } 937 938 static void 939 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 940 { 941 942 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 943 } 944 945 static void 946 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 947 { 948 949 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 950 } 951 952 static int 953 cs4281_init(struct cs428x_softc *sc, int init) 954 { 955 int n; 956 uint16_t data; 957 uint32_t dat32; 958 959 /* set "Configuration Write Protect" register to 960 * 0x4281 to allow to write */ 961 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 962 963 /* 964 * Unset "Full Power-Down bit of Extended PCI Power Management 965 * Control" register to release the reset state. 966 */ 967 dat32 = BA0READ4(sc, CS4281_EPPMC); 968 if (dat32 & EPPMC_FPDN) { 969 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 970 } 971 972 /* Start PLL out in known state */ 973 BA0WRITE4(sc, CS4281_CLKCR1, 0); 974 /* Start serial ports out in known state */ 975 BA0WRITE4(sc, CS4281_SERMC, 0); 976 977 /* Reset codec */ 978 BA0WRITE4(sc, CS428X_ACCTL, 0); 979 delay(50); /* delay 50us */ 980 981 BA0WRITE4(sc, CS4281_SPMC, 0); 982 delay(100); /* delay 100us */ 983 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 984 #if defined(ENABLE_SECONDARY_CODEC) 985 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 986 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 987 #endif 988 delay(50000); /* XXX: delay 50ms */ 989 990 /* Turn on Sound System clocks based on ABITCLK */ 991 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 992 delay(50000); /* XXX: delay 50ms */ 993 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 994 995 /* Set enables for sections that are needed in the SSPM registers */ 996 BA0WRITE4(sc, CS4281_SSPM, 997 SSPM_MIXEN | /* Mixer */ 998 SSPM_CSRCEN | /* Capture SRC */ 999 SSPM_PSRCEN | /* Playback SRC */ 1000 SSPM_JSEN | /* Joystick */ 1001 SSPM_ACLEN | /* AC LINK */ 1002 SSPM_FMEN /* FM */ 1003 ); 1004 1005 /* Wait for clock stabilization */ 1006 n = 0; 1007 #if 1 1008 /* what document says */ 1009 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1010 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1011 delay(100); 1012 if (++n > 1000) { 1013 printf("%s: timeout waiting for clock stabilization\n", 1014 sc->sc_dev.dv_xname); 1015 return -1; 1016 } 1017 } 1018 #else 1019 /* Cirrus driver for Linux does */ 1020 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1021 delay(1000); 1022 if (++n > 1000) { 1023 printf("%s: timeout waiting for clock stabilization\n", 1024 sc->sc_dev.dv_xname); 1025 return -1; 1026 } 1027 } 1028 #endif 1029 1030 /* Enable ASYNC generation */ 1031 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1032 1033 /* Wait for codec ready. Linux driver waits 50ms here */ 1034 n = 0; 1035 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1036 delay(100); 1037 if (++n > 1000) { 1038 printf("%s: timeout waiting for codec ready\n", 1039 sc->sc_dev.dv_xname); 1040 return -1; 1041 } 1042 } 1043 1044 #if defined(ENABLE_SECONDARY_CODEC) 1045 /* secondary codec ready*/ 1046 n = 0; 1047 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1048 delay(100); 1049 if (++n > 1000) { 1050 printf("%s: timeout waiting for secondary codec ready\n", 1051 sc->sc_dev.dv_xname); 1052 return -1; 1053 } 1054 } 1055 #endif 1056 1057 /* Set the serial timing configuration */ 1058 /* XXX: undocumented but the Linux driver do this */ 1059 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1060 1061 /* Wait for codec ready signal */ 1062 n = 0; 1063 do { 1064 delay(1000); 1065 if (++n > 1000) { 1066 printf("%s: timeout waiting for codec ready\n", 1067 sc->sc_dev.dv_xname); 1068 return -1; 1069 } 1070 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1071 } while (dat32 == 0); 1072 1073 /* Enable Valid Frame output on ASDOUT */ 1074 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1075 1076 /* Wait until codec calibration is finished. codec register 26h */ 1077 n = 0; 1078 do { 1079 delay(1); 1080 if (++n > 1000) { 1081 printf("%s: timeout waiting for codec calibration\n", 1082 sc->sc_dev.dv_xname); 1083 return -1; 1084 } 1085 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1086 } while ((data & 0x0f) != 0x0f); 1087 1088 /* Set the serial timing configuration again */ 1089 /* XXX: undocumented but the Linux driver do this */ 1090 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1091 1092 /* Wait until we've sampled input slots 3 & 4 as valid */ 1093 n = 0; 1094 do { 1095 delay(1000); 1096 if (++n > 1000) { 1097 printf("%s: timeout waiting for sampled input slots as valid\n", 1098 sc->sc_dev.dv_xname); 1099 return -1; 1100 } 1101 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1102 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1103 1104 /* Start digital data transfer of audio data to the codec */ 1105 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1106 1107 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1108 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1109 1110 /* Power on the DAC */ 1111 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1112 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1113 1114 /* Wait until we sample a DAC ready state. 1115 * Not documented, but Linux driver does. 1116 */ 1117 for (n = 0; n < 32; ++n) { 1118 delay(1000); 1119 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1120 if (data & 0x02) 1121 break; 1122 } 1123 1124 /* Power on the ADC */ 1125 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1126 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1127 1128 /* Wait until we sample ADC ready state. 1129 * Not documented, but Linux driver does. 1130 */ 1131 for (n = 0; n < 32; ++n) { 1132 delay(1000); 1133 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1134 if (data & 0x01) 1135 break; 1136 } 1137 1138 #if 0 1139 /* Initialize AC-Link features */ 1140 /* variable sample-rate support */ 1141 mem = BA0READ4(sc, CS4281_SERMC); 1142 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1143 BA0WRITE4(sc, CS4281_SERMC, mem); 1144 /* XXX: more... */ 1145 1146 /* Initialize SSCR register features */ 1147 /* XXX: hardware volume setting */ 1148 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1149 #endif 1150 1151 /* disable Sound Blaster Pro emulation */ 1152 /* XXX: 1153 * Cannot set since the documents does not describe which bit is 1154 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1155 * we can ignore it.*/ 1156 #if 0 1157 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1158 #endif 1159 1160 /* map AC97 PCM playback to DMA Channel 0 */ 1161 /* Reset FEN bit to setup first */ 1162 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1163 /* 1164 *| RS[4:0]/| | 1165 *| LS[4:0] | AC97 | Slot Function 1166 *|---------+--------+-------------------- 1167 *| 0 | 3 | Left PCM Playback 1168 *| 1 | 4 | Right PCM Playback 1169 *| 2 | 5 | Phone Line 1 DAC 1170 *| 3 | 6 | Center PCM Playback 1171 *.... 1172 * quoted from Table 29(p109) 1173 */ 1174 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1175 0x00 << 16 | /* LS[4:0] = 0 see above */ 1176 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1177 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1178 BA0WRITE4(sc, CS4281_FCR0, dat32); 1179 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1180 1181 /* map AC97 PCM record to DMA Channel 1 */ 1182 /* Reset FEN bit to setup first */ 1183 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1184 /* 1185 *| RS[4:0]/| 1186 *| LS[4:0] | AC97 | Slot Function 1187 *|---------+------+------------------- 1188 *| 10 | 3 | Left PCM Record 1189 *| 11 | 4 | Right PCM Record 1190 *| 12 | 5 | Phone Line 1 ADC 1191 *| 13 | 6 | Mic ADC 1192 *.... 1193 * quoted from Table 30(p109) 1194 */ 1195 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1196 0x0a << 16 | /* LS[4:0] = 10 See above */ 1197 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1198 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1199 1200 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1201 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1202 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1203 1204 #if 0 1205 /* Disable DMA Channel 2, 3 */ 1206 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1207 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1208 #endif 1209 1210 /* Set the SRC Slot Assignment accordingly */ 1211 /*| PLSS[4:0]/ 1212 *| PRSS[4:0] | AC97 | Slot Function 1213 *|-----------+------+---------------- 1214 *| 0 | 3 | Left PCM Playback 1215 *| 1 | 4 | Right PCM Playback 1216 *| 2 | 5 | phone line 1 DAC 1217 *| 3 | 6 | Center PCM Playback 1218 *| 4 | 7 | Left Surround PCM Playback 1219 *| 5 | 8 | Right Surround PCM Playback 1220 *...... 1221 * 1222 *| CLSS[4:0]/ 1223 *| CRSS[4:0] | AC97 | Codec |Slot Function 1224 *|-----------+------+-------+----------------- 1225 *| 10 | 3 |Primary| Left PCM Record 1226 *| 11 | 4 |Primary| Right PCM Record 1227 *| 12 | 5 |Primary| Phone Line 1 ADC 1228 *| 13 | 6 |Primary| Mic ADC 1229 *|..... 1230 *| 20 | 3 | Sec. | Left PCM Record 1231 *| 21 | 4 | Sec. | Right PCM Record 1232 *| 22 | 5 | Sec. | Phone Line 1 ADC 1233 *| 23 | 6 | Sec. | Mic ADC 1234 */ 1235 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1236 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1237 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1238 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1239 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1240 1241 /* Set interrupt to occurred at Half and Full terminal 1242 * count interrupt enable for DMA channel 0 and 1. 1243 * To keep DMA stop, set MSK. 1244 */ 1245 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1246 BA0WRITE4(sc, CS4281_DCR0, dat32); 1247 BA0WRITE4(sc, CS4281_DCR1, dat32); 1248 1249 /* Set Auto-Initialize Contorl enable */ 1250 BA0WRITE4(sc, CS4281_DMR0, 1251 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1252 BA0WRITE4(sc, CS4281_DMR1, 1253 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1254 1255 /* Clear DMA Mask in HIMR */ 1256 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1257 BA0WRITE4(sc, CS4281_HIMR, 1258 BA0READ4(sc, CS4281_HIMR) & dat32); 1259 1260 /* set current status */ 1261 if (init != 0) { 1262 sc->sc_prun = 0; 1263 sc->sc_rrun = 0; 1264 } 1265 1266 /* setup playback volume */ 1267 BA0WRITE4(sc, CS4281_PPRVC, 7); 1268 BA0WRITE4(sc, CS4281_PPLVC, 7); 1269 1270 return 0; 1271 } 1272
Indexes created Wed Oct 01 07:09:59 GMT 2025