cs4281.c revision 1.26.2.7
1 /* $NetBSD: cs4281.c,v 1.26.2.7 2008/03/24 09:38:50 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.26.2.7 2008/03/24 09:38:50 yamt Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <sys/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(struct device *, struct cfdata *, void *); 84 static void cs4281_attach(struct device *, struct device *, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static bool cs4281_suspend(device_t PMF_FN_PROTO); 110 static bool cs4281_resume(device_t PMF_FN_PROTO); 111 112 static const struct audio_hw_if cs4281_hw_if = { 113 NULL, /* open */ 114 NULL, /* close */ 115 NULL, 116 cs4281_query_encoding, 117 cs4281_set_params, 118 cs428x_round_blocksize, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 NULL, 124 cs4281_halt_output, 125 cs4281_halt_input, 126 NULL, 127 cs4281_getdev, 128 NULL, 129 cs428x_mixer_set_port, 130 cs428x_mixer_get_port, 131 cs428x_query_devinfo, 132 cs428x_malloc, 133 cs428x_free, 134 cs428x_round_buffersize, 135 cs428x_mappage, 136 cs428x_get_props, 137 cs4281_trigger_output, 138 cs4281_trigger_input, 139 NULL, 140 NULL, 141 }; 142 143 #if NMIDI > 0 && 0 144 /* Midi Interface */ 145 static void cs4281_midi_close(void*); 146 static void cs4281_midi_getinfo(void *, struct midi_info *); 147 static int cs4281_midi_open(void *, int, void (*)(void *, int), 148 void (*)(void *), void *); 149 static int cs4281_midi_output(void *, int); 150 151 static const struct midi_hw_if cs4281_midi_hw_if = { 152 cs4281_midi_open, 153 cs4281_midi_close, 154 cs4281_midi_output, 155 cs4281_midi_getinfo, 156 0, 157 }; 158 #endif 159 160 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 161 cs4281_match, cs4281_attach, NULL, NULL); 162 163 static struct audio_device cs4281_device = { 164 "CS4281", 165 "", 166 "cs4281" 167 }; 168 169 170 static int 171 cs4281_match(struct device *parent, struct cfdata *match, 172 void *aux) 173 { 174 struct pci_attach_args *pa; 175 176 pa = (struct pci_attach_args *)aux; 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 178 return 0; 179 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 180 return 1; 181 return 0; 182 } 183 184 static void 185 cs4281_attach(struct device *parent, struct device *self, void *aux) 186 { 187 struct cs428x_softc *sc; 188 struct pci_attach_args *pa; 189 pci_chipset_tag_t pc; 190 char const *intrstr; 191 pcireg_t reg; 192 char devinfo[256]; 193 int error; 194 195 sc = (struct cs428x_softc *)self; 196 pa = (struct pci_attach_args *)aux; 197 pc = pa->pa_pc; 198 aprint_naive(": Audio controller\n"); 199 200 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 201 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 202 PCI_REVISION(pa->pa_class)); 203 204 sc->sc_pc = pa->pa_pc; 205 sc->sc_pt = pa->pa_tag; 206 207 /* Map I/O register */ 208 if (pci_mapreg_map(pa, PCI_BA0, 209 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 210 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 211 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n"); 212 return; 213 } 214 if (pci_mapreg_map(pa, PCI_BA1, 215 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 216 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 217 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n"); 218 return; 219 } 220 221 sc->sc_dmatag = pa->pa_dmat; 222 223 /* power up chip */ 224 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 225 pci_activate_null)) && error != EOPNOTSUPP) { 226 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 227 return; 228 } 229 230 /* Enable the device (set bus master flag) */ 231 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 233 reg | PCI_COMMAND_MASTER_ENABLE); 234 235 #if 0 236 /* LATENCY_TIMER setting */ 237 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 238 if (PCI_LATTIMER(temp1) < 32) { 239 temp1 &= 0xffff00ff; 240 temp1 |= 0x00002000; 241 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 242 } 243 #endif 244 245 /* Map and establish the interrupt. */ 246 if (pci_intr_map(pa, &sc->intrh)) { 247 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 248 return; 249 } 250 intrstr = pci_intr_string(pc, sc->intrh); 251 252 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 253 cs4281_intr, sc); 254 if (sc->sc_ih == NULL) { 255 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 256 if (intrstr != NULL) 257 aprint_error(" at %s", intrstr); 258 aprint_error("\n"); 259 return; 260 } 261 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 262 263 /* 264 * Sound System start-up 265 */ 266 if (cs4281_init(sc, 1) != 0) 267 return; 268 269 sc->type = TYPE_CS4281; 270 sc->halt_input = cs4281_halt_input; 271 sc->halt_output = cs4281_halt_output; 272 273 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 274 sc->dma_align = 0x10; 275 sc->hw_blocksize = sc->dma_size / 2; 276 277 /* AC 97 attachment */ 278 sc->host_if.arg = sc; 279 sc->host_if.attach = cs428x_attach_codec; 280 sc->host_if.read = cs428x_read_codec; 281 sc->host_if.write = cs428x_write_codec; 282 sc->host_if.reset = cs4281_reset_codec; 283 if (ac97_attach(&sc->host_if, self) != 0) { 284 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n"); 285 return; 286 } 287 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 288 289 #if NMIDI > 0 && 0 290 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 291 #endif 292 293 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 294 aprint_error_dev(self, "couldn't establish power handler\n"); 295 } 296 297 static int 298 cs4281_intr(void *p) 299 { 300 struct cs428x_softc *sc; 301 uint32_t intr, hdsr0, hdsr1; 302 char *empty_dma; 303 int handled; 304 305 sc = p; 306 handled = 0; 307 hdsr0 = 0; 308 hdsr1 = 0; 309 310 /* grab interrupt register */ 311 intr = BA0READ4(sc, CS4281_HISR); 312 313 DPRINTF(("cs4281_intr:")); 314 /* not for me */ 315 if ((intr & HISR_INTENA) == 0) { 316 /* clear the interrupt register */ 317 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 318 return 0; 319 } 320 321 if (intr & HISR_DMA0) 322 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 323 if (intr & HISR_DMA1) 324 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 325 /* clear the interrupt register */ 326 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 327 328 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 329 intr, hdsr0, hdsr1)); 330 331 /* Playback Interrupt */ 332 if (intr & HISR_DMA0) { 333 handled = 1; 334 if (sc->sc_prun) { 335 DPRINTF((" PB DMA 0x%x(%d)", 336 (int)BA0READ4(sc, CS4281_DCA0), 337 (int)BA0READ4(sc, CS4281_DCC0))); 338 if ((sc->sc_pi%sc->sc_pcount) == 0) 339 sc->sc_pintr(sc->sc_parg); 340 /* copy buffer */ 341 ++sc->sc_pi; 342 empty_dma = sc->sc_pdma->addr; 343 if (sc->sc_pi&1) 344 empty_dma += sc->hw_blocksize; 345 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 346 sc->sc_pn += sc->hw_blocksize; 347 if (sc->sc_pn >= sc->sc_pe) 348 sc->sc_pn = sc->sc_ps; 349 } else { 350 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n"); 351 } 352 } 353 if (intr & HISR_DMA1) { 354 handled = 1; 355 if (sc->sc_rrun) { 356 /* copy from DMA */ 357 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 358 (int)BA0READ4(sc, CS4281_DCC1))); 359 ++sc->sc_ri; 360 empty_dma = sc->sc_rdma->addr; 361 if ((sc->sc_ri & 1) == 0) 362 empty_dma += sc->hw_blocksize; 363 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 364 sc->sc_rn += sc->hw_blocksize; 365 if (sc->sc_rn >= sc->sc_re) 366 sc->sc_rn = sc->sc_rs; 367 if ((sc->sc_ri % sc->sc_rcount) == 0) 368 sc->sc_rintr(sc->sc_rarg); 369 } else { 370 aprint_error_dev(&sc->sc_dev, 371 "unexpected record intr\n"); 372 } 373 } 374 DPRINTF(("\n")); 375 376 return handled; 377 } 378 379 static int 380 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 381 { 382 383 switch (fp->index) { 384 case 0: 385 strcpy(fp->name, AudioEulinear); 386 fp->encoding = AUDIO_ENCODING_ULINEAR; 387 fp->precision = 8; 388 fp->flags = 0; 389 break; 390 case 1: 391 strcpy(fp->name, AudioEmulaw); 392 fp->encoding = AUDIO_ENCODING_ULAW; 393 fp->precision = 8; 394 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 395 break; 396 case 2: 397 strcpy(fp->name, AudioEalaw); 398 fp->encoding = AUDIO_ENCODING_ALAW; 399 fp->precision = 8; 400 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 401 break; 402 case 3: 403 strcpy(fp->name, AudioEslinear); 404 fp->encoding = AUDIO_ENCODING_SLINEAR; 405 fp->precision = 8; 406 fp->flags = 0; 407 break; 408 case 4: 409 strcpy(fp->name, AudioEslinear_le); 410 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 411 fp->precision = 16; 412 fp->flags = 0; 413 break; 414 case 5: 415 strcpy(fp->name, AudioEulinear_le); 416 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 417 fp->precision = 16; 418 fp->flags = 0; 419 break; 420 case 6: 421 strcpy(fp->name, AudioEslinear_be); 422 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 423 fp->precision = 16; 424 fp->flags = 0; 425 break; 426 case 7: 427 strcpy(fp->name, AudioEulinear_be); 428 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 429 fp->precision = 16; 430 fp->flags = 0; 431 break; 432 default: 433 return EINVAL; 434 } 435 return 0; 436 } 437 438 static int 439 cs4281_set_params(void *addr, int setmode, int usemode, 440 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 441 stream_filter_list_t *rfil) 442 { 443 audio_params_t hw; 444 struct cs428x_softc *sc; 445 audio_params_t *p; 446 stream_filter_list_t *fil; 447 int mode; 448 449 sc = addr; 450 for (mode = AUMODE_RECORD; mode != -1; 451 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 452 if ((setmode & mode) == 0) 453 continue; 454 455 p = mode == AUMODE_PLAY ? play : rec; 456 457 if (p == play) { 458 DPRINTFN(5, 459 ("play: sample=%u precision=%u channels=%u\n", 460 p->sample_rate, p->precision, p->channels)); 461 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 462 (p->precision != 8 && p->precision != 16) || 463 (p->channels != 1 && p->channels != 2)) { 464 return EINVAL; 465 } 466 } else { 467 DPRINTFN(5, 468 ("rec: sample=%u precision=%u channels=%u\n", 469 p->sample_rate, p->precision, p->channels)); 470 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 471 (p->precision != 8 && p->precision != 16) || 472 (p->channels != 1 && p->channels != 2)) { 473 return EINVAL; 474 } 475 } 476 hw = *p; 477 fil = mode == AUMODE_PLAY ? pfil : rfil; 478 479 switch (p->encoding) { 480 case AUDIO_ENCODING_SLINEAR_BE: 481 break; 482 case AUDIO_ENCODING_SLINEAR_LE: 483 break; 484 case AUDIO_ENCODING_ULINEAR_BE: 485 break; 486 case AUDIO_ENCODING_ULINEAR_LE: 487 break; 488 case AUDIO_ENCODING_ULAW: 489 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 490 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 491 : linear8_to_mulaw, &hw); 492 break; 493 case AUDIO_ENCODING_ALAW: 494 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 495 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 496 : linear8_to_alaw, &hw); 497 break; 498 default: 499 return EINVAL; 500 } 501 } 502 503 /* set sample rate */ 504 cs4281_set_dac_rate(sc, play->sample_rate); 505 cs4281_set_adc_rate(sc, rec->sample_rate); 506 return 0; 507 } 508 509 static int 510 cs4281_halt_output(void *addr) 511 { 512 struct cs428x_softc *sc; 513 514 sc = addr; 515 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 516 sc->sc_prun = 0; 517 return 0; 518 } 519 520 static int 521 cs4281_halt_input(void *addr) 522 { 523 struct cs428x_softc *sc; 524 525 sc = addr; 526 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 527 sc->sc_rrun = 0; 528 return 0; 529 } 530 531 static int 532 cs4281_getdev(void *addr, struct audio_device *retp) 533 { 534 535 *retp = cs4281_device; 536 return 0; 537 } 538 539 static int 540 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 541 void (*intr)(void *), void *arg, 542 const audio_params_t *param) 543 { 544 struct cs428x_softc *sc; 545 uint32_t fmt; 546 struct cs428x_dma *p; 547 int dma_count; 548 549 sc = addr; 550 fmt = 0; 551 #ifdef DIAGNOSTIC 552 if (sc->sc_prun) 553 printf("cs4281_trigger_output: already running\n"); 554 #endif 555 sc->sc_prun = 1; 556 557 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 558 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 559 sc->sc_pintr = intr; 560 sc->sc_parg = arg; 561 562 /* stop playback DMA */ 563 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 564 565 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 566 param->precision, param->channels, param->encoding)); 567 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 568 continue; 569 if (p == NULL) { 570 printf("cs4281_trigger_output: bad addr %p\n", start); 571 return EINVAL; 572 } 573 574 sc->sc_pcount = blksize / sc->hw_blocksize; 575 sc->sc_ps = (char *)start; 576 sc->sc_pe = (char *)end; 577 sc->sc_pdma = p; 578 sc->sc_pbuf = KERNADDR(p); 579 sc->sc_pi = 0; 580 sc->sc_pn = sc->sc_ps; 581 if (blksize >= sc->dma_size) { 582 sc->sc_pn = sc->sc_ps + sc->dma_size; 583 memcpy(sc->sc_pbuf, start, sc->dma_size); 584 ++sc->sc_pi; 585 } else { 586 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 587 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 588 } 589 590 dma_count = sc->dma_size; 591 if (param->precision != 8) 592 dma_count /= 2; /* 16 bit */ 593 if (param->channels > 1) 594 dma_count /= 2; /* Stereo */ 595 596 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 597 (int)DMAADDR(p), dma_count)); 598 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 599 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 600 601 /* set playback format */ 602 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 603 if (param->precision == 8) 604 fmt |= DMRn_SIZE8; 605 if (param->channels == 1) 606 fmt |= DMRn_MONO; 607 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 608 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 609 fmt |= DMRn_BEND; 610 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 611 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 612 fmt |= DMRn_USIGN; 613 BA0WRITE4(sc, CS4281_DMR0, fmt); 614 615 /* set sample rate */ 616 sc->sc_prate = param->sample_rate; 617 cs4281_set_dac_rate(sc, param->sample_rate); 618 619 /* start DMA */ 620 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 621 /* Enable interrupts */ 622 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 623 624 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 625 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 626 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 627 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 628 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 629 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 630 BA0READ4(sc, CS4281_DACSR))); 631 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 632 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 633 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 634 635 return 0; 636 } 637 638 static int 639 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 640 void (*intr)(void *), void *arg, 641 const audio_params_t *param) 642 { 643 struct cs428x_softc *sc; 644 struct cs428x_dma *p; 645 uint32_t fmt; 646 int dma_count; 647 648 sc = addr; 649 fmt = 0; 650 #ifdef DIAGNOSTIC 651 if (sc->sc_rrun) 652 printf("cs4281_trigger_input: already running\n"); 653 #endif 654 sc->sc_rrun = 1; 655 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 656 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 657 sc->sc_rintr = intr; 658 sc->sc_rarg = arg; 659 660 /* stop recording DMA */ 661 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 662 663 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 664 continue; 665 if (!p) { 666 printf("cs4281_trigger_input: bad addr %p\n", start); 667 return EINVAL; 668 } 669 670 sc->sc_rcount = blksize / sc->hw_blocksize; 671 sc->sc_rs = (char *)start; 672 sc->sc_re = (char *)end; 673 sc->sc_rdma = p; 674 sc->sc_rbuf = KERNADDR(p); 675 sc->sc_ri = 0; 676 sc->sc_rn = sc->sc_rs; 677 678 dma_count = sc->dma_size; 679 if (param->precision != 8) 680 dma_count /= 2; 681 if (param->channels > 1) 682 dma_count /= 2; 683 684 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 685 (int)DMAADDR(p), dma_count)); 686 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 687 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 688 689 /* set recording format */ 690 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 691 if (param->precision == 8) 692 fmt |= DMRn_SIZE8; 693 if (param->channels == 1) 694 fmt |= DMRn_MONO; 695 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 696 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 697 fmt |= DMRn_BEND; 698 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 699 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 700 fmt |= DMRn_USIGN; 701 BA0WRITE4(sc, CS4281_DMR1, fmt); 702 703 /* set sample rate */ 704 sc->sc_rrate = param->sample_rate; 705 cs4281_set_adc_rate(sc, param->sample_rate); 706 707 /* Start DMA */ 708 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 709 /* Enable interrupts */ 710 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 711 712 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 713 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 714 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 715 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 716 717 return 0; 718 } 719 720 static bool 721 cs4281_suspend(device_t dv PMF_FN_ARGS) 722 { 723 struct cs428x_softc *sc = device_private(dv); 724 725 /* save current playback status */ 726 if (sc->sc_prun) { 727 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 728 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 729 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 730 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 731 } 732 733 /* save current capture status */ 734 if (sc->sc_rrun) { 735 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 736 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 737 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 738 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 739 } 740 /* Stop DMA */ 741 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 742 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 743 744 return true; 745 } 746 747 static bool 748 cs4281_resume(device_t dv PMF_FN_ARGS) 749 { 750 struct cs428x_softc *sc = device_private(dv); 751 752 cs4281_init(sc, 0); 753 cs4281_reset_codec(sc); 754 755 /* restore ac97 registers */ 756 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 757 758 /* restore DMA related status */ 759 if (sc->sc_prun) { 760 cs4281_set_dac_rate(sc, sc->sc_prate); 761 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 762 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 763 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 764 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 765 } 766 if (sc->sc_rrun) { 767 cs4281_set_adc_rate(sc, sc->sc_rrate); 768 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 769 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 770 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 771 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 772 } 773 /* enable intterupts */ 774 if (sc->sc_prun || sc->sc_rrun) 775 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 776 777 return true; 778 } 779 780 /* control AC97 codec */ 781 static int 782 cs4281_reset_codec(void *addr) 783 { 784 struct cs428x_softc *sc; 785 uint16_t data; 786 uint32_t dat32; 787 int n; 788 789 sc = addr; 790 791 DPRINTFN(3, ("cs4281_reset_codec\n")); 792 793 /* Reset codec */ 794 BA0WRITE4(sc, CS428X_ACCTL, 0); 795 delay(50); /* delay 50us */ 796 797 BA0WRITE4(sc, CS4281_SPMC, 0); 798 delay(100); /* delay 100us */ 799 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 800 #if defined(ENABLE_SECONDARY_CODEC) 801 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 802 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 803 #endif 804 delay(50000); /* XXX: delay 50ms */ 805 806 /* Enable ASYNC generation */ 807 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 808 809 /* Wait for codec ready. Linux driver waits 50ms here */ 810 n = 0; 811 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 812 delay(100); 813 if (++n > 1000) { 814 printf("reset_codec: AC97 codec ready timeout\n"); 815 return ETIMEDOUT; 816 } 817 } 818 #if defined(ENABLE_SECONDARY_CODEC) 819 /* secondary codec ready*/ 820 n = 0; 821 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 822 delay(100); 823 if (++n > 1000) 824 return 0; 825 } 826 #endif 827 /* Set the serial timing configuration */ 828 /* XXX: undocumented but the Linux driver do this */ 829 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 830 831 /* Wait for codec ready signal */ 832 n = 0; 833 do { 834 delay(1000); 835 if (++n > 1000) { 836 aprint_error_dev(&sc->sc_dev, 837 "timeout waiting for codec ready\n"); 838 return ETIMEDOUT; 839 } 840 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 841 } while (dat32 == 0); 842 843 /* Enable Valid Frame output on ASDOUT */ 844 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 845 846 /* Wait until codec calibration is finished. Codec register 26h */ 847 n = 0; 848 do { 849 delay(1); 850 if (++n > 1000) { 851 aprint_error_dev(&sc->sc_dev, 852 "timeout waiting for codec calibration\n"); 853 return ETIMEDOUT; 854 } 855 cs428x_read_codec(sc, AC97_REG_POWER, &data); 856 } while ((data & 0x0f) != 0x0f); 857 858 /* Set the serial timing configuration again */ 859 /* XXX: undocumented but the Linux driver do this */ 860 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 861 862 /* Wait until we've sampled input slots 3 & 4 as valid */ 863 n = 0; 864 do { 865 delay(1000); 866 if (++n > 1000) { 867 aprint_error_dev(&sc->sc_dev, "timeout waiting for " 868 "sampled input slots as valid\n"); 869 return ETIMEDOUT; 870 } 871 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 872 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 873 874 /* Start digital data transfer of audio data to the codec */ 875 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 876 return 0; 877 } 878 879 880 /* Internal functions */ 881 882 /* convert sample rate to register value */ 883 static uint8_t 884 cs4281_sr2regval(int rate) 885 { 886 uint8_t retval; 887 888 /* We don't have to change here. but anyway ... */ 889 if (rate > 48000) 890 rate = 48000; 891 if (rate < 6023) 892 rate = 6023; 893 894 switch (rate) { 895 case 8000: 896 retval = 5; 897 break; 898 case 11025: 899 retval = 4; 900 break; 901 case 16000: 902 retval = 3; 903 break; 904 case 22050: 905 retval = 2; 906 break; 907 case 44100: 908 retval = 1; 909 break; 910 case 48000: 911 retval = 0; 912 break; 913 default: 914 retval = 1536000/rate; /* == 24576000/(rate*16) */ 915 } 916 return retval; 917 } 918 919 static void 920 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 921 { 922 923 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 924 } 925 926 static void 927 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 928 { 929 930 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 931 } 932 933 static int 934 cs4281_init(struct cs428x_softc *sc, int init) 935 { 936 int n; 937 uint16_t data; 938 uint32_t dat32; 939 940 /* set "Configuration Write Protect" register to 941 * 0x4281 to allow to write */ 942 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 943 944 /* 945 * Unset "Full Power-Down bit of Extended PCI Power Management 946 * Control" register to release the reset state. 947 */ 948 dat32 = BA0READ4(sc, CS4281_EPPMC); 949 if (dat32 & EPPMC_FPDN) { 950 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 951 } 952 953 /* Start PLL out in known state */ 954 BA0WRITE4(sc, CS4281_CLKCR1, 0); 955 /* Start serial ports out in known state */ 956 BA0WRITE4(sc, CS4281_SERMC, 0); 957 958 /* Reset codec */ 959 BA0WRITE4(sc, CS428X_ACCTL, 0); 960 delay(50); /* delay 50us */ 961 962 BA0WRITE4(sc, CS4281_SPMC, 0); 963 delay(100); /* delay 100us */ 964 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 965 #if defined(ENABLE_SECONDARY_CODEC) 966 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 967 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 968 #endif 969 delay(50000); /* XXX: delay 50ms */ 970 971 /* Turn on Sound System clocks based on ABITCLK */ 972 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 973 delay(50000); /* XXX: delay 50ms */ 974 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 975 976 /* Set enables for sections that are needed in the SSPM registers */ 977 BA0WRITE4(sc, CS4281_SSPM, 978 SSPM_MIXEN | /* Mixer */ 979 SSPM_CSRCEN | /* Capture SRC */ 980 SSPM_PSRCEN | /* Playback SRC */ 981 SSPM_JSEN | /* Joystick */ 982 SSPM_ACLEN | /* AC LINK */ 983 SSPM_FMEN /* FM */ 984 ); 985 986 /* Wait for clock stabilization */ 987 n = 0; 988 #if 1 989 /* what document says */ 990 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 991 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 992 delay(100); 993 if (++n > 1000) { 994 aprint_error_dev(&sc->sc_dev, 995 "timeout waiting for clock stabilization\n"); 996 return -1; 997 } 998 } 999 #else 1000 /* Cirrus driver for Linux does */ 1001 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1002 delay(1000); 1003 if (++n > 1000) { 1004 aprint_error_dev(&sc->sc_dev, 1005 "timeout waiting for clock stabilization\n"); 1006 return -1; 1007 } 1008 } 1009 #endif 1010 1011 /* Enable ASYNC generation */ 1012 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1013 1014 /* Wait for codec ready. Linux driver waits 50ms here */ 1015 n = 0; 1016 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1017 delay(100); 1018 if (++n > 1000) { 1019 aprint_error_dev(&sc->sc_dev, 1020 "timeout waiting for codec ready\n"); 1021 return -1; 1022 } 1023 } 1024 1025 #if defined(ENABLE_SECONDARY_CODEC) 1026 /* secondary codec ready*/ 1027 n = 0; 1028 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1029 delay(100); 1030 if (++n > 1000) { 1031 aprint_error_dev(&sc->sc_dev, 1032 "timeout waiting for secondary codec ready\n"); 1033 return -1; 1034 } 1035 } 1036 #endif 1037 1038 /* Set the serial timing configuration */ 1039 /* XXX: undocumented but the Linux driver do this */ 1040 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1041 1042 /* Wait for codec ready signal */ 1043 n = 0; 1044 do { 1045 delay(1000); 1046 if (++n > 1000) { 1047 aprint_error_dev(&sc->sc_dev, 1048 "timeout waiting for codec ready\n"); 1049 return -1; 1050 } 1051 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1052 } while (dat32 == 0); 1053 1054 /* Enable Valid Frame output on ASDOUT */ 1055 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1056 1057 /* Wait until codec calibration is finished. codec register 26h */ 1058 n = 0; 1059 do { 1060 delay(1); 1061 if (++n > 1000) { 1062 aprint_error_dev(&sc->sc_dev, 1063 "timeout waiting for codec calibration\n"); 1064 return -1; 1065 } 1066 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1067 } while ((data & 0x0f) != 0x0f); 1068 1069 /* Set the serial timing configuration again */ 1070 /* XXX: undocumented but the Linux driver do this */ 1071 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1072 1073 /* Wait until we've sampled input slots 3 & 4 as valid */ 1074 n = 0; 1075 do { 1076 delay(1000); 1077 if (++n > 1000) { 1078 aprint_error_dev(&sc->sc_dev, "timeout waiting for " 1079 "sampled input slots as valid\n"); 1080 return -1; 1081 } 1082 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1083 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1084 1085 /* Start digital data transfer of audio data to the codec */ 1086 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1087 1088 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1089 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1090 1091 /* Power on the DAC */ 1092 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1093 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1094 1095 /* Wait until we sample a DAC ready state. 1096 * Not documented, but Linux driver does. 1097 */ 1098 for (n = 0; n < 32; ++n) { 1099 delay(1000); 1100 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1101 if (data & 0x02) 1102 break; 1103 } 1104 1105 /* Power on the ADC */ 1106 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1107 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1108 1109 /* Wait until we sample ADC ready state. 1110 * Not documented, but Linux driver does. 1111 */ 1112 for (n = 0; n < 32; ++n) { 1113 delay(1000); 1114 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1115 if (data & 0x01) 1116 break; 1117 } 1118 1119 #if 0 1120 /* Initialize AC-Link features */ 1121 /* variable sample-rate support */ 1122 mem = BA0READ4(sc, CS4281_SERMC); 1123 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1124 BA0WRITE4(sc, CS4281_SERMC, mem); 1125 /* XXX: more... */ 1126 1127 /* Initialize SSCR register features */ 1128 /* XXX: hardware volume setting */ 1129 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1130 #endif 1131 1132 /* disable Sound Blaster Pro emulation */ 1133 /* XXX: 1134 * Cannot set since the documents does not describe which bit is 1135 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1136 * we can ignore it.*/ 1137 #if 0 1138 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1139 #endif 1140 1141 /* map AC97 PCM playback to DMA Channel 0 */ 1142 /* Reset FEN bit to setup first */ 1143 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1144 /* 1145 *| RS[4:0]/| | 1146 *| LS[4:0] | AC97 | Slot Function 1147 *|---------+--------+-------------------- 1148 *| 0 | 3 | Left PCM Playback 1149 *| 1 | 4 | Right PCM Playback 1150 *| 2 | 5 | Phone Line 1 DAC 1151 *| 3 | 6 | Center PCM Playback 1152 *.... 1153 * quoted from Table 29(p109) 1154 */ 1155 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1156 0x00 << 16 | /* LS[4:0] = 0 see above */ 1157 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1158 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1159 BA0WRITE4(sc, CS4281_FCR0, dat32); 1160 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1161 1162 /* map AC97 PCM record to DMA Channel 1 */ 1163 /* Reset FEN bit to setup first */ 1164 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1165 /* 1166 *| RS[4:0]/| 1167 *| LS[4:0] | AC97 | Slot Function 1168 *|---------+------+------------------- 1169 *| 10 | 3 | Left PCM Record 1170 *| 11 | 4 | Right PCM Record 1171 *| 12 | 5 | Phone Line 1 ADC 1172 *| 13 | 6 | Mic ADC 1173 *.... 1174 * quoted from Table 30(p109) 1175 */ 1176 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1177 0x0a << 16 | /* LS[4:0] = 10 See above */ 1178 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1179 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1180 1181 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1182 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1183 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1184 1185 #if 0 1186 /* Disable DMA Channel 2, 3 */ 1187 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1188 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1189 #endif 1190 1191 /* Set the SRC Slot Assignment accordingly */ 1192 /*| PLSS[4:0]/ 1193 *| PRSS[4:0] | AC97 | Slot Function 1194 *|-----------+------+---------------- 1195 *| 0 | 3 | Left PCM Playback 1196 *| 1 | 4 | Right PCM Playback 1197 *| 2 | 5 | phone line 1 DAC 1198 *| 3 | 6 | Center PCM Playback 1199 *| 4 | 7 | Left Surround PCM Playback 1200 *| 5 | 8 | Right Surround PCM Playback 1201 *...... 1202 * 1203 *| CLSS[4:0]/ 1204 *| CRSS[4:0] | AC97 | Codec |Slot Function 1205 *|-----------+------+-------+----------------- 1206 *| 10 | 3 |Primary| Left PCM Record 1207 *| 11 | 4 |Primary| Right PCM Record 1208 *| 12 | 5 |Primary| Phone Line 1 ADC 1209 *| 13 | 6 |Primary| Mic ADC 1210 *|..... 1211 *| 20 | 3 | Sec. | Left PCM Record 1212 *| 21 | 4 | Sec. | Right PCM Record 1213 *| 22 | 5 | Sec. | Phone Line 1 ADC 1214 *| 23 | 6 | Sec. | Mic ADC 1215 */ 1216 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1217 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1218 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1219 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1220 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1221 1222 /* Set interrupt to occurred at Half and Full terminal 1223 * count interrupt enable for DMA channel 0 and 1. 1224 * To keep DMA stop, set MSK. 1225 */ 1226 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1227 BA0WRITE4(sc, CS4281_DCR0, dat32); 1228 BA0WRITE4(sc, CS4281_DCR1, dat32); 1229 1230 /* Set Auto-Initialize Contorl enable */ 1231 BA0WRITE4(sc, CS4281_DMR0, 1232 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1233 BA0WRITE4(sc, CS4281_DMR1, 1234 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1235 1236 /* Clear DMA Mask in HIMR */ 1237 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1238 BA0WRITE4(sc, CS4281_HIMR, 1239 BA0READ4(sc, CS4281_HIMR) & dat32); 1240 1241 /* set current status */ 1242 if (init != 0) { 1243 sc->sc_prun = 0; 1244 sc->sc_rrun = 0; 1245 } 1246 1247 /* setup playback volume */ 1248 BA0WRITE4(sc, CS4281_PPRVC, 7); 1249 BA0WRITE4(sc, CS4281_PPLVC, 7); 1250 1251 return 0; 1252 } 1253
Indexes created Thu Oct 02 10:09:58 GMT 2025