cs4281.c revision 1.29
1 /* $NetBSD: cs4281.c,v 1.29 2006/06/17 23:34:26 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.29 2006/06/17 23:34:26 christos Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(struct device *, struct cfdata *, void *); 84 static void cs4281_attach(struct device *, struct device *, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static void cs4281_power(int, void *); 110 111 static const struct audio_hw_if cs4281_hw_if = { 112 NULL, /* open */ 113 NULL, /* close */ 114 NULL, 115 cs4281_query_encoding, 116 cs4281_set_params, 117 cs428x_round_blocksize, 118 NULL, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 cs4281_halt_output, 124 cs4281_halt_input, 125 NULL, 126 cs4281_getdev, 127 NULL, 128 cs428x_mixer_set_port, 129 cs428x_mixer_get_port, 130 cs428x_query_devinfo, 131 cs428x_malloc, 132 cs428x_free, 133 cs428x_round_buffersize, 134 cs428x_mappage, 135 cs428x_get_props, 136 cs4281_trigger_output, 137 cs4281_trigger_input, 138 NULL, 139 }; 140 141 #if NMIDI > 0 && 0 142 /* Midi Interface */ 143 static void cs4281_midi_close(void*); 144 static void cs4281_midi_getinfo(void *, struct midi_info *); 145 static int cs4281_midi_open(void *, int, void (*)(void *, int), 146 void (*)(void *), void *); 147 static int cs4281_midi_output(void *, int); 148 149 static const struct midi_hw_if cs4281_midi_hw_if = { 150 cs4281_midi_open, 151 cs4281_midi_close, 152 cs4281_midi_output, 153 cs4281_midi_getinfo, 154 0, 155 }; 156 #endif 157 158 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 159 cs4281_match, cs4281_attach, NULL, NULL); 160 161 static struct audio_device cs4281_device = { 162 "CS4281", 163 "", 164 "cs4281" 165 }; 166 167 168 static int 169 cs4281_match(struct device *parent, struct cfdata *match, void *aux) 170 { 171 struct pci_attach_args *pa; 172 173 pa = (struct pci_attach_args *)aux; 174 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 175 return 0; 176 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 177 return 1; 178 return 0; 179 } 180 181 static void 182 cs4281_attach(struct device *parent, struct device *self, void *aux) 183 { 184 struct cs428x_softc *sc; 185 struct pci_attach_args *pa; 186 pci_chipset_tag_t pc; 187 char const *intrstr; 188 pci_intr_handle_t ih; 189 pcireg_t reg; 190 char devinfo[256]; 191 int error; 192 193 sc = (struct cs428x_softc *)self; 194 pa = (struct pci_attach_args *)aux; 195 pc = pa->pa_pc; 196 aprint_naive(": Audio controller\n"); 197 198 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 199 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 200 PCI_REVISION(pa->pa_class)); 201 202 /* Map I/O register */ 203 if (pci_mapreg_map(pa, PCI_BA0, 204 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 205 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 206 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 207 return; 208 } 209 if (pci_mapreg_map(pa, PCI_BA1, 210 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 211 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 212 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 213 return; 214 } 215 216 sc->sc_dmatag = pa->pa_dmat; 217 218 /* power up chip */ 219 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 220 pci_activate_null)) && error != EOPNOTSUPP) { 221 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 222 error); 223 return; 224 } 225 226 /* Enable the device (set bus master flag) */ 227 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 228 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 229 reg | PCI_COMMAND_MASTER_ENABLE); 230 231 #if 0 232 /* LATENCY_TIMER setting */ 233 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 234 if (PCI_LATTIMER(temp1) < 32) { 235 temp1 &= 0xffff00ff; 236 temp1 |= 0x00002000; 237 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 238 } 239 #endif 240 241 /* Map and establish the interrupt. */ 242 if (pci_intr_map(pa, &ih)) { 243 aprint_error("%s: couldn't map interrupt\n", 244 sc->sc_dev.dv_xname); 245 return; 246 } 247 intrstr = pci_intr_string(pc, ih); 248 249 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 250 if (sc->sc_ih == NULL) { 251 aprint_error("%s: couldn't establish interrupt", 252 sc->sc_dev.dv_xname); 253 if (intrstr != NULL) 254 aprint_normal(" at %s", intrstr); 255 aprint_normal("\n"); 256 return; 257 } 258 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 259 260 /* 261 * Sound System start-up 262 */ 263 if (cs4281_init(sc, 1) != 0) 264 return; 265 266 sc->type = TYPE_CS4281; 267 sc->halt_input = cs4281_halt_input; 268 sc->halt_output = cs4281_halt_output; 269 270 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 271 sc->dma_align = 0x10; 272 sc->hw_blocksize = sc->dma_size / 2; 273 274 /* AC 97 attachment */ 275 sc->host_if.arg = sc; 276 sc->host_if.attach = cs428x_attach_codec; 277 sc->host_if.read = cs428x_read_codec; 278 sc->host_if.write = cs428x_write_codec; 279 sc->host_if.reset = cs4281_reset_codec; 280 if (ac97_attach(&sc->host_if, self) != 0) { 281 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 282 return; 283 } 284 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 285 286 #if NMIDI > 0 && 0 287 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 288 #endif 289 290 sc->sc_suspend = PWR_RESUME; 291 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 292 } 293 294 static int 295 cs4281_intr(void *p) 296 { 297 struct cs428x_softc *sc; 298 uint32_t intr, hdsr0, hdsr1; 299 char *empty_dma; 300 int handled; 301 302 sc = p; 303 handled = 0; 304 hdsr0 = 0; 305 hdsr1 = 0; 306 307 /* grab interrupt register */ 308 intr = BA0READ4(sc, CS4281_HISR); 309 310 DPRINTF(("cs4281_intr:")); 311 /* not for me */ 312 if ((intr & HISR_INTENA) == 0) { 313 /* clear the interrupt register */ 314 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 315 return 0; 316 } 317 318 if (intr & HISR_DMA0) 319 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 320 if (intr & HISR_DMA1) 321 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 322 /* clear the interrupt register */ 323 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 324 325 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 326 intr, hdsr0, hdsr1)); 327 328 /* Playback Interrupt */ 329 if (intr & HISR_DMA0) { 330 handled = 1; 331 if (sc->sc_prun) { 332 DPRINTF((" PB DMA 0x%x(%d)", 333 (int)BA0READ4(sc, CS4281_DCA0), 334 (int)BA0READ4(sc, CS4281_DCC0))); 335 if ((sc->sc_pi%sc->sc_pcount) == 0) 336 sc->sc_pintr(sc->sc_parg); 337 /* copy buffer */ 338 ++sc->sc_pi; 339 empty_dma = sc->sc_pdma->addr; 340 if (sc->sc_pi&1) 341 empty_dma += sc->hw_blocksize; 342 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 343 sc->sc_pn += sc->hw_blocksize; 344 if (sc->sc_pn >= sc->sc_pe) 345 sc->sc_pn = sc->sc_ps; 346 } else { 347 printf("%s: unexpected play intr\n", 348 sc->sc_dev.dv_xname); 349 } 350 } 351 if (intr & HISR_DMA1) { 352 handled = 1; 353 if (sc->sc_rrun) { 354 /* copy from DMA */ 355 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 356 (int)BA0READ4(sc, CS4281_DCC1))); 357 ++sc->sc_ri; 358 empty_dma = sc->sc_rdma->addr; 359 if ((sc->sc_ri & 1) == 0) 360 empty_dma += sc->hw_blocksize; 361 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 362 sc->sc_rn += sc->hw_blocksize; 363 if (sc->sc_rn >= sc->sc_re) 364 sc->sc_rn = sc->sc_rs; 365 if ((sc->sc_ri % sc->sc_rcount) == 0) 366 sc->sc_rintr(sc->sc_rarg); 367 } else { 368 printf("%s: unexpected record intr\n", 369 sc->sc_dev.dv_xname); 370 } 371 } 372 DPRINTF(("\n")); 373 374 return handled; 375 } 376 377 static int 378 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 379 { 380 381 switch (fp->index) { 382 case 0: 383 strcpy(fp->name, AudioEulinear); 384 fp->encoding = AUDIO_ENCODING_ULINEAR; 385 fp->precision = 8; 386 fp->flags = 0; 387 break; 388 case 1: 389 strcpy(fp->name, AudioEmulaw); 390 fp->encoding = AUDIO_ENCODING_ULAW; 391 fp->precision = 8; 392 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 393 break; 394 case 2: 395 strcpy(fp->name, AudioEalaw); 396 fp->encoding = AUDIO_ENCODING_ALAW; 397 fp->precision = 8; 398 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 399 break; 400 case 3: 401 strcpy(fp->name, AudioEslinear); 402 fp->encoding = AUDIO_ENCODING_SLINEAR; 403 fp->precision = 8; 404 fp->flags = 0; 405 break; 406 case 4: 407 strcpy(fp->name, AudioEslinear_le); 408 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 409 fp->precision = 16; 410 fp->flags = 0; 411 break; 412 case 5: 413 strcpy(fp->name, AudioEulinear_le); 414 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 415 fp->precision = 16; 416 fp->flags = 0; 417 break; 418 case 6: 419 strcpy(fp->name, AudioEslinear_be); 420 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 421 fp->precision = 16; 422 fp->flags = 0; 423 break; 424 case 7: 425 strcpy(fp->name, AudioEulinear_be); 426 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 427 fp->precision = 16; 428 fp->flags = 0; 429 break; 430 default: 431 return EINVAL; 432 } 433 return 0; 434 } 435 436 static int 437 cs4281_set_params(void *addr, int setmode, int usemode, 438 audio_params_t *play, audio_params_t *rec, 439 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 440 { 441 audio_params_t hw; 442 struct cs428x_softc *sc; 443 audio_params_t *p; 444 stream_filter_list_t *fil; 445 int mode; 446 447 sc = addr; 448 for (mode = AUMODE_RECORD; mode != -1; 449 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 450 if ((setmode & mode) == 0) 451 continue; 452 453 p = mode == AUMODE_PLAY ? play : rec; 454 455 if (p == play) { 456 DPRINTFN(5, 457 ("play: sample=%u precision=%u channels=%u\n", 458 p->sample_rate, p->precision, p->channels)); 459 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 460 (p->precision != 8 && p->precision != 16) || 461 (p->channels != 1 && p->channels != 2)) { 462 return EINVAL; 463 } 464 } else { 465 DPRINTFN(5, 466 ("rec: sample=%u precision=%u channels=%u\n", 467 p->sample_rate, p->precision, p->channels)); 468 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 469 (p->precision != 8 && p->precision != 16) || 470 (p->channels != 1 && p->channels != 2)) { 471 return EINVAL; 472 } 473 } 474 hw = *p; 475 fil = mode == AUMODE_PLAY ? pfil : rfil; 476 477 switch (p->encoding) { 478 case AUDIO_ENCODING_SLINEAR_BE: 479 break; 480 case AUDIO_ENCODING_SLINEAR_LE: 481 break; 482 case AUDIO_ENCODING_ULINEAR_BE: 483 break; 484 case AUDIO_ENCODING_ULINEAR_LE: 485 break; 486 case AUDIO_ENCODING_ULAW: 487 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 488 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 489 : linear8_to_mulaw, &hw); 490 break; 491 case AUDIO_ENCODING_ALAW: 492 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 493 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 494 : linear8_to_alaw, &hw); 495 break; 496 default: 497 return EINVAL; 498 } 499 } 500 501 /* set sample rate */ 502 cs4281_set_dac_rate(sc, play->sample_rate); 503 cs4281_set_adc_rate(sc, rec->sample_rate); 504 return 0; 505 } 506 507 static int 508 cs4281_halt_output(void *addr) 509 { 510 struct cs428x_softc *sc; 511 512 sc = addr; 513 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 514 sc->sc_prun = 0; 515 return 0; 516 } 517 518 static int 519 cs4281_halt_input(void *addr) 520 { 521 struct cs428x_softc *sc; 522 523 sc = addr; 524 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 525 sc->sc_rrun = 0; 526 return 0; 527 } 528 529 static int 530 cs4281_getdev(void *addr, struct audio_device *retp) 531 { 532 533 *retp = cs4281_device; 534 return 0; 535 } 536 537 static int 538 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 539 void (*intr)(void *), void *arg, 540 const audio_params_t *param) 541 { 542 struct cs428x_softc *sc; 543 uint32_t fmt; 544 struct cs428x_dma *p; 545 int dma_count; 546 547 sc = addr; 548 fmt = 0; 549 #ifdef DIAGNOSTIC 550 if (sc->sc_prun) 551 printf("cs4281_trigger_output: already running\n"); 552 #endif 553 sc->sc_prun = 1; 554 555 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 556 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 557 sc->sc_pintr = intr; 558 sc->sc_parg = arg; 559 560 /* stop playback DMA */ 561 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 562 563 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 564 param->precision, param->channels, param->encoding)); 565 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 566 continue; 567 if (p == NULL) { 568 printf("cs4281_trigger_output: bad addr %p\n", start); 569 return EINVAL; 570 } 571 572 sc->sc_pcount = blksize / sc->hw_blocksize; 573 sc->sc_ps = (char *)start; 574 sc->sc_pe = (char *)end; 575 sc->sc_pdma = p; 576 sc->sc_pbuf = KERNADDR(p); 577 sc->sc_pi = 0; 578 sc->sc_pn = sc->sc_ps; 579 if (blksize >= sc->dma_size) { 580 sc->sc_pn = sc->sc_ps + sc->dma_size; 581 memcpy(sc->sc_pbuf, start, sc->dma_size); 582 ++sc->sc_pi; 583 } else { 584 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 585 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 586 } 587 588 dma_count = sc->dma_size; 589 if (param->precision != 8) 590 dma_count /= 2; /* 16 bit */ 591 if (param->channels > 1) 592 dma_count /= 2; /* Stereo */ 593 594 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 595 (int)DMAADDR(p), dma_count)); 596 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 597 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 598 599 /* set playback format */ 600 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 601 if (param->precision == 8) 602 fmt |= DMRn_SIZE8; 603 if (param->channels == 1) 604 fmt |= DMRn_MONO; 605 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 606 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 607 fmt |= DMRn_BEND; 608 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 609 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 610 fmt |= DMRn_USIGN; 611 BA0WRITE4(sc, CS4281_DMR0, fmt); 612 613 /* set sample rate */ 614 sc->sc_prate = param->sample_rate; 615 cs4281_set_dac_rate(sc, param->sample_rate); 616 617 /* start DMA */ 618 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 619 /* Enable interrupts */ 620 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 621 622 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 623 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 624 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 625 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 626 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 627 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 628 BA0READ4(sc, CS4281_DACSR))); 629 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 630 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 631 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 632 633 return 0; 634 } 635 636 static int 637 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 638 void (*intr)(void *), void *arg, 639 const audio_params_t *param) 640 { 641 struct cs428x_softc *sc; 642 struct cs428x_dma *p; 643 uint32_t fmt; 644 int dma_count; 645 646 sc = addr; 647 fmt = 0; 648 #ifdef DIAGNOSTIC 649 if (sc->sc_rrun) 650 printf("cs4281_trigger_input: already running\n"); 651 #endif 652 sc->sc_rrun = 1; 653 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 654 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 655 sc->sc_rintr = intr; 656 sc->sc_rarg = arg; 657 658 /* stop recording DMA */ 659 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 660 661 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 662 continue; 663 if (!p) { 664 printf("cs4281_trigger_input: bad addr %p\n", start); 665 return EINVAL; 666 } 667 668 sc->sc_rcount = blksize / sc->hw_blocksize; 669 sc->sc_rs = (char *)start; 670 sc->sc_re = (char *)end; 671 sc->sc_rdma = p; 672 sc->sc_rbuf = KERNADDR(p); 673 sc->sc_ri = 0; 674 sc->sc_rn = sc->sc_rs; 675 676 dma_count = sc->dma_size; 677 if (param->precision != 8) 678 dma_count /= 2; 679 if (param->channels > 1) 680 dma_count /= 2; 681 682 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 683 (int)DMAADDR(p), dma_count)); 684 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 685 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 686 687 /* set recording format */ 688 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 689 if (param->precision == 8) 690 fmt |= DMRn_SIZE8; 691 if (param->channels == 1) 692 fmt |= DMRn_MONO; 693 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 694 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 695 fmt |= DMRn_BEND; 696 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 697 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 698 fmt |= DMRn_USIGN; 699 BA0WRITE4(sc, CS4281_DMR1, fmt); 700 701 /* set sample rate */ 702 sc->sc_rrate = param->sample_rate; 703 cs4281_set_adc_rate(sc, param->sample_rate); 704 705 /* Start DMA */ 706 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 707 /* Enable interrupts */ 708 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 709 710 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 711 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 712 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 713 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 714 715 return 0; 716 } 717 718 /* Power Hook */ 719 static void 720 cs4281_power(int why, void *v) 721 { 722 static uint32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 723 static uint32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 724 struct cs428x_softc *sc; 725 726 sc = (struct cs428x_softc *)v; 727 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 728 switch (why) { 729 case PWR_SUSPEND: 730 case PWR_STANDBY: 731 sc->sc_suspend = why; 732 733 /* save current playback status */ 734 if (sc->sc_prun) { 735 dcr0 = BA0READ4(sc, CS4281_DCR0); 736 dmr0 = BA0READ4(sc, CS4281_DMR0); 737 dbc0 = BA0READ4(sc, CS4281_DBC0); 738 dba0 = BA0READ4(sc, CS4281_DBA0); 739 } 740 741 /* save current capture status */ 742 if (sc->sc_rrun) { 743 dcr1 = BA0READ4(sc, CS4281_DCR1); 744 dmr1 = BA0READ4(sc, CS4281_DMR1); 745 dbc1 = BA0READ4(sc, CS4281_DBC1); 746 dba1 = BA0READ4(sc, CS4281_DBA1); 747 } 748 /* Stop DMA */ 749 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 750 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 751 break; 752 case PWR_RESUME: 753 if (sc->sc_suspend == PWR_RESUME) { 754 printf("cs4281_power: odd, resume without suspend.\n"); 755 sc->sc_suspend = why; 756 return; 757 } 758 sc->sc_suspend = why; 759 cs4281_init(sc, 0); 760 cs4281_reset_codec(sc); 761 762 /* restore ac97 registers */ 763 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 764 765 /* restore DMA related status */ 766 if (sc->sc_prun) { 767 cs4281_set_dac_rate(sc, sc->sc_prate); 768 BA0WRITE4(sc, CS4281_DBA0, dba0); 769 BA0WRITE4(sc, CS4281_DBC0, dbc0); 770 BA0WRITE4(sc, CS4281_DMR0, dmr0); 771 BA0WRITE4(sc, CS4281_DCR0, dcr0); 772 } 773 if (sc->sc_rrun) { 774 cs4281_set_adc_rate(sc, sc->sc_rrate); 775 BA0WRITE4(sc, CS4281_DBA1, dba1); 776 BA0WRITE4(sc, CS4281_DBC1, dbc1); 777 BA0WRITE4(sc, CS4281_DMR1, dmr1); 778 BA0WRITE4(sc, CS4281_DCR1, dcr1); 779 } 780 /* enable intterupts */ 781 if (sc->sc_prun || sc->sc_rrun) 782 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 783 break; 784 case PWR_SOFTSUSPEND: 785 case PWR_SOFTSTANDBY: 786 case PWR_SOFTRESUME: 787 break; 788 } 789 } 790 791 /* control AC97 codec */ 792 static int 793 cs4281_reset_codec(void *addr) 794 { 795 struct cs428x_softc *sc; 796 uint16_t data; 797 uint32_t dat32; 798 int n; 799 800 sc = addr; 801 802 DPRINTFN(3, ("cs4281_reset_codec\n")); 803 804 /* Reset codec */ 805 BA0WRITE4(sc, CS428X_ACCTL, 0); 806 delay(50); /* delay 50us */ 807 808 BA0WRITE4(sc, CS4281_SPMC, 0); 809 delay(100); /* delay 100us */ 810 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 811 #if defined(ENABLE_SECONDARY_CODEC) 812 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 813 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 814 #endif 815 delay(50000); /* XXX: delay 50ms */ 816 817 /* Enable ASYNC generation */ 818 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 819 820 /* Wait for codec ready. Linux driver waits 50ms here */ 821 n = 0; 822 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 823 delay(100); 824 if (++n > 1000) { 825 printf("reset_codec: AC97 codec ready timeout\n"); 826 return ETIMEDOUT; 827 } 828 } 829 #if defined(ENABLE_SECONDARY_CODEC) 830 /* secondary codec ready*/ 831 n = 0; 832 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 833 delay(100); 834 if (++n > 1000) 835 return 0; 836 } 837 #endif 838 /* Set the serial timing configuration */ 839 /* XXX: undocumented but the Linux driver do this */ 840 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 841 842 /* Wait for codec ready signal */ 843 n = 0; 844 do { 845 delay(1000); 846 if (++n > 1000) { 847 printf("%s: timeout waiting for codec ready\n", 848 sc->sc_dev.dv_xname); 849 return ETIMEDOUT; 850 } 851 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 852 } while (dat32 == 0); 853 854 /* Enable Valid Frame output on ASDOUT */ 855 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 856 857 /* Wait until codec calibration is finished. Codec register 26h */ 858 n = 0; 859 do { 860 delay(1); 861 if (++n > 1000) { 862 printf("%s: timeout waiting for codec calibration\n", 863 sc->sc_dev.dv_xname); 864 return ETIMEDOUT; 865 } 866 cs428x_read_codec(sc, AC97_REG_POWER, &data); 867 } while ((data & 0x0f) != 0x0f); 868 869 /* Set the serial timing configuration again */ 870 /* XXX: undocumented but the Linux driver do this */ 871 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 872 873 /* Wait until we've sampled input slots 3 & 4 as valid */ 874 n = 0; 875 do { 876 delay(1000); 877 if (++n > 1000) { 878 printf("%s: timeout waiting for sampled input slots as valid\n", 879 sc->sc_dev.dv_xname); 880 return ETIMEDOUT; 881 } 882 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 883 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 884 885 /* Start digital data transfer of audio data to the codec */ 886 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 887 return 0; 888 } 889 890 891 /* Internal functions */ 892 893 /* convert sample rate to register value */ 894 static uint8_t 895 cs4281_sr2regval(int rate) 896 { 897 uint8_t retval; 898 899 /* We don't have to change here. but anyway ... */ 900 if (rate > 48000) 901 rate = 48000; 902 if (rate < 6023) 903 rate = 6023; 904 905 switch (rate) { 906 case 8000: 907 retval = 5; 908 break; 909 case 11025: 910 retval = 4; 911 break; 912 case 16000: 913 retval = 3; 914 break; 915 case 22050: 916 retval = 2; 917 break; 918 case 44100: 919 retval = 1; 920 break; 921 case 48000: 922 retval = 0; 923 break; 924 default: 925 retval = 1536000/rate; /* == 24576000/(rate*16) */ 926 } 927 return retval; 928 } 929 930 static void 931 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 932 { 933 934 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 935 } 936 937 static void 938 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 939 { 940 941 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 942 } 943 944 static int 945 cs4281_init(struct cs428x_softc *sc, int init) 946 { 947 int n; 948 uint16_t data; 949 uint32_t dat32; 950 951 /* set "Configuration Write Protect" register to 952 * 0x4281 to allow to write */ 953 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 954 955 /* 956 * Unset "Full Power-Down bit of Extended PCI Power Management 957 * Control" register to release the reset state. 958 */ 959 dat32 = BA0READ4(sc, CS4281_EPPMC); 960 if (dat32 & EPPMC_FPDN) { 961 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 962 } 963 964 /* Start PLL out in known state */ 965 BA0WRITE4(sc, CS4281_CLKCR1, 0); 966 /* Start serial ports out in known state */ 967 BA0WRITE4(sc, CS4281_SERMC, 0); 968 969 /* Reset codec */ 970 BA0WRITE4(sc, CS428X_ACCTL, 0); 971 delay(50); /* delay 50us */ 972 973 BA0WRITE4(sc, CS4281_SPMC, 0); 974 delay(100); /* delay 100us */ 975 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 976 #if defined(ENABLE_SECONDARY_CODEC) 977 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 978 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 979 #endif 980 delay(50000); /* XXX: delay 50ms */ 981 982 /* Turn on Sound System clocks based on ABITCLK */ 983 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 984 delay(50000); /* XXX: delay 50ms */ 985 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 986 987 /* Set enables for sections that are needed in the SSPM registers */ 988 BA0WRITE4(sc, CS4281_SSPM, 989 SSPM_MIXEN | /* Mixer */ 990 SSPM_CSRCEN | /* Capture SRC */ 991 SSPM_PSRCEN | /* Playback SRC */ 992 SSPM_JSEN | /* Joystick */ 993 SSPM_ACLEN | /* AC LINK */ 994 SSPM_FMEN /* FM */ 995 ); 996 997 /* Wait for clock stabilization */ 998 n = 0; 999 #if 1 1000 /* what document says */ 1001 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1002 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1003 delay(100); 1004 if (++n > 1000) { 1005 printf("%s: timeout waiting for clock stabilization\n", 1006 sc->sc_dev.dv_xname); 1007 return -1; 1008 } 1009 } 1010 #else 1011 /* Cirrus driver for Linux does */ 1012 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1013 delay(1000); 1014 if (++n > 1000) { 1015 printf("%s: timeout waiting for clock stabilization\n", 1016 sc->sc_dev.dv_xname); 1017 return -1; 1018 } 1019 } 1020 #endif 1021 1022 /* Enable ASYNC generation */ 1023 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1024 1025 /* Wait for codec ready. Linux driver waits 50ms here */ 1026 n = 0; 1027 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1028 delay(100); 1029 if (++n > 1000) { 1030 printf("%s: timeout waiting for codec ready\n", 1031 sc->sc_dev.dv_xname); 1032 return -1; 1033 } 1034 } 1035 1036 #if defined(ENABLE_SECONDARY_CODEC) 1037 /* secondary codec ready*/ 1038 n = 0; 1039 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1040 delay(100); 1041 if (++n > 1000) { 1042 printf("%s: timeout waiting for secondary codec ready\n", 1043 sc->sc_dev.dv_xname); 1044 return -1; 1045 } 1046 } 1047 #endif 1048 1049 /* Set the serial timing configuration */ 1050 /* XXX: undocumented but the Linux driver do this */ 1051 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1052 1053 /* Wait for codec ready signal */ 1054 n = 0; 1055 do { 1056 delay(1000); 1057 if (++n > 1000) { 1058 printf("%s: timeout waiting for codec ready\n", 1059 sc->sc_dev.dv_xname); 1060 return -1; 1061 } 1062 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1063 } while (dat32 == 0); 1064 1065 /* Enable Valid Frame output on ASDOUT */ 1066 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1067 1068 /* Wait until codec calibration is finished. codec register 26h */ 1069 n = 0; 1070 do { 1071 delay(1); 1072 if (++n > 1000) { 1073 printf("%s: timeout waiting for codec calibration\n", 1074 sc->sc_dev.dv_xname); 1075 return -1; 1076 } 1077 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1078 } while ((data & 0x0f) != 0x0f); 1079 1080 /* Set the serial timing configuration again */ 1081 /* XXX: undocumented but the Linux driver do this */ 1082 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1083 1084 /* Wait until we've sampled input slots 3 & 4 as valid */ 1085 n = 0; 1086 do { 1087 delay(1000); 1088 if (++n > 1000) { 1089 printf("%s: timeout waiting for sampled input slots as valid\n", 1090 sc->sc_dev.dv_xname); 1091 return -1; 1092 } 1093 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1094 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1095 1096 /* Start digital data transfer of audio data to the codec */ 1097 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1098 1099 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1100 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1101 1102 /* Power on the DAC */ 1103 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1104 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1105 1106 /* Wait until we sample a DAC ready state. 1107 * Not documented, but Linux driver does. 1108 */ 1109 for (n = 0; n < 32; ++n) { 1110 delay(1000); 1111 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1112 if (data & 0x02) 1113 break; 1114 } 1115 1116 /* Power on the ADC */ 1117 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1118 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1119 1120 /* Wait until we sample ADC ready state. 1121 * Not documented, but Linux driver does. 1122 */ 1123 for (n = 0; n < 32; ++n) { 1124 delay(1000); 1125 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1126 if (data & 0x01) 1127 break; 1128 } 1129 1130 #if 0 1131 /* Initialize AC-Link features */ 1132 /* variable sample-rate support */ 1133 mem = BA0READ4(sc, CS4281_SERMC); 1134 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1135 BA0WRITE4(sc, CS4281_SERMC, mem); 1136 /* XXX: more... */ 1137 1138 /* Initialize SSCR register features */ 1139 /* XXX: hardware volume setting */ 1140 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1141 #endif 1142 1143 /* disable Sound Blaster Pro emulation */ 1144 /* XXX: 1145 * Cannot set since the documents does not describe which bit is 1146 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1147 * we can ignore it.*/ 1148 #if 0 1149 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1150 #endif 1151 1152 /* map AC97 PCM playback to DMA Channel 0 */ 1153 /* Reset FEN bit to setup first */ 1154 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1155 /* 1156 *| RS[4:0]/| | 1157 *| LS[4:0] | AC97 | Slot Function 1158 *|---------+--------+-------------------- 1159 *| 0 | 3 | Left PCM Playback 1160 *| 1 | 4 | Right PCM Playback 1161 *| 2 | 5 | Phone Line 1 DAC 1162 *| 3 | 6 | Center PCM Playback 1163 *.... 1164 * quoted from Table 29(p109) 1165 */ 1166 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1167 0x00 << 16 | /* LS[4:0] = 0 see above */ 1168 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1169 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1170 BA0WRITE4(sc, CS4281_FCR0, dat32); 1171 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1172 1173 /* map AC97 PCM record to DMA Channel 1 */ 1174 /* Reset FEN bit to setup first */ 1175 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1176 /* 1177 *| RS[4:0]/| 1178 *| LS[4:0] | AC97 | Slot Function 1179 *|---------+------+------------------- 1180 *| 10 | 3 | Left PCM Record 1181 *| 11 | 4 | Right PCM Record 1182 *| 12 | 5 | Phone Line 1 ADC 1183 *| 13 | 6 | Mic ADC 1184 *.... 1185 * quoted from Table 30(p109) 1186 */ 1187 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1188 0x0a << 16 | /* LS[4:0] = 10 See above */ 1189 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1190 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1191 1192 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1193 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1194 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1195 1196 #if 0 1197 /* Disable DMA Channel 2, 3 */ 1198 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1199 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1200 #endif 1201 1202 /* Set the SRC Slot Assignment accordingly */ 1203 /*| PLSS[4:0]/ 1204 *| PRSS[4:0] | AC97 | Slot Function 1205 *|-----------+------+---------------- 1206 *| 0 | 3 | Left PCM Playback 1207 *| 1 | 4 | Right PCM Playback 1208 *| 2 | 5 | phone line 1 DAC 1209 *| 3 | 6 | Center PCM Playback 1210 *| 4 | 7 | Left Surround PCM Playback 1211 *| 5 | 8 | Right Surround PCM Playback 1212 *...... 1213 * 1214 *| CLSS[4:0]/ 1215 *| CRSS[4:0] | AC97 | Codec |Slot Function 1216 *|-----------+------+-------+----------------- 1217 *| 10 | 3 |Primary| Left PCM Record 1218 *| 11 | 4 |Primary| Right PCM Record 1219 *| 12 | 5 |Primary| Phone Line 1 ADC 1220 *| 13 | 6 |Primary| Mic ADC 1221 *|..... 1222 *| 20 | 3 | Sec. | Left PCM Record 1223 *| 21 | 4 | Sec. | Right PCM Record 1224 *| 22 | 5 | Sec. | Phone Line 1 ADC 1225 *| 23 | 6 | Sec. | Mic ADC 1226 */ 1227 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1228 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1229 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1230 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1231 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1232 1233 /* Set interrupt to occurred at Half and Full terminal 1234 * count interrupt enable for DMA channel 0 and 1. 1235 * To keep DMA stop, set MSK. 1236 */ 1237 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1238 BA0WRITE4(sc, CS4281_DCR0, dat32); 1239 BA0WRITE4(sc, CS4281_DCR1, dat32); 1240 1241 /* Set Auto-Initialize Contorl enable */ 1242 BA0WRITE4(sc, CS4281_DMR0, 1243 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1244 BA0WRITE4(sc, CS4281_DMR1, 1245 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1246 1247 /* Clear DMA Mask in HIMR */ 1248 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1249 BA0WRITE4(sc, CS4281_HIMR, 1250 BA0READ4(sc, CS4281_HIMR) & dat32); 1251 1252 /* set current status */ 1253 if (init != 0) { 1254 sc->sc_prun = 0; 1255 sc->sc_rrun = 0; 1256 } 1257 1258 /* setup playback volume */ 1259 BA0WRITE4(sc, CS4281_PPRVC, 7); 1260 BA0WRITE4(sc, CS4281_PPLVC, 7); 1261 1262 return 0; 1263 } 1264
Indexes created Wed Oct 01 07:09:59 GMT 2025