cs4281.c revision 1.3
1 /* $NetBSD: cs4281.c,v 1.3 2001/02/07 14:41:11 tacha Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/malloc.h> 49 #include <sys/fcntl.h> 50 #include <sys/device.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 54 #include <dev/pci/pcidevs.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/cs4281reg.h> 57 #include <dev/pci/cs428xreg.h> 58 59 #include <sys/audioio.h> 60 #include <dev/audio_if.h> 61 #include <dev/midi_if.h> 62 #include <dev/mulaw.h> 63 #include <dev/auconv.h> 64 65 #include <dev/ic/ac97reg.h> 66 #include <dev/ic/ac97var.h> 67 68 #include <dev/pci/cs428x.h> 69 70 #include <machine/bus.h> 71 72 #if defined(ENABLE_SECONDARY_CODEC) 73 #define MAX_CHANNELS (4) 74 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 75 #else 76 #define MAX_CHANNELS (2) 77 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 78 #endif 79 80 /* IF functions for audio driver */ 81 int cs4281_match(struct device *, struct cfdata *, void *); 82 void cs4281_attach(struct device *, struct device *, void *); 83 int cs4281_intr(void *); 84 int cs4281_query_encoding(void *, struct audio_encoding *); 85 int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 86 int cs4281_halt_output(void *); 87 int cs4281_halt_input(void *); 88 int cs4281_getdev(void *, struct audio_device *); 89 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 90 void *, struct audio_params *); 91 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 92 void *, struct audio_params *); 93 94 void cs4281_reset_codec(void *); 95 96 /* Internal functions */ 97 u_int8_t cs4281_sr2regval(int); 98 void cs4281_set_dac_rate(struct cs428x_softc *, int ); 99 void cs4281_set_adc_rate(struct cs428x_softc *, int ); 100 int cs4281_init(struct cs428x_softc *); 101 102 /* Power Management */ 103 void cs4281_power(int, void *); 104 105 struct audio_hw_if cs4281_hw_if = { 106 cs428x_open, 107 cs428x_close, 108 NULL, 109 cs4281_query_encoding, 110 cs4281_set_params, 111 cs428x_round_blocksize, 112 NULL, 113 NULL, 114 NULL, 115 NULL, 116 NULL, 117 cs4281_halt_output, 118 cs4281_halt_input, 119 NULL, 120 cs4281_getdev, 121 NULL, 122 cs428x_mixer_set_port, 123 cs428x_mixer_get_port, 124 cs428x_query_devinfo, 125 cs428x_malloc, 126 cs428x_free, 127 cs428x_round_buffersize, 128 cs428x_mappage, 129 cs428x_get_props, 130 cs4281_trigger_output, 131 cs4281_trigger_input, 132 }; 133 134 #if NMIDI > 0 && 0 135 /* Midi Interface */ 136 void cs4281_midi_close(void*); 137 void cs4281_midi_getinfo(void *, struct midi_info *); 138 int cs4281_midi_open(void *, int, void (*)(void *, int), 139 void (*)(void *), void *); 140 int cs4281_midi_output(void *, int); 141 142 struct midi_hw_if cs4281_midi_hw_if = { 143 cs4281_midi_open, 144 cs4281_midi_close, 145 cs4281_midi_output, 146 cs4281_midi_getinfo, 147 0, 148 }; 149 #endif 150 151 struct cfattach clct_ca = { 152 sizeof(struct cs428x_softc), cs4281_match, cs4281_attach 153 }; 154 155 struct audio_device cs4281_device = { 156 "CS4281", 157 "", 158 "cs4281" 159 }; 160 161 162 int 163 cs4281_match(parent, match, aux) 164 struct device *parent; 165 struct cfdata *match; 166 void *aux; 167 { 168 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 169 170 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 171 return 0; 172 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 173 return 1; 174 return 0; 175 } 176 177 void 178 cs4281_attach(parent, self, aux) 179 struct device *parent; 180 struct device *self; 181 void *aux; 182 { 183 struct cs428x_softc *sc = (struct cs428x_softc *)self; 184 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 185 pci_chipset_tag_t pc = pa->pa_pc; 186 char const *intrstr; 187 pci_intr_handle_t ih; 188 pcireg_t reg; 189 char devinfo[256]; 190 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 191 192 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 193 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 194 195 /* Map I/O register */ 196 if (pci_mapreg_map(pa, PCI_BA0, 197 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 198 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 199 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 200 return; 201 } 202 if (pci_mapreg_map(pa, PCI_BA1, 203 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 204 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 205 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 206 return; 207 } 208 209 sc->sc_dmatag = pa->pa_dmat; 210 211 /* 212 * Set Power State D0. 213 * Without do this, 0xffffffff is read from all registers after 214 * using Windows. 215 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 216 */ 217 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 218 &pci_pwrmgmt_cap_reg, 0)) { 219 220 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 221 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 222 pci_pwrmgmt_csr_reg); 223 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 224 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 225 (reg & ~PCI_PMCSR_STATE_MASK) | 226 PCI_PMCSR_STATE_D0); 227 } 228 } 229 230 /* Enable the device (set bus master flag) */ 231 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 233 reg | PCI_COMMAND_MASTER_ENABLE); 234 235 #if 0 236 /* LATENCY_TIMER setting */ 237 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 238 if ( PCI_LATTIMER(temp1) < 32 ) { 239 temp1 &= 0xffff00ff; 240 temp1 |= 0x00002000; 241 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 242 } 243 #endif 244 245 /* Map and establish the interrupt. */ 246 if (pci_intr_map(pa, &ih)) { 247 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 248 return; 249 } 250 intrstr = pci_intr_string(pc, ih); 251 252 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 253 if (sc->sc_ih == NULL) { 254 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 255 if (intrstr != NULL) 256 printf(" at %s", intrstr); 257 printf("\n"); 258 return; 259 } 260 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 261 262 /* 263 * Sound System start-up 264 */ 265 if (cs4281_init(sc) != 0) 266 return; 267 268 sc->type = TYPE_CS4281; 269 sc->halt_input = cs4281_halt_input; 270 sc->halt_output = cs4281_halt_output; 271 272 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 273 sc->dma_align = 0x10; 274 sc->hw_blocksize = sc->dma_size / 2; 275 276 /* AC 97 attachment */ 277 sc->host_if.arg = sc; 278 sc->host_if.attach = cs428x_attach_codec; 279 sc->host_if.read = cs428x_read_codec; 280 sc->host_if.write = cs428x_write_codec; 281 sc->host_if.reset = cs4281_reset_codec; 282 if (ac97_attach(&sc->host_if) != 0) { 283 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 284 return; 285 } 286 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 287 288 #if NMIDI > 0 && 0 289 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 290 #endif 291 292 sc->sc_suspend = PWR_RESUME; 293 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 294 } 295 296 int 297 cs4281_intr(p) 298 void *p; 299 { 300 struct cs428x_softc *sc = p; 301 u_int32_t intr, hdsr0, hdsr1; 302 char *empty_dma; 303 int handled = 0; 304 305 hdsr0 = 0; 306 hdsr1 = 0; 307 308 /* grab interrupt register */ 309 intr = BA0READ4(sc, CS4281_HISR); 310 311 DPRINTF(("cs4281_intr:")); 312 /* not for me */ 313 if ((intr & HISR_INTENA) == 0) { 314 /* clear the interrupt register */ 315 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 316 return 0; 317 } 318 319 if (intr & HISR_DMA0) 320 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 321 if (intr & HISR_DMA1) 322 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 323 /* clear the interrupt register */ 324 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 325 326 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 327 intr, hdsr0, hdsr1)); 328 329 /* Playback Interrupt */ 330 if (intr & HISR_DMA0) { 331 handled = 1; 332 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 333 (int)BA0READ4(sc, CS4281_DCC0))); 334 if (sc->sc_pintr) { 335 if ((sc->sc_pi%sc->sc_pcount) == 0) 336 sc->sc_pintr(sc->sc_parg); 337 } else { 338 printf("unexpected play intr\n"); 339 } 340 /* copy buffer */ 341 ++sc->sc_pi; 342 empty_dma = sc->sc_pdma->addr; 343 if (sc->sc_pi&1) 344 empty_dma += sc->hw_blocksize; 345 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 346 sc->sc_pn += sc->hw_blocksize; 347 if (sc->sc_pn >= sc->sc_pe) 348 sc->sc_pn = sc->sc_ps; 349 } 350 if (intr & HISR_DMA1) { 351 handled = 1; 352 /* copy from dma */ 353 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 354 (int)BA0READ4(sc, CS4281_DCC1))); 355 ++sc->sc_ri; 356 empty_dma = sc->sc_rdma->addr; 357 if ((sc->sc_ri & 1) == 0) 358 empty_dma += sc->hw_blocksize; 359 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 360 if (sc->sc_rn >= sc->sc_re) 361 sc->sc_rn = sc->sc_rs; 362 if (sc->sc_rintr) { 363 if ((sc->sc_ri % sc->sc_rcount) == 0) 364 sc->sc_rintr(sc->sc_rarg); 365 } else { 366 printf("unexpected record intr\n"); 367 } 368 } 369 DPRINTF(("\n")); 370 371 return handled; 372 } 373 374 int 375 cs4281_query_encoding(addr, fp) 376 void *addr; 377 struct audio_encoding *fp; 378 { 379 switch (fp->index) { 380 case 0: 381 strcpy(fp->name, AudioEulinear); 382 fp->encoding = AUDIO_ENCODING_ULINEAR; 383 fp->precision = 8; 384 fp->flags = 0; 385 break; 386 case 1: 387 strcpy(fp->name, AudioEmulaw); 388 fp->encoding = AUDIO_ENCODING_ULAW; 389 fp->precision = 8; 390 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 391 break; 392 case 2: 393 strcpy(fp->name, AudioEalaw); 394 fp->encoding = AUDIO_ENCODING_ALAW; 395 fp->precision = 8; 396 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 397 break; 398 case 3: 399 strcpy(fp->name, AudioEslinear); 400 fp->encoding = AUDIO_ENCODING_SLINEAR; 401 fp->precision = 8; 402 fp->flags = 0; 403 break; 404 case 4: 405 strcpy(fp->name, AudioEslinear_le); 406 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 407 fp->precision = 16; 408 fp->flags = 0; 409 break; 410 case 5: 411 strcpy(fp->name, AudioEulinear_le); 412 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 413 fp->precision = 16; 414 fp->flags = 0; 415 break; 416 case 6: 417 strcpy(fp->name, AudioEslinear_be); 418 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 419 fp->precision = 16; 420 fp->flags = 0; 421 break; 422 case 7: 423 strcpy(fp->name, AudioEulinear_be); 424 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 425 fp->precision = 16; 426 fp->flags = 0; 427 break; 428 default: 429 return EINVAL; 430 } 431 return 0; 432 } 433 434 int 435 cs4281_set_params(addr, setmode, usemode, play, rec) 436 void *addr; 437 int setmode, usemode; 438 struct audio_params *play, *rec; 439 { 440 struct cs428x_softc *sc = addr; 441 struct audio_params *p; 442 int mode; 443 444 for (mode = AUMODE_RECORD; mode != -1; 445 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 446 if ((setmode & mode) == 0) 447 continue; 448 449 p = mode == AUMODE_PLAY ? play : rec; 450 451 if (p == play) { 452 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 453 p->sample_rate, p->precision, p->channels)); 454 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 455 (p->precision != 8 && p->precision != 16) || 456 (p->channels != 1 && p->channels != 2)) { 457 return (EINVAL); 458 } 459 } else { 460 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 461 p->sample_rate, p->precision, p->channels)); 462 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 463 (p->precision != 8 && p->precision != 16) || 464 (p->channels != 1 && p->channels != 2)) { 465 return (EINVAL); 466 } 467 } 468 p->factor = 1; 469 p->sw_code = 0; 470 471 switch (p->encoding) { 472 case AUDIO_ENCODING_SLINEAR_BE: 473 break; 474 case AUDIO_ENCODING_SLINEAR_LE: 475 break; 476 case AUDIO_ENCODING_ULINEAR_BE: 477 break; 478 case AUDIO_ENCODING_ULINEAR_LE: 479 break; 480 case AUDIO_ENCODING_ULAW: 481 if (mode == AUMODE_PLAY) { 482 p->sw_code = mulaw_to_slinear8; 483 } else { 484 p->sw_code = slinear8_to_mulaw; 485 } 486 break; 487 case AUDIO_ENCODING_ALAW: 488 if (mode == AUMODE_PLAY) { 489 p->sw_code = alaw_to_slinear8; 490 } else { 491 p->sw_code = slinear8_to_alaw; 492 } 493 break; 494 default: 495 return (EINVAL); 496 } 497 } 498 499 /* set sample rate */ 500 cs4281_set_dac_rate(sc, play->sample_rate); 501 cs4281_set_adc_rate(sc, rec->sample_rate); 502 return 0; 503 } 504 505 int 506 cs4281_halt_output(addr) 507 void *addr; 508 { 509 struct cs428x_softc *sc = addr; 510 511 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 512 #ifdef DIAGNOSTIC 513 sc->sc_prun = 0; 514 #endif 515 return 0; 516 } 517 518 int 519 cs4281_halt_input(addr) 520 void *addr; 521 { 522 struct cs428x_softc *sc = addr; 523 524 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 525 #ifdef DIAGNOSTIC 526 sc->sc_rrun = 0; 527 #endif 528 return 0; 529 } 530 531 int 532 cs4281_getdev(addr, retp) 533 void *addr; 534 struct audio_device *retp; 535 { 536 *retp = cs4281_device; 537 return 0; 538 } 539 540 int 541 cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 542 void *addr; 543 void *start, *end; 544 int blksize; 545 void (*intr) __P((void *)); 546 void *arg; 547 struct audio_params *param; 548 { 549 struct cs428x_softc *sc = addr; 550 u_int32_t fmt=0; 551 struct cs428x_dma *p; 552 int dma_count; 553 554 #ifdef DIAGNOSTIC 555 if (sc->sc_prun) 556 printf("cs4281_trigger_output: already running\n"); 557 sc->sc_prun = 1; 558 #endif 559 560 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 561 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 562 sc->sc_pintr = intr; 563 sc->sc_parg = arg; 564 565 /* stop playback DMA */ 566 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 567 568 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 569 param->precision, param->factor, param->channels, 570 param->encoding)); 571 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 572 ; 573 if (p == NULL) { 574 printf("cs4281_trigger_output: bad addr %p\n", start); 575 return (EINVAL); 576 } 577 578 sc->sc_pcount = blksize / sc->hw_blocksize; 579 sc->sc_ps = (char *)start; 580 sc->sc_pe = (char *)end; 581 sc->sc_pdma = p; 582 sc->sc_pbuf = KERNADDR(p); 583 sc->sc_pi = 0; 584 sc->sc_pn = sc->sc_ps; 585 if (blksize >= sc->dma_size) { 586 sc->sc_pn = sc->sc_ps + sc->dma_size; 587 memcpy(sc->sc_pbuf, start, sc->dma_size); 588 ++sc->sc_pi; 589 } else { 590 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 591 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 592 } 593 594 dma_count = sc->dma_size; 595 if (param->precision * param->factor != 8) 596 dma_count /= 2; /* 16 bit */ 597 if (param->channels > 1) 598 dma_count /= 2; /* Stereo */ 599 600 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 601 (int)DMAADDR(p), dma_count)); 602 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 603 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 604 605 /* set playback format */ 606 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 607 if (param->precision * param->factor == 8) 608 fmt |= DMRn_SIZE8; 609 if (param->channels == 1) 610 fmt |= DMRn_MONO; 611 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 612 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 613 fmt |= DMRn_BEND; 614 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 615 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 616 fmt |= DMRn_USIGN; 617 BA0WRITE4(sc, CS4281_DMR0, fmt); 618 619 /* set sample rate */ 620 cs4281_set_dac_rate(sc, param->sample_rate); 621 622 /* start DMA */ 623 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 624 /* Enable interrupts */ 625 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 626 627 #if 1 628 /* XXX 629 * I think these BA0WRITE4 should not be here 630 */ 631 BA0WRITE4(sc, CS4281_PPRVC, 7); 632 BA0WRITE4(sc, CS4281_PPLVC, 7); 633 #endif 634 635 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 636 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 637 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 638 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 639 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 640 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 641 BA0READ4(sc, CS4281_DACSR))); 642 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 643 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 644 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 645 646 return 0; 647 } 648 649 int 650 cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 651 void *addr; 652 void *start, *end; 653 int blksize; 654 void (*intr) __P((void *)); 655 void *arg; 656 struct audio_params *param; 657 { 658 struct cs428x_softc *sc = addr; 659 struct cs428x_dma *p; 660 u_int32_t fmt=0; 661 int dma_count; 662 663 printf("cs4281_trigger_input: not implemented yet\n"); 664 #ifdef DIAGNOSTIC 665 if (sc->sc_rrun) 666 printf("cs4281_trigger_input: already running\n"); 667 sc->sc_rrun = 1; 668 #endif 669 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 670 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 671 sc->sc_rintr = intr; 672 sc->sc_rarg = arg; 673 674 /* stop recording DMA */ 675 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 676 677 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 678 ; 679 if (!p) { 680 printf("cs4281_trigger_input: bad addr %p\n", start); 681 return (EINVAL); 682 } 683 684 sc->sc_rcount = blksize / sc->hw_blocksize; 685 sc->sc_rs = (char *)start; 686 sc->sc_re = (char *)end; 687 sc->sc_rdma = p; 688 sc->sc_rbuf = KERNADDR(p); 689 sc->sc_ri = 0; 690 sc->sc_rn = sc->sc_rs; 691 692 dma_count = sc->dma_size; 693 if (param->precision * param->factor == 8) 694 dma_count /= 2; 695 if (param->channels > 1) 696 dma_count /= 2; 697 698 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 699 (int)DMAADDR(p), dma_count)); 700 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 701 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 702 703 /* set recording format */ 704 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 705 if (param->precision * param->factor == 8) 706 fmt |= DMRn_SIZE8; 707 if (param->channels == 1) 708 fmt |= DMRn_MONO; 709 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 710 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 711 fmt |= DMRn_BEND; 712 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 713 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 714 fmt |= DMRn_USIGN; 715 BA0WRITE4(sc, CS4281_DMR1, fmt); 716 717 /* set sample rate */ 718 cs4281_set_adc_rate(sc, param->sample_rate); 719 720 /* Start DMA */ 721 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 722 /* Enable interrupts */ 723 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 724 725 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 726 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 727 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 728 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 729 730 return 0; 731 } 732 733 /* Power Hook */ 734 void 735 cs4281_power(why, v) 736 int why; 737 void *v; 738 { 739 struct cs428x_softc *sc = (struct cs428x_softc *)v; 740 741 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 742 switch (why) { 743 case PWR_SUSPEND: 744 case PWR_STANDBY: 745 sc->sc_suspend = why; 746 747 cs4281_halt_output(sc); 748 cs4281_halt_input(sc); 749 /* should I powerdown here ? */ 750 cs428x_write_codec(sc, AC97_REG_POWER, CS4281_POWER_DOWN_ALL); 751 break; 752 case PWR_RESUME: 753 if (sc->sc_suspend == PWR_RESUME) { 754 printf("cs4281_power: odd, resume without suspend.\n"); 755 sc->sc_suspend = why; 756 return; 757 } 758 sc->sc_suspend = why; 759 cs4281_init(sc); 760 cs4281_reset_codec(sc); 761 762 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 763 break; 764 case PWR_SOFTSUSPEND: 765 case PWR_SOFTSTANDBY: 766 case PWR_SOFTRESUME: 767 break; 768 } 769 } 770 771 /* control AC97 codec */ 772 void 773 cs4281_reset_codec(void *addr) 774 { 775 struct cs428x_softc *sc; 776 u_int16_t data; 777 u_int32_t dat32; 778 int n; 779 780 sc = addr; 781 782 DPRINTFN(3,("cs4281_reset_codec\n")); 783 784 /* Reset codec */ 785 BA0WRITE4(sc, CS428X_ACCTL, 0); 786 delay(50); /* delay 50us */ 787 788 BA0WRITE4(sc, CS4281_SPMC, 0); 789 delay(100); /* delay 100us */ 790 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 791 #if defined(ENABLE_SECONDARY_CODEC) 792 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 793 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 794 #endif 795 delay(50000); /* XXX: delay 50ms */ 796 797 /* Enable ASYNC generation */ 798 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 799 800 /* Wait for Codec ready. Linux driver wait 50ms here */ 801 n = 0; 802 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 803 delay(100); 804 if (++n > 1000) { 805 printf("reset_codec: AC97 codec ready timeout\n"); 806 return; 807 } 808 } 809 #if defined(ENABLE_SECONDARY_CODEC) 810 /* secondary codec ready*/ 811 n = 0; 812 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 813 delay(100); 814 if (++n > 1000) 815 return; 816 } 817 #endif 818 /* Set the serial timing configuration */ 819 /* XXX: undocumented but the Linux driver do this */ 820 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 821 822 /* Wait for Codec ready signal */ 823 n = 0; 824 do { 825 delay(1000); 826 if (++n > 1000) { 827 printf("%s: Timeout waiting for Codec ready\n", 828 sc->sc_dev.dv_xname); 829 return; 830 } 831 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 832 } while (dat32 == 0); 833 834 /* Enable Valid Frame output on ASDOUT */ 835 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 836 837 /* Wait until Codec Calibration is finished. Codec register 26h */ 838 n = 0; 839 do { 840 delay(1); 841 if (++n > 1000) { 842 printf("%s: Timeout waiting for Codec calibration\n", 843 sc->sc_dev.dv_xname); 844 return ; 845 } 846 cs428x_read_codec(sc, AC97_REG_POWER, &data); 847 } while ((data & 0x0f) != 0x0f); 848 849 /* Set the serial timing configuration again */ 850 /* XXX: undocumented but the Linux driver do this */ 851 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 852 853 /* Wait until we've sampled input slots 3 & 4 as valid */ 854 n = 0; 855 do { 856 delay(1000); 857 if (++n > 1000) { 858 printf("%s: Timeout waiting for sampled input slots as valid\n", 859 sc->sc_dev.dv_xname); 860 return; 861 } 862 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 863 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 864 865 /* Start digital data transfer of audio data to the codec */ 866 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 867 } 868 869 870 /* Internal functions */ 871 872 /* convert sample rate to register value */ 873 u_int8_t 874 cs4281_sr2regval(rate) 875 int rate; 876 { 877 u_int8_t retval; 878 879 /* We don't have to change here. but anyway ... */ 880 if (rate > 48000) 881 rate = 48000; 882 if (rate < 6023) 883 rate = 6023; 884 885 switch (rate) { 886 case 8000: 887 retval = 5; 888 break; 889 case 11025: 890 retval = 4; 891 break; 892 case 16000: 893 retval = 3; 894 break; 895 case 22050: 896 retval = 2; 897 break; 898 case 44100: 899 retval = 1; 900 break; 901 case 48000: 902 retval = 0; 903 break; 904 default: 905 retval = 1536000/rate; /* == 24576000/(rate*16) */ 906 } 907 return retval; 908 } 909 910 void 911 cs4281_set_adc_rate(sc, rate) 912 struct cs428x_softc *sc; 913 int rate; 914 { 915 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 916 } 917 918 void 919 cs4281_set_dac_rate(sc, rate) 920 struct cs428x_softc *sc; 921 int rate; 922 { 923 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 924 } 925 926 int 927 cs4281_init(sc) 928 struct cs428x_softc *sc; 929 { 930 int n; 931 u_int16_t data; 932 u_int32_t dat32; 933 934 /* set "Configuration Write Protect" register to 935 * 0x4281 to allow to write */ 936 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 937 938 /* 939 * Unset "Full Power-Down bit of Extended PCI Power Management 940 * Control" register to release the reset state. 941 */ 942 dat32 = BA0READ4(sc, CS4281_EPPMC); 943 if (dat32 & EPPMC_FPDN) { 944 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 945 } 946 947 /* Start PLL out in known state */ 948 BA0WRITE4(sc, CS4281_CLKCR1, 0); 949 /* Start serial ports out in known state */ 950 BA0WRITE4(sc, CS4281_SERMC, 0); 951 952 /* Reset codec */ 953 BA0WRITE4(sc, CS428X_ACCTL, 0); 954 delay(50); /* delay 50us */ 955 956 BA0WRITE4(sc, CS4281_SPMC, 0); 957 delay(100); /* delay 100us */ 958 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 959 #if defined(ENABLE_SECONDARY_CODEC) 960 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 961 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 962 #endif 963 delay(50000); /* XXX: delay 50ms */ 964 965 /* Turn on Sound System clocks based on ABITCLK */ 966 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 967 delay(50000); /* XXX: delay 50ms */ 968 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 969 970 /* Set enables for sections that are needed in the SSPM registers */ 971 BA0WRITE4(sc, CS4281_SSPM, 972 SSPM_MIXEN | /* Mixer */ 973 SSPM_CSRCEN | /* Capture SRC */ 974 SSPM_PSRCEN | /* Playback SRC */ 975 SSPM_JSEN | /* Joystick */ 976 SSPM_ACLEN | /* AC LINK */ 977 SSPM_FMEN /* FM */ 978 ); 979 980 /* Wait for clock stabilization */ 981 n = 0; 982 #if 1 983 /* what document says */ 984 while ( ( BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 985 != (CLKCR1_DLLRDY | CLKCR1_CLKON )) { 986 delay(100); 987 if ( ++n > 1000 ) 988 return -1; 989 } 990 #else 991 /* Cirrus driver for Linux does */ 992 while ( !(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 993 delay(1000); 994 if ( ++n > 1000 ) 995 return -1; 996 } 997 #endif 998 999 /* Enable ASYNC generation */ 1000 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1001 1002 /* Wait for Codec ready. Linux driver wait 50ms here */ 1003 n = 0; 1004 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1005 delay(100); 1006 if (++n > 1000) 1007 return -1; 1008 } 1009 1010 #if defined(ENABLE_SECONDARY_CODEC) 1011 /* secondary codec ready*/ 1012 n = 0; 1013 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1014 delay(100); 1015 if (++n > 1000) 1016 return -1; 1017 } 1018 #endif 1019 1020 /* Set the serial timing configuration */ 1021 /* XXX: undocumented but the Linux driver do this */ 1022 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1023 1024 /* Wait for Codec ready signal */ 1025 n = 0; 1026 do { 1027 delay(1000); 1028 if (++n > 1000) { 1029 printf("%s: Timeout waiting for Codec ready\n", 1030 sc->sc_dev.dv_xname); 1031 return -1; 1032 } 1033 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1034 } while (dat32 == 0); 1035 1036 /* Enable Valid Frame output on ASDOUT */ 1037 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1038 1039 /* Wait until Codec Calibration is finished. Codec register 26h */ 1040 n = 0; 1041 do { 1042 delay(1); 1043 if (++n > 1000) { 1044 printf("%s: Timeout waiting for Codec calibration\n", 1045 sc->sc_dev.dv_xname); 1046 return -1; 1047 } 1048 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1049 } while ((data & 0x0f) != 0x0f); 1050 1051 /* Set the serial timing configuration again */ 1052 /* XXX: undocumented but the Linux driver do this */ 1053 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1054 1055 /* Wait until we've sampled input slots 3 & 4 as valid */ 1056 n = 0; 1057 do { 1058 delay(1000); 1059 if (++n > 1000) { 1060 printf("%s: Timeout waiting for sampled input slots as valid\n", 1061 sc->sc_dev.dv_xname); 1062 return -1; 1063 } 1064 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1065 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1066 1067 /* Start digital data transfer of audio data to the codec */ 1068 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1069 1070 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1071 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1072 1073 /* Power on the DAC */ 1074 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1075 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1076 1077 /* Wait until we sample a DAC ready state. 1078 * Not documented, but Linux driver does. 1079 */ 1080 for (n = 0; n < 32; ++n) { 1081 delay(1000); 1082 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1083 if (data & 0x02) 1084 break; 1085 } 1086 1087 /* Power on the ADC */ 1088 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1089 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1090 1091 /* Wait until we sample ADC ready state. 1092 * Not documented, but Linux driver does. 1093 */ 1094 for (n = 0; n < 32; ++n) { 1095 delay(1000); 1096 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1097 if (data & 0x01) 1098 break; 1099 } 1100 1101 #if 0 1102 /* Initialize AC-Link features */ 1103 /* variable sample-rate support */ 1104 mem = BA0READ4(sc, CS4281_SERMC); 1105 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1106 BA0WRITE4(sc, CS4281_SERMC, mem); 1107 /* XXX: more... */ 1108 1109 /* Initialize SSCR register features */ 1110 /* XXX: hardware volume setting */ 1111 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1112 #endif 1113 1114 /* disable Sound Blaster Pro emulation */ 1115 /* XXX: 1116 * Cannot set since the documents does not describe which bit is 1117 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1118 * we can ignore it.*/ 1119 #if 0 1120 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1121 #endif 1122 1123 /* map AC97 PCM playback to DMA Channel 0 */ 1124 /* Reset FEN bit to setup first */ 1125 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc,CS4281_FCR0) & ~FCRn_FEN)); 1126 /* 1127 *| RS[4:0]/| | 1128 *| LS[4:0] | AC97 | Slot Function 1129 *|---------+--------+-------------------- 1130 *| 0 | 3 | Left PCM Playback 1131 *| 1 | 4 | Right PCM Playback 1132 *| 2 | 5 | Phone Line 1 DAC 1133 *| 3 | 6 | Center PCM Playback 1134 *.... 1135 * quoted from Table 29(p109) 1136 */ 1137 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1138 0x00 << 16 | /* LS[4:0] = 0 see above */ 1139 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1140 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1141 BA0WRITE4(sc, CS4281_FCR0, dat32); 1142 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1143 1144 /* map AC97 PCM record to DMA Channel 1 */ 1145 /* Reset FEN bit to setup first */ 1146 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc,CS4281_FCR1) & ~FCRn_FEN)); 1147 /* 1148 *| RS[4:0]/| 1149 *| LS[4:0] | AC97 | Slot Function 1150 *|---------+------+------------------- 1151 *| 10 | 3 | Left PCM Record 1152 *| 11 | 4 | Right PCM Record 1153 *| 12 | 5 | Phone Line 1 ADC 1154 *| 13 | 6 | Mic ADC 1155 *.... 1156 * quoted from Table 30(p109) 1157 */ 1158 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1159 0x0a << 16 | /* LS[4:0] = 10 See above */ 1160 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1161 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1162 1163 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1164 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1165 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1166 1167 #if 0 1168 /* Disable DMA Channel 2, 3 */ 1169 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc,CS4281_FCR2) & ~FCRn_FEN)); 1170 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc,CS4281_FCR3) & ~FCRn_FEN)); 1171 #endif 1172 1173 /* Set the SRC Slot Assignment accordingly */ 1174 /*| PLSS[4:0]/ 1175 *| PRSS[4:0] | AC97 | Slot Function 1176 *|-----------+------+---------------- 1177 *| 0 | 3 | Left PCM Playback 1178 *| 1 | 4 | Right PCM Playback 1179 *| 2 | 5 | phone line 1 DAC 1180 *| 3 | 6 | Center PCM Playback 1181 *| 4 | 7 | Left Surround PCM Playback 1182 *| 5 | 8 | Right Surround PCM Playback 1183 *...... 1184 * 1185 *| CLSS[4:0]/ 1186 *| CRSS[4:0] | AC97 | Codec |Slot Function 1187 *|-----------+------+-------+----------------- 1188 *| 10 | 3 |Primary| Left PCM Record 1189 *| 11 | 4 |Primary| Right PCM Record 1190 *| 12 | 5 |Primary| Phone Line 1 ADC 1191 *| 13 | 6 |Primary| Mic ADC 1192 *|..... 1193 *| 20 | 3 | Sec. | Left PCM Record 1194 *| 21 | 4 | Sec. | Right PCM Record 1195 *| 22 | 5 | Sec. | Phone Line 1 ADC 1196 *| 23 | 6 | Sec. | Mic ADC 1197 */ 1198 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1199 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1200 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1201 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1202 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1203 1204 /* Set interrupt to occured at Half and Full terminal 1205 * count interrupt enable for DMA channel 0 and 1. 1206 * To keep DMA stop, set MSK. 1207 */ 1208 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1209 BA0WRITE4(sc, CS4281_DCR0, dat32); 1210 BA0WRITE4(sc, CS4281_DCR1, dat32); 1211 1212 /* Set Auto-Initialize Contorl enable */ 1213 BA0WRITE4(sc, CS4281_DMR0, 1214 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1215 BA0WRITE4(sc, CS4281_DMR1, 1216 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1217 1218 /* Clear DMA Mask in HIMR */ 1219 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1220 BA0WRITE4(sc, CS4281_HIMR, 1221 BA0READ4(sc, CS4281_HIMR) & dat32); 1222 return 0; 1223 } 1224
Indexes created Wed Oct 01 07:09:59 GMT 2025