cs4281.c revision 1.30
1 /* $NetBSD: cs4281.c,v 1.30 2006/08/29 23:54:10 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.30 2006/08/29 23:54:10 christos Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(struct device *, struct cfdata *, void *); 84 static void cs4281_attach(struct device *, struct device *, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static void cs4281_power(int, void *); 110 111 static const struct audio_hw_if cs4281_hw_if = { 112 NULL, /* open */ 113 NULL, /* close */ 114 NULL, 115 cs4281_query_encoding, 116 cs4281_set_params, 117 cs428x_round_blocksize, 118 NULL, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 cs4281_halt_output, 124 cs4281_halt_input, 125 NULL, 126 cs4281_getdev, 127 NULL, 128 cs428x_mixer_set_port, 129 cs428x_mixer_get_port, 130 cs428x_query_devinfo, 131 cs428x_malloc, 132 cs428x_free, 133 cs428x_round_buffersize, 134 cs428x_mappage, 135 cs428x_get_props, 136 cs4281_trigger_output, 137 cs4281_trigger_input, 138 NULL, 139 NULL, 140 }; 141 142 #if NMIDI > 0 && 0 143 /* Midi Interface */ 144 static void cs4281_midi_close(void*); 145 static void cs4281_midi_getinfo(void *, struct midi_info *); 146 static int cs4281_midi_open(void *, int, void (*)(void *, int), 147 void (*)(void *), void *); 148 static int cs4281_midi_output(void *, int); 149 150 static const struct midi_hw_if cs4281_midi_hw_if = { 151 cs4281_midi_open, 152 cs4281_midi_close, 153 cs4281_midi_output, 154 cs4281_midi_getinfo, 155 0, 156 }; 157 #endif 158 159 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 160 cs4281_match, cs4281_attach, NULL, NULL); 161 162 static struct audio_device cs4281_device = { 163 "CS4281", 164 "", 165 "cs4281" 166 }; 167 168 169 static int 170 cs4281_match(struct device *parent, struct cfdata *match, void *aux) 171 { 172 struct pci_attach_args *pa; 173 174 pa = (struct pci_attach_args *)aux; 175 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 176 return 0; 177 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 178 return 1; 179 return 0; 180 } 181 182 static void 183 cs4281_attach(struct device *parent, struct device *self, void *aux) 184 { 185 struct cs428x_softc *sc; 186 struct pci_attach_args *pa; 187 pci_chipset_tag_t pc; 188 char const *intrstr; 189 pci_intr_handle_t ih; 190 pcireg_t reg; 191 char devinfo[256]; 192 int error; 193 194 sc = (struct cs428x_softc *)self; 195 pa = (struct pci_attach_args *)aux; 196 pc = pa->pa_pc; 197 aprint_naive(": Audio controller\n"); 198 199 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 200 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 201 PCI_REVISION(pa->pa_class)); 202 203 /* Map I/O register */ 204 if (pci_mapreg_map(pa, PCI_BA0, 205 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 206 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 207 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 208 return; 209 } 210 if (pci_mapreg_map(pa, PCI_BA1, 211 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 212 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 213 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 214 return; 215 } 216 217 sc->sc_dmatag = pa->pa_dmat; 218 219 /* power up chip */ 220 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 221 pci_activate_null)) && error != EOPNOTSUPP) { 222 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 223 error); 224 return; 225 } 226 227 /* Enable the device (set bus master flag) */ 228 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 229 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 230 reg | PCI_COMMAND_MASTER_ENABLE); 231 232 #if 0 233 /* LATENCY_TIMER setting */ 234 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 235 if (PCI_LATTIMER(temp1) < 32) { 236 temp1 &= 0xffff00ff; 237 temp1 |= 0x00002000; 238 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 239 } 240 #endif 241 242 /* Map and establish the interrupt. */ 243 if (pci_intr_map(pa, &ih)) { 244 aprint_error("%s: couldn't map interrupt\n", 245 sc->sc_dev.dv_xname); 246 return; 247 } 248 intrstr = pci_intr_string(pc, ih); 249 250 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 251 if (sc->sc_ih == NULL) { 252 aprint_error("%s: couldn't establish interrupt", 253 sc->sc_dev.dv_xname); 254 if (intrstr != NULL) 255 aprint_normal(" at %s", intrstr); 256 aprint_normal("\n"); 257 return; 258 } 259 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 260 261 /* 262 * Sound System start-up 263 */ 264 if (cs4281_init(sc, 1) != 0) 265 return; 266 267 sc->type = TYPE_CS4281; 268 sc->halt_input = cs4281_halt_input; 269 sc->halt_output = cs4281_halt_output; 270 271 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 272 sc->dma_align = 0x10; 273 sc->hw_blocksize = sc->dma_size / 2; 274 275 /* AC 97 attachment */ 276 sc->host_if.arg = sc; 277 sc->host_if.attach = cs428x_attach_codec; 278 sc->host_if.read = cs428x_read_codec; 279 sc->host_if.write = cs428x_write_codec; 280 sc->host_if.reset = cs4281_reset_codec; 281 if (ac97_attach(&sc->host_if, self) != 0) { 282 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 283 return; 284 } 285 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 286 287 #if NMIDI > 0 && 0 288 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 289 #endif 290 291 sc->sc_suspend = PWR_RESUME; 292 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 293 } 294 295 static int 296 cs4281_intr(void *p) 297 { 298 struct cs428x_softc *sc; 299 uint32_t intr, hdsr0, hdsr1; 300 char *empty_dma; 301 int handled; 302 303 sc = p; 304 handled = 0; 305 hdsr0 = 0; 306 hdsr1 = 0; 307 308 /* grab interrupt register */ 309 intr = BA0READ4(sc, CS4281_HISR); 310 311 DPRINTF(("cs4281_intr:")); 312 /* not for me */ 313 if ((intr & HISR_INTENA) == 0) { 314 /* clear the interrupt register */ 315 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 316 return 0; 317 } 318 319 if (intr & HISR_DMA0) 320 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 321 if (intr & HISR_DMA1) 322 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 323 /* clear the interrupt register */ 324 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 325 326 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 327 intr, hdsr0, hdsr1)); 328 329 /* Playback Interrupt */ 330 if (intr & HISR_DMA0) { 331 handled = 1; 332 if (sc->sc_prun) { 333 DPRINTF((" PB DMA 0x%x(%d)", 334 (int)BA0READ4(sc, CS4281_DCA0), 335 (int)BA0READ4(sc, CS4281_DCC0))); 336 if ((sc->sc_pi%sc->sc_pcount) == 0) 337 sc->sc_pintr(sc->sc_parg); 338 /* copy buffer */ 339 ++sc->sc_pi; 340 empty_dma = sc->sc_pdma->addr; 341 if (sc->sc_pi&1) 342 empty_dma += sc->hw_blocksize; 343 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 344 sc->sc_pn += sc->hw_blocksize; 345 if (sc->sc_pn >= sc->sc_pe) 346 sc->sc_pn = sc->sc_ps; 347 } else { 348 printf("%s: unexpected play intr\n", 349 sc->sc_dev.dv_xname); 350 } 351 } 352 if (intr & HISR_DMA1) { 353 handled = 1; 354 if (sc->sc_rrun) { 355 /* copy from DMA */ 356 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 357 (int)BA0READ4(sc, CS4281_DCC1))); 358 ++sc->sc_ri; 359 empty_dma = sc->sc_rdma->addr; 360 if ((sc->sc_ri & 1) == 0) 361 empty_dma += sc->hw_blocksize; 362 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 363 sc->sc_rn += sc->hw_blocksize; 364 if (sc->sc_rn >= sc->sc_re) 365 sc->sc_rn = sc->sc_rs; 366 if ((sc->sc_ri % sc->sc_rcount) == 0) 367 sc->sc_rintr(sc->sc_rarg); 368 } else { 369 printf("%s: unexpected record intr\n", 370 sc->sc_dev.dv_xname); 371 } 372 } 373 DPRINTF(("\n")); 374 375 return handled; 376 } 377 378 static int 379 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 380 { 381 382 switch (fp->index) { 383 case 0: 384 strcpy(fp->name, AudioEulinear); 385 fp->encoding = AUDIO_ENCODING_ULINEAR; 386 fp->precision = 8; 387 fp->flags = 0; 388 break; 389 case 1: 390 strcpy(fp->name, AudioEmulaw); 391 fp->encoding = AUDIO_ENCODING_ULAW; 392 fp->precision = 8; 393 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 394 break; 395 case 2: 396 strcpy(fp->name, AudioEalaw); 397 fp->encoding = AUDIO_ENCODING_ALAW; 398 fp->precision = 8; 399 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 400 break; 401 case 3: 402 strcpy(fp->name, AudioEslinear); 403 fp->encoding = AUDIO_ENCODING_SLINEAR; 404 fp->precision = 8; 405 fp->flags = 0; 406 break; 407 case 4: 408 strcpy(fp->name, AudioEslinear_le); 409 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 410 fp->precision = 16; 411 fp->flags = 0; 412 break; 413 case 5: 414 strcpy(fp->name, AudioEulinear_le); 415 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 416 fp->precision = 16; 417 fp->flags = 0; 418 break; 419 case 6: 420 strcpy(fp->name, AudioEslinear_be); 421 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 422 fp->precision = 16; 423 fp->flags = 0; 424 break; 425 case 7: 426 strcpy(fp->name, AudioEulinear_be); 427 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 428 fp->precision = 16; 429 fp->flags = 0; 430 break; 431 default: 432 return EINVAL; 433 } 434 return 0; 435 } 436 437 static int 438 cs4281_set_params(void *addr, int setmode, int usemode, 439 audio_params_t *play, audio_params_t *rec, 440 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 441 { 442 audio_params_t hw; 443 struct cs428x_softc *sc; 444 audio_params_t *p; 445 stream_filter_list_t *fil; 446 int mode; 447 448 sc = addr; 449 for (mode = AUMODE_RECORD; mode != -1; 450 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 451 if ((setmode & mode) == 0) 452 continue; 453 454 p = mode == AUMODE_PLAY ? play : rec; 455 456 if (p == play) { 457 DPRINTFN(5, 458 ("play: sample=%u precision=%u channels=%u\n", 459 p->sample_rate, p->precision, p->channels)); 460 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 461 (p->precision != 8 && p->precision != 16) || 462 (p->channels != 1 && p->channels != 2)) { 463 return EINVAL; 464 } 465 } else { 466 DPRINTFN(5, 467 ("rec: sample=%u precision=%u channels=%u\n", 468 p->sample_rate, p->precision, p->channels)); 469 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 470 (p->precision != 8 && p->precision != 16) || 471 (p->channels != 1 && p->channels != 2)) { 472 return EINVAL; 473 } 474 } 475 hw = *p; 476 fil = mode == AUMODE_PLAY ? pfil : rfil; 477 478 switch (p->encoding) { 479 case AUDIO_ENCODING_SLINEAR_BE: 480 break; 481 case AUDIO_ENCODING_SLINEAR_LE: 482 break; 483 case AUDIO_ENCODING_ULINEAR_BE: 484 break; 485 case AUDIO_ENCODING_ULINEAR_LE: 486 break; 487 case AUDIO_ENCODING_ULAW: 488 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 489 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 490 : linear8_to_mulaw, &hw); 491 break; 492 case AUDIO_ENCODING_ALAW: 493 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 494 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 495 : linear8_to_alaw, &hw); 496 break; 497 default: 498 return EINVAL; 499 } 500 } 501 502 /* set sample rate */ 503 cs4281_set_dac_rate(sc, play->sample_rate); 504 cs4281_set_adc_rate(sc, rec->sample_rate); 505 return 0; 506 } 507 508 static int 509 cs4281_halt_output(void *addr) 510 { 511 struct cs428x_softc *sc; 512 513 sc = addr; 514 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 515 sc->sc_prun = 0; 516 return 0; 517 } 518 519 static int 520 cs4281_halt_input(void *addr) 521 { 522 struct cs428x_softc *sc; 523 524 sc = addr; 525 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 526 sc->sc_rrun = 0; 527 return 0; 528 } 529 530 static int 531 cs4281_getdev(void *addr, struct audio_device *retp) 532 { 533 534 *retp = cs4281_device; 535 return 0; 536 } 537 538 static int 539 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 540 void (*intr)(void *), void *arg, 541 const audio_params_t *param) 542 { 543 struct cs428x_softc *sc; 544 uint32_t fmt; 545 struct cs428x_dma *p; 546 int dma_count; 547 548 sc = addr; 549 fmt = 0; 550 #ifdef DIAGNOSTIC 551 if (sc->sc_prun) 552 printf("cs4281_trigger_output: already running\n"); 553 #endif 554 sc->sc_prun = 1; 555 556 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 557 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 558 sc->sc_pintr = intr; 559 sc->sc_parg = arg; 560 561 /* stop playback DMA */ 562 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 563 564 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 565 param->precision, param->channels, param->encoding)); 566 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 567 continue; 568 if (p == NULL) { 569 printf("cs4281_trigger_output: bad addr %p\n", start); 570 return EINVAL; 571 } 572 573 sc->sc_pcount = blksize / sc->hw_blocksize; 574 sc->sc_ps = (char *)start; 575 sc->sc_pe = (char *)end; 576 sc->sc_pdma = p; 577 sc->sc_pbuf = KERNADDR(p); 578 sc->sc_pi = 0; 579 sc->sc_pn = sc->sc_ps; 580 if (blksize >= sc->dma_size) { 581 sc->sc_pn = sc->sc_ps + sc->dma_size; 582 memcpy(sc->sc_pbuf, start, sc->dma_size); 583 ++sc->sc_pi; 584 } else { 585 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 586 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 587 } 588 589 dma_count = sc->dma_size; 590 if (param->precision != 8) 591 dma_count /= 2; /* 16 bit */ 592 if (param->channels > 1) 593 dma_count /= 2; /* Stereo */ 594 595 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 596 (int)DMAADDR(p), dma_count)); 597 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 598 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 599 600 /* set playback format */ 601 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 602 if (param->precision == 8) 603 fmt |= DMRn_SIZE8; 604 if (param->channels == 1) 605 fmt |= DMRn_MONO; 606 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 607 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 608 fmt |= DMRn_BEND; 609 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 610 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 611 fmt |= DMRn_USIGN; 612 BA0WRITE4(sc, CS4281_DMR0, fmt); 613 614 /* set sample rate */ 615 sc->sc_prate = param->sample_rate; 616 cs4281_set_dac_rate(sc, param->sample_rate); 617 618 /* start DMA */ 619 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 620 /* Enable interrupts */ 621 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 622 623 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 624 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 625 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 626 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 627 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 628 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 629 BA0READ4(sc, CS4281_DACSR))); 630 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 631 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 632 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 633 634 return 0; 635 } 636 637 static int 638 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 639 void (*intr)(void *), void *arg, 640 const audio_params_t *param) 641 { 642 struct cs428x_softc *sc; 643 struct cs428x_dma *p; 644 uint32_t fmt; 645 int dma_count; 646 647 sc = addr; 648 fmt = 0; 649 #ifdef DIAGNOSTIC 650 if (sc->sc_rrun) 651 printf("cs4281_trigger_input: already running\n"); 652 #endif 653 sc->sc_rrun = 1; 654 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 655 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 656 sc->sc_rintr = intr; 657 sc->sc_rarg = arg; 658 659 /* stop recording DMA */ 660 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 661 662 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 663 continue; 664 if (!p) { 665 printf("cs4281_trigger_input: bad addr %p\n", start); 666 return EINVAL; 667 } 668 669 sc->sc_rcount = blksize / sc->hw_blocksize; 670 sc->sc_rs = (char *)start; 671 sc->sc_re = (char *)end; 672 sc->sc_rdma = p; 673 sc->sc_rbuf = KERNADDR(p); 674 sc->sc_ri = 0; 675 sc->sc_rn = sc->sc_rs; 676 677 dma_count = sc->dma_size; 678 if (param->precision != 8) 679 dma_count /= 2; 680 if (param->channels > 1) 681 dma_count /= 2; 682 683 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 684 (int)DMAADDR(p), dma_count)); 685 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 686 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 687 688 /* set recording format */ 689 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 690 if (param->precision == 8) 691 fmt |= DMRn_SIZE8; 692 if (param->channels == 1) 693 fmt |= DMRn_MONO; 694 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 695 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 696 fmt |= DMRn_BEND; 697 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 698 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 699 fmt |= DMRn_USIGN; 700 BA0WRITE4(sc, CS4281_DMR1, fmt); 701 702 /* set sample rate */ 703 sc->sc_rrate = param->sample_rate; 704 cs4281_set_adc_rate(sc, param->sample_rate); 705 706 /* Start DMA */ 707 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 708 /* Enable interrupts */ 709 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 710 711 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 712 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 713 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 714 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 715 716 return 0; 717 } 718 719 /* Power Hook */ 720 static void 721 cs4281_power(int why, void *v) 722 { 723 static uint32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 724 static uint32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 725 struct cs428x_softc *sc; 726 727 sc = (struct cs428x_softc *)v; 728 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 729 switch (why) { 730 case PWR_SUSPEND: 731 case PWR_STANDBY: 732 sc->sc_suspend = why; 733 734 /* save current playback status */ 735 if (sc->sc_prun) { 736 dcr0 = BA0READ4(sc, CS4281_DCR0); 737 dmr0 = BA0READ4(sc, CS4281_DMR0); 738 dbc0 = BA0READ4(sc, CS4281_DBC0); 739 dba0 = BA0READ4(sc, CS4281_DBA0); 740 } 741 742 /* save current capture status */ 743 if (sc->sc_rrun) { 744 dcr1 = BA0READ4(sc, CS4281_DCR1); 745 dmr1 = BA0READ4(sc, CS4281_DMR1); 746 dbc1 = BA0READ4(sc, CS4281_DBC1); 747 dba1 = BA0READ4(sc, CS4281_DBA1); 748 } 749 /* Stop DMA */ 750 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 751 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 752 break; 753 case PWR_RESUME: 754 if (sc->sc_suspend == PWR_RESUME) { 755 printf("cs4281_power: odd, resume without suspend.\n"); 756 sc->sc_suspend = why; 757 return; 758 } 759 sc->sc_suspend = why; 760 cs4281_init(sc, 0); 761 cs4281_reset_codec(sc); 762 763 /* restore ac97 registers */ 764 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 765 766 /* restore DMA related status */ 767 if (sc->sc_prun) { 768 cs4281_set_dac_rate(sc, sc->sc_prate); 769 BA0WRITE4(sc, CS4281_DBA0, dba0); 770 BA0WRITE4(sc, CS4281_DBC0, dbc0); 771 BA0WRITE4(sc, CS4281_DMR0, dmr0); 772 BA0WRITE4(sc, CS4281_DCR0, dcr0); 773 } 774 if (sc->sc_rrun) { 775 cs4281_set_adc_rate(sc, sc->sc_rrate); 776 BA0WRITE4(sc, CS4281_DBA1, dba1); 777 BA0WRITE4(sc, CS4281_DBC1, dbc1); 778 BA0WRITE4(sc, CS4281_DMR1, dmr1); 779 BA0WRITE4(sc, CS4281_DCR1, dcr1); 780 } 781 /* enable intterupts */ 782 if (sc->sc_prun || sc->sc_rrun) 783 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 784 break; 785 case PWR_SOFTSUSPEND: 786 case PWR_SOFTSTANDBY: 787 case PWR_SOFTRESUME: 788 break; 789 } 790 } 791 792 /* control AC97 codec */ 793 static int 794 cs4281_reset_codec(void *addr) 795 { 796 struct cs428x_softc *sc; 797 uint16_t data; 798 uint32_t dat32; 799 int n; 800 801 sc = addr; 802 803 DPRINTFN(3, ("cs4281_reset_codec\n")); 804 805 /* Reset codec */ 806 BA0WRITE4(sc, CS428X_ACCTL, 0); 807 delay(50); /* delay 50us */ 808 809 BA0WRITE4(sc, CS4281_SPMC, 0); 810 delay(100); /* delay 100us */ 811 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 812 #if defined(ENABLE_SECONDARY_CODEC) 813 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 814 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 815 #endif 816 delay(50000); /* XXX: delay 50ms */ 817 818 /* Enable ASYNC generation */ 819 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 820 821 /* Wait for codec ready. Linux driver waits 50ms here */ 822 n = 0; 823 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 824 delay(100); 825 if (++n > 1000) { 826 printf("reset_codec: AC97 codec ready timeout\n"); 827 return ETIMEDOUT; 828 } 829 } 830 #if defined(ENABLE_SECONDARY_CODEC) 831 /* secondary codec ready*/ 832 n = 0; 833 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 834 delay(100); 835 if (++n > 1000) 836 return 0; 837 } 838 #endif 839 /* Set the serial timing configuration */ 840 /* XXX: undocumented but the Linux driver do this */ 841 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 842 843 /* Wait for codec ready signal */ 844 n = 0; 845 do { 846 delay(1000); 847 if (++n > 1000) { 848 printf("%s: timeout waiting for codec ready\n", 849 sc->sc_dev.dv_xname); 850 return ETIMEDOUT; 851 } 852 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 853 } while (dat32 == 0); 854 855 /* Enable Valid Frame output on ASDOUT */ 856 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 857 858 /* Wait until codec calibration is finished. Codec register 26h */ 859 n = 0; 860 do { 861 delay(1); 862 if (++n > 1000) { 863 printf("%s: timeout waiting for codec calibration\n", 864 sc->sc_dev.dv_xname); 865 return ETIMEDOUT; 866 } 867 cs428x_read_codec(sc, AC97_REG_POWER, &data); 868 } while ((data & 0x0f) != 0x0f); 869 870 /* Set the serial timing configuration again */ 871 /* XXX: undocumented but the Linux driver do this */ 872 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 873 874 /* Wait until we've sampled input slots 3 & 4 as valid */ 875 n = 0; 876 do { 877 delay(1000); 878 if (++n > 1000) { 879 printf("%s: timeout waiting for sampled input slots as valid\n", 880 sc->sc_dev.dv_xname); 881 return ETIMEDOUT; 882 } 883 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 884 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 885 886 /* Start digital data transfer of audio data to the codec */ 887 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 888 return 0; 889 } 890 891 892 /* Internal functions */ 893 894 /* convert sample rate to register value */ 895 static uint8_t 896 cs4281_sr2regval(int rate) 897 { 898 uint8_t retval; 899 900 /* We don't have to change here. but anyway ... */ 901 if (rate > 48000) 902 rate = 48000; 903 if (rate < 6023) 904 rate = 6023; 905 906 switch (rate) { 907 case 8000: 908 retval = 5; 909 break; 910 case 11025: 911 retval = 4; 912 break; 913 case 16000: 914 retval = 3; 915 break; 916 case 22050: 917 retval = 2; 918 break; 919 case 44100: 920 retval = 1; 921 break; 922 case 48000: 923 retval = 0; 924 break; 925 default: 926 retval = 1536000/rate; /* == 24576000/(rate*16) */ 927 } 928 return retval; 929 } 930 931 static void 932 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 933 { 934 935 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 936 } 937 938 static void 939 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 940 { 941 942 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 943 } 944 945 static int 946 cs4281_init(struct cs428x_softc *sc, int init) 947 { 948 int n; 949 uint16_t data; 950 uint32_t dat32; 951 952 /* set "Configuration Write Protect" register to 953 * 0x4281 to allow to write */ 954 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 955 956 /* 957 * Unset "Full Power-Down bit of Extended PCI Power Management 958 * Control" register to release the reset state. 959 */ 960 dat32 = BA0READ4(sc, CS4281_EPPMC); 961 if (dat32 & EPPMC_FPDN) { 962 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 963 } 964 965 /* Start PLL out in known state */ 966 BA0WRITE4(sc, CS4281_CLKCR1, 0); 967 /* Start serial ports out in known state */ 968 BA0WRITE4(sc, CS4281_SERMC, 0); 969 970 /* Reset codec */ 971 BA0WRITE4(sc, CS428X_ACCTL, 0); 972 delay(50); /* delay 50us */ 973 974 BA0WRITE4(sc, CS4281_SPMC, 0); 975 delay(100); /* delay 100us */ 976 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 977 #if defined(ENABLE_SECONDARY_CODEC) 978 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 979 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 980 #endif 981 delay(50000); /* XXX: delay 50ms */ 982 983 /* Turn on Sound System clocks based on ABITCLK */ 984 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 985 delay(50000); /* XXX: delay 50ms */ 986 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 987 988 /* Set enables for sections that are needed in the SSPM registers */ 989 BA0WRITE4(sc, CS4281_SSPM, 990 SSPM_MIXEN | /* Mixer */ 991 SSPM_CSRCEN | /* Capture SRC */ 992 SSPM_PSRCEN | /* Playback SRC */ 993 SSPM_JSEN | /* Joystick */ 994 SSPM_ACLEN | /* AC LINK */ 995 SSPM_FMEN /* FM */ 996 ); 997 998 /* Wait for clock stabilization */ 999 n = 0; 1000 #if 1 1001 /* what document says */ 1002 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1003 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1004 delay(100); 1005 if (++n > 1000) { 1006 printf("%s: timeout waiting for clock stabilization\n", 1007 sc->sc_dev.dv_xname); 1008 return -1; 1009 } 1010 } 1011 #else 1012 /* Cirrus driver for Linux does */ 1013 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1014 delay(1000); 1015 if (++n > 1000) { 1016 printf("%s: timeout waiting for clock stabilization\n", 1017 sc->sc_dev.dv_xname); 1018 return -1; 1019 } 1020 } 1021 #endif 1022 1023 /* Enable ASYNC generation */ 1024 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1025 1026 /* Wait for codec ready. Linux driver waits 50ms here */ 1027 n = 0; 1028 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1029 delay(100); 1030 if (++n > 1000) { 1031 printf("%s: timeout waiting for codec ready\n", 1032 sc->sc_dev.dv_xname); 1033 return -1; 1034 } 1035 } 1036 1037 #if defined(ENABLE_SECONDARY_CODEC) 1038 /* secondary codec ready*/ 1039 n = 0; 1040 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1041 delay(100); 1042 if (++n > 1000) { 1043 printf("%s: timeout waiting for secondary codec ready\n", 1044 sc->sc_dev.dv_xname); 1045 return -1; 1046 } 1047 } 1048 #endif 1049 1050 /* Set the serial timing configuration */ 1051 /* XXX: undocumented but the Linux driver do this */ 1052 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1053 1054 /* Wait for codec ready signal */ 1055 n = 0; 1056 do { 1057 delay(1000); 1058 if (++n > 1000) { 1059 printf("%s: timeout waiting for codec ready\n", 1060 sc->sc_dev.dv_xname); 1061 return -1; 1062 } 1063 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1064 } while (dat32 == 0); 1065 1066 /* Enable Valid Frame output on ASDOUT */ 1067 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1068 1069 /* Wait until codec calibration is finished. codec register 26h */ 1070 n = 0; 1071 do { 1072 delay(1); 1073 if (++n > 1000) { 1074 printf("%s: timeout waiting for codec calibration\n", 1075 sc->sc_dev.dv_xname); 1076 return -1; 1077 } 1078 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1079 } while ((data & 0x0f) != 0x0f); 1080 1081 /* Set the serial timing configuration again */ 1082 /* XXX: undocumented but the Linux driver do this */ 1083 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1084 1085 /* Wait until we've sampled input slots 3 & 4 as valid */ 1086 n = 0; 1087 do { 1088 delay(1000); 1089 if (++n > 1000) { 1090 printf("%s: timeout waiting for sampled input slots as valid\n", 1091 sc->sc_dev.dv_xname); 1092 return -1; 1093 } 1094 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1095 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1096 1097 /* Start digital data transfer of audio data to the codec */ 1098 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1099 1100 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1101 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1102 1103 /* Power on the DAC */ 1104 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1105 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1106 1107 /* Wait until we sample a DAC ready state. 1108 * Not documented, but Linux driver does. 1109 */ 1110 for (n = 0; n < 32; ++n) { 1111 delay(1000); 1112 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1113 if (data & 0x02) 1114 break; 1115 } 1116 1117 /* Power on the ADC */ 1118 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1119 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1120 1121 /* Wait until we sample ADC ready state. 1122 * Not documented, but Linux driver does. 1123 */ 1124 for (n = 0; n < 32; ++n) { 1125 delay(1000); 1126 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1127 if (data & 0x01) 1128 break; 1129 } 1130 1131 #if 0 1132 /* Initialize AC-Link features */ 1133 /* variable sample-rate support */ 1134 mem = BA0READ4(sc, CS4281_SERMC); 1135 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1136 BA0WRITE4(sc, CS4281_SERMC, mem); 1137 /* XXX: more... */ 1138 1139 /* Initialize SSCR register features */ 1140 /* XXX: hardware volume setting */ 1141 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1142 #endif 1143 1144 /* disable Sound Blaster Pro emulation */ 1145 /* XXX: 1146 * Cannot set since the documents does not describe which bit is 1147 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1148 * we can ignore it.*/ 1149 #if 0 1150 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1151 #endif 1152 1153 /* map AC97 PCM playback to DMA Channel 0 */ 1154 /* Reset FEN bit to setup first */ 1155 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1156 /* 1157 *| RS[4:0]/| | 1158 *| LS[4:0] | AC97 | Slot Function 1159 *|---------+--------+-------------------- 1160 *| 0 | 3 | Left PCM Playback 1161 *| 1 | 4 | Right PCM Playback 1162 *| 2 | 5 | Phone Line 1 DAC 1163 *| 3 | 6 | Center PCM Playback 1164 *.... 1165 * quoted from Table 29(p109) 1166 */ 1167 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1168 0x00 << 16 | /* LS[4:0] = 0 see above */ 1169 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1170 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1171 BA0WRITE4(sc, CS4281_FCR0, dat32); 1172 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1173 1174 /* map AC97 PCM record to DMA Channel 1 */ 1175 /* Reset FEN bit to setup first */ 1176 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1177 /* 1178 *| RS[4:0]/| 1179 *| LS[4:0] | AC97 | Slot Function 1180 *|---------+------+------------------- 1181 *| 10 | 3 | Left PCM Record 1182 *| 11 | 4 | Right PCM Record 1183 *| 12 | 5 | Phone Line 1 ADC 1184 *| 13 | 6 | Mic ADC 1185 *.... 1186 * quoted from Table 30(p109) 1187 */ 1188 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1189 0x0a << 16 | /* LS[4:0] = 10 See above */ 1190 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1191 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1192 1193 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1194 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1195 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1196 1197 #if 0 1198 /* Disable DMA Channel 2, 3 */ 1199 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1200 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1201 #endif 1202 1203 /* Set the SRC Slot Assignment accordingly */ 1204 /*| PLSS[4:0]/ 1205 *| PRSS[4:0] | AC97 | Slot Function 1206 *|-----------+------+---------------- 1207 *| 0 | 3 | Left PCM Playback 1208 *| 1 | 4 | Right PCM Playback 1209 *| 2 | 5 | phone line 1 DAC 1210 *| 3 | 6 | Center PCM Playback 1211 *| 4 | 7 | Left Surround PCM Playback 1212 *| 5 | 8 | Right Surround PCM Playback 1213 *...... 1214 * 1215 *| CLSS[4:0]/ 1216 *| CRSS[4:0] | AC97 | Codec |Slot Function 1217 *|-----------+------+-------+----------------- 1218 *| 10 | 3 |Primary| Left PCM Record 1219 *| 11 | 4 |Primary| Right PCM Record 1220 *| 12 | 5 |Primary| Phone Line 1 ADC 1221 *| 13 | 6 |Primary| Mic ADC 1222 *|..... 1223 *| 20 | 3 | Sec. | Left PCM Record 1224 *| 21 | 4 | Sec. | Right PCM Record 1225 *| 22 | 5 | Sec. | Phone Line 1 ADC 1226 *| 23 | 6 | Sec. | Mic ADC 1227 */ 1228 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1229 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1230 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1231 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1232 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1233 1234 /* Set interrupt to occurred at Half and Full terminal 1235 * count interrupt enable for DMA channel 0 and 1. 1236 * To keep DMA stop, set MSK. 1237 */ 1238 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1239 BA0WRITE4(sc, CS4281_DCR0, dat32); 1240 BA0WRITE4(sc, CS4281_DCR1, dat32); 1241 1242 /* Set Auto-Initialize Contorl enable */ 1243 BA0WRITE4(sc, CS4281_DMR0, 1244 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1245 BA0WRITE4(sc, CS4281_DMR1, 1246 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1247 1248 /* Clear DMA Mask in HIMR */ 1249 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1250 BA0WRITE4(sc, CS4281_HIMR, 1251 BA0READ4(sc, CS4281_HIMR) & dat32); 1252 1253 /* set current status */ 1254 if (init != 0) { 1255 sc->sc_prun = 0; 1256 sc->sc_rrun = 0; 1257 } 1258 1259 /* setup playback volume */ 1260 BA0WRITE4(sc, CS4281_PPRVC, 7); 1261 BA0WRITE4(sc, CS4281_PPLVC, 7); 1262 1263 return 0; 1264 } 1265
Indexes created Tue Sep 30 20:09:53 GMT 2025