cs4281.c revision 1.31
1 /* $NetBSD: cs4281.c,v 1.31 2006/09/24 03:53:09 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.31 2006/09/24 03:53:09 jmcneill Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(struct device *, struct cfdata *, void *); 84 static void cs4281_attach(struct device *, struct device *, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static void cs4281_power(int, void *); 110 111 static const struct audio_hw_if cs4281_hw_if = { 112 NULL, /* open */ 113 NULL, /* close */ 114 NULL, 115 cs4281_query_encoding, 116 cs4281_set_params, 117 cs428x_round_blocksize, 118 NULL, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 cs4281_halt_output, 124 cs4281_halt_input, 125 NULL, 126 cs4281_getdev, 127 NULL, 128 cs428x_mixer_set_port, 129 cs428x_mixer_get_port, 130 cs428x_query_devinfo, 131 cs428x_malloc, 132 cs428x_free, 133 cs428x_round_buffersize, 134 cs428x_mappage, 135 cs428x_get_props, 136 cs4281_trigger_output, 137 cs4281_trigger_input, 138 NULL, 139 NULL, 140 }; 141 142 #if NMIDI > 0 && 0 143 /* Midi Interface */ 144 static void cs4281_midi_close(void*); 145 static void cs4281_midi_getinfo(void *, struct midi_info *); 146 static int cs4281_midi_open(void *, int, void (*)(void *, int), 147 void (*)(void *), void *); 148 static int cs4281_midi_output(void *, int); 149 150 static const struct midi_hw_if cs4281_midi_hw_if = { 151 cs4281_midi_open, 152 cs4281_midi_close, 153 cs4281_midi_output, 154 cs4281_midi_getinfo, 155 0, 156 }; 157 #endif 158 159 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 160 cs4281_match, cs4281_attach, NULL, NULL); 161 162 static struct audio_device cs4281_device = { 163 "CS4281", 164 "", 165 "cs4281" 166 }; 167 168 169 static int 170 cs4281_match(struct device *parent, struct cfdata *match, void *aux) 171 { 172 struct pci_attach_args *pa; 173 174 pa = (struct pci_attach_args *)aux; 175 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 176 return 0; 177 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 178 return 1; 179 return 0; 180 } 181 182 static void 183 cs4281_attach(struct device *parent, struct device *self, void *aux) 184 { 185 struct cs428x_softc *sc; 186 struct pci_attach_args *pa; 187 pci_chipset_tag_t pc; 188 char const *intrstr; 189 pci_intr_handle_t ih; 190 pcireg_t reg; 191 char devinfo[256]; 192 int error; 193 194 sc = (struct cs428x_softc *)self; 195 pa = (struct pci_attach_args *)aux; 196 pc = pa->pa_pc; 197 aprint_naive(": Audio controller\n"); 198 199 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 200 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 201 PCI_REVISION(pa->pa_class)); 202 203 /* Map I/O register */ 204 if (pci_mapreg_map(pa, PCI_BA0, 205 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 206 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 207 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 208 return; 209 } 210 if (pci_mapreg_map(pa, PCI_BA1, 211 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 212 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 213 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 214 return; 215 } 216 217 sc->sc_dmatag = pa->pa_dmat; 218 219 /* power up chip */ 220 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 221 pci_activate_null)) && error != EOPNOTSUPP) { 222 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 223 error); 224 return; 225 } 226 227 /* Enable the device (set bus master flag) */ 228 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 229 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 230 reg | PCI_COMMAND_MASTER_ENABLE); 231 232 #if 0 233 /* LATENCY_TIMER setting */ 234 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 235 if (PCI_LATTIMER(temp1) < 32) { 236 temp1 &= 0xffff00ff; 237 temp1 |= 0x00002000; 238 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 239 } 240 #endif 241 242 /* Map and establish the interrupt. */ 243 if (pci_intr_map(pa, &ih)) { 244 aprint_error("%s: couldn't map interrupt\n", 245 sc->sc_dev.dv_xname); 246 return; 247 } 248 intrstr = pci_intr_string(pc, ih); 249 250 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 251 if (sc->sc_ih == NULL) { 252 aprint_error("%s: couldn't establish interrupt", 253 sc->sc_dev.dv_xname); 254 if (intrstr != NULL) 255 aprint_normal(" at %s", intrstr); 256 aprint_normal("\n"); 257 return; 258 } 259 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 260 261 /* 262 * Sound System start-up 263 */ 264 if (cs4281_init(sc, 1) != 0) 265 return; 266 267 sc->type = TYPE_CS4281; 268 sc->halt_input = cs4281_halt_input; 269 sc->halt_output = cs4281_halt_output; 270 271 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 272 sc->dma_align = 0x10; 273 sc->hw_blocksize = sc->dma_size / 2; 274 275 /* AC 97 attachment */ 276 sc->host_if.arg = sc; 277 sc->host_if.attach = cs428x_attach_codec; 278 sc->host_if.read = cs428x_read_codec; 279 sc->host_if.write = cs428x_write_codec; 280 sc->host_if.reset = cs4281_reset_codec; 281 if (ac97_attach(&sc->host_if, self) != 0) { 282 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 283 return; 284 } 285 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 286 287 #if NMIDI > 0 && 0 288 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 289 #endif 290 291 sc->sc_suspend = PWR_RESUME; 292 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 293 cs4281_power, sc); 294 } 295 296 static int 297 cs4281_intr(void *p) 298 { 299 struct cs428x_softc *sc; 300 uint32_t intr, hdsr0, hdsr1; 301 char *empty_dma; 302 int handled; 303 304 sc = p; 305 handled = 0; 306 hdsr0 = 0; 307 hdsr1 = 0; 308 309 /* grab interrupt register */ 310 intr = BA0READ4(sc, CS4281_HISR); 311 312 DPRINTF(("cs4281_intr:")); 313 /* not for me */ 314 if ((intr & HISR_INTENA) == 0) { 315 /* clear the interrupt register */ 316 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 317 return 0; 318 } 319 320 if (intr & HISR_DMA0) 321 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 322 if (intr & HISR_DMA1) 323 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 324 /* clear the interrupt register */ 325 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 326 327 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 328 intr, hdsr0, hdsr1)); 329 330 /* Playback Interrupt */ 331 if (intr & HISR_DMA0) { 332 handled = 1; 333 if (sc->sc_prun) { 334 DPRINTF((" PB DMA 0x%x(%d)", 335 (int)BA0READ4(sc, CS4281_DCA0), 336 (int)BA0READ4(sc, CS4281_DCC0))); 337 if ((sc->sc_pi%sc->sc_pcount) == 0) 338 sc->sc_pintr(sc->sc_parg); 339 /* copy buffer */ 340 ++sc->sc_pi; 341 empty_dma = sc->sc_pdma->addr; 342 if (sc->sc_pi&1) 343 empty_dma += sc->hw_blocksize; 344 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 345 sc->sc_pn += sc->hw_blocksize; 346 if (sc->sc_pn >= sc->sc_pe) 347 sc->sc_pn = sc->sc_ps; 348 } else { 349 printf("%s: unexpected play intr\n", 350 sc->sc_dev.dv_xname); 351 } 352 } 353 if (intr & HISR_DMA1) { 354 handled = 1; 355 if (sc->sc_rrun) { 356 /* copy from DMA */ 357 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 358 (int)BA0READ4(sc, CS4281_DCC1))); 359 ++sc->sc_ri; 360 empty_dma = sc->sc_rdma->addr; 361 if ((sc->sc_ri & 1) == 0) 362 empty_dma += sc->hw_blocksize; 363 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 364 sc->sc_rn += sc->hw_blocksize; 365 if (sc->sc_rn >= sc->sc_re) 366 sc->sc_rn = sc->sc_rs; 367 if ((sc->sc_ri % sc->sc_rcount) == 0) 368 sc->sc_rintr(sc->sc_rarg); 369 } else { 370 printf("%s: unexpected record intr\n", 371 sc->sc_dev.dv_xname); 372 } 373 } 374 DPRINTF(("\n")); 375 376 return handled; 377 } 378 379 static int 380 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 381 { 382 383 switch (fp->index) { 384 case 0: 385 strcpy(fp->name, AudioEulinear); 386 fp->encoding = AUDIO_ENCODING_ULINEAR; 387 fp->precision = 8; 388 fp->flags = 0; 389 break; 390 case 1: 391 strcpy(fp->name, AudioEmulaw); 392 fp->encoding = AUDIO_ENCODING_ULAW; 393 fp->precision = 8; 394 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 395 break; 396 case 2: 397 strcpy(fp->name, AudioEalaw); 398 fp->encoding = AUDIO_ENCODING_ALAW; 399 fp->precision = 8; 400 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 401 break; 402 case 3: 403 strcpy(fp->name, AudioEslinear); 404 fp->encoding = AUDIO_ENCODING_SLINEAR; 405 fp->precision = 8; 406 fp->flags = 0; 407 break; 408 case 4: 409 strcpy(fp->name, AudioEslinear_le); 410 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 411 fp->precision = 16; 412 fp->flags = 0; 413 break; 414 case 5: 415 strcpy(fp->name, AudioEulinear_le); 416 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 417 fp->precision = 16; 418 fp->flags = 0; 419 break; 420 case 6: 421 strcpy(fp->name, AudioEslinear_be); 422 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 423 fp->precision = 16; 424 fp->flags = 0; 425 break; 426 case 7: 427 strcpy(fp->name, AudioEulinear_be); 428 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 429 fp->precision = 16; 430 fp->flags = 0; 431 break; 432 default: 433 return EINVAL; 434 } 435 return 0; 436 } 437 438 static int 439 cs4281_set_params(void *addr, int setmode, int usemode, 440 audio_params_t *play, audio_params_t *rec, 441 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 442 { 443 audio_params_t hw; 444 struct cs428x_softc *sc; 445 audio_params_t *p; 446 stream_filter_list_t *fil; 447 int mode; 448 449 sc = addr; 450 for (mode = AUMODE_RECORD; mode != -1; 451 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 452 if ((setmode & mode) == 0) 453 continue; 454 455 p = mode == AUMODE_PLAY ? play : rec; 456 457 if (p == play) { 458 DPRINTFN(5, 459 ("play: sample=%u precision=%u channels=%u\n", 460 p->sample_rate, p->precision, p->channels)); 461 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 462 (p->precision != 8 && p->precision != 16) || 463 (p->channels != 1 && p->channels != 2)) { 464 return EINVAL; 465 } 466 } else { 467 DPRINTFN(5, 468 ("rec: sample=%u precision=%u channels=%u\n", 469 p->sample_rate, p->precision, p->channels)); 470 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 471 (p->precision != 8 && p->precision != 16) || 472 (p->channels != 1 && p->channels != 2)) { 473 return EINVAL; 474 } 475 } 476 hw = *p; 477 fil = mode == AUMODE_PLAY ? pfil : rfil; 478 479 switch (p->encoding) { 480 case AUDIO_ENCODING_SLINEAR_BE: 481 break; 482 case AUDIO_ENCODING_SLINEAR_LE: 483 break; 484 case AUDIO_ENCODING_ULINEAR_BE: 485 break; 486 case AUDIO_ENCODING_ULINEAR_LE: 487 break; 488 case AUDIO_ENCODING_ULAW: 489 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 490 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 491 : linear8_to_mulaw, &hw); 492 break; 493 case AUDIO_ENCODING_ALAW: 494 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 495 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 496 : linear8_to_alaw, &hw); 497 break; 498 default: 499 return EINVAL; 500 } 501 } 502 503 /* set sample rate */ 504 cs4281_set_dac_rate(sc, play->sample_rate); 505 cs4281_set_adc_rate(sc, rec->sample_rate); 506 return 0; 507 } 508 509 static int 510 cs4281_halt_output(void *addr) 511 { 512 struct cs428x_softc *sc; 513 514 sc = addr; 515 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 516 sc->sc_prun = 0; 517 return 0; 518 } 519 520 static int 521 cs4281_halt_input(void *addr) 522 { 523 struct cs428x_softc *sc; 524 525 sc = addr; 526 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 527 sc->sc_rrun = 0; 528 return 0; 529 } 530 531 static int 532 cs4281_getdev(void *addr, struct audio_device *retp) 533 { 534 535 *retp = cs4281_device; 536 return 0; 537 } 538 539 static int 540 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 541 void (*intr)(void *), void *arg, 542 const audio_params_t *param) 543 { 544 struct cs428x_softc *sc; 545 uint32_t fmt; 546 struct cs428x_dma *p; 547 int dma_count; 548 549 sc = addr; 550 fmt = 0; 551 #ifdef DIAGNOSTIC 552 if (sc->sc_prun) 553 printf("cs4281_trigger_output: already running\n"); 554 #endif 555 sc->sc_prun = 1; 556 557 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 558 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 559 sc->sc_pintr = intr; 560 sc->sc_parg = arg; 561 562 /* stop playback DMA */ 563 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 564 565 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 566 param->precision, param->channels, param->encoding)); 567 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 568 continue; 569 if (p == NULL) { 570 printf("cs4281_trigger_output: bad addr %p\n", start); 571 return EINVAL; 572 } 573 574 sc->sc_pcount = blksize / sc->hw_blocksize; 575 sc->sc_ps = (char *)start; 576 sc->sc_pe = (char *)end; 577 sc->sc_pdma = p; 578 sc->sc_pbuf = KERNADDR(p); 579 sc->sc_pi = 0; 580 sc->sc_pn = sc->sc_ps; 581 if (blksize >= sc->dma_size) { 582 sc->sc_pn = sc->sc_ps + sc->dma_size; 583 memcpy(sc->sc_pbuf, start, sc->dma_size); 584 ++sc->sc_pi; 585 } else { 586 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 587 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 588 } 589 590 dma_count = sc->dma_size; 591 if (param->precision != 8) 592 dma_count /= 2; /* 16 bit */ 593 if (param->channels > 1) 594 dma_count /= 2; /* Stereo */ 595 596 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 597 (int)DMAADDR(p), dma_count)); 598 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 599 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 600 601 /* set playback format */ 602 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 603 if (param->precision == 8) 604 fmt |= DMRn_SIZE8; 605 if (param->channels == 1) 606 fmt |= DMRn_MONO; 607 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 608 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 609 fmt |= DMRn_BEND; 610 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 611 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 612 fmt |= DMRn_USIGN; 613 BA0WRITE4(sc, CS4281_DMR0, fmt); 614 615 /* set sample rate */ 616 sc->sc_prate = param->sample_rate; 617 cs4281_set_dac_rate(sc, param->sample_rate); 618 619 /* start DMA */ 620 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 621 /* Enable interrupts */ 622 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 623 624 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 625 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 626 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 627 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 628 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 629 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 630 BA0READ4(sc, CS4281_DACSR))); 631 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 632 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 633 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 634 635 return 0; 636 } 637 638 static int 639 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 640 void (*intr)(void *), void *arg, 641 const audio_params_t *param) 642 { 643 struct cs428x_softc *sc; 644 struct cs428x_dma *p; 645 uint32_t fmt; 646 int dma_count; 647 648 sc = addr; 649 fmt = 0; 650 #ifdef DIAGNOSTIC 651 if (sc->sc_rrun) 652 printf("cs4281_trigger_input: already running\n"); 653 #endif 654 sc->sc_rrun = 1; 655 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 656 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 657 sc->sc_rintr = intr; 658 sc->sc_rarg = arg; 659 660 /* stop recording DMA */ 661 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 662 663 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 664 continue; 665 if (!p) { 666 printf("cs4281_trigger_input: bad addr %p\n", start); 667 return EINVAL; 668 } 669 670 sc->sc_rcount = blksize / sc->hw_blocksize; 671 sc->sc_rs = (char *)start; 672 sc->sc_re = (char *)end; 673 sc->sc_rdma = p; 674 sc->sc_rbuf = KERNADDR(p); 675 sc->sc_ri = 0; 676 sc->sc_rn = sc->sc_rs; 677 678 dma_count = sc->dma_size; 679 if (param->precision != 8) 680 dma_count /= 2; 681 if (param->channels > 1) 682 dma_count /= 2; 683 684 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 685 (int)DMAADDR(p), dma_count)); 686 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 687 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 688 689 /* set recording format */ 690 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 691 if (param->precision == 8) 692 fmt |= DMRn_SIZE8; 693 if (param->channels == 1) 694 fmt |= DMRn_MONO; 695 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 696 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 697 fmt |= DMRn_BEND; 698 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 699 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 700 fmt |= DMRn_USIGN; 701 BA0WRITE4(sc, CS4281_DMR1, fmt); 702 703 /* set sample rate */ 704 sc->sc_rrate = param->sample_rate; 705 cs4281_set_adc_rate(sc, param->sample_rate); 706 707 /* Start DMA */ 708 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 709 /* Enable interrupts */ 710 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 711 712 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 713 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 714 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 715 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 716 717 return 0; 718 } 719 720 /* Power Hook */ 721 static void 722 cs4281_power(int why, void *v) 723 { 724 static uint32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 725 static uint32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 726 struct cs428x_softc *sc; 727 728 sc = (struct cs428x_softc *)v; 729 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 730 switch (why) { 731 case PWR_SUSPEND: 732 case PWR_STANDBY: 733 sc->sc_suspend = why; 734 735 /* save current playback status */ 736 if (sc->sc_prun) { 737 dcr0 = BA0READ4(sc, CS4281_DCR0); 738 dmr0 = BA0READ4(sc, CS4281_DMR0); 739 dbc0 = BA0READ4(sc, CS4281_DBC0); 740 dba0 = BA0READ4(sc, CS4281_DBA0); 741 } 742 743 /* save current capture status */ 744 if (sc->sc_rrun) { 745 dcr1 = BA0READ4(sc, CS4281_DCR1); 746 dmr1 = BA0READ4(sc, CS4281_DMR1); 747 dbc1 = BA0READ4(sc, CS4281_DBC1); 748 dba1 = BA0READ4(sc, CS4281_DBA1); 749 } 750 /* Stop DMA */ 751 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 752 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 753 break; 754 case PWR_RESUME: 755 if (sc->sc_suspend == PWR_RESUME) { 756 printf("cs4281_power: odd, resume without suspend.\n"); 757 sc->sc_suspend = why; 758 return; 759 } 760 sc->sc_suspend = why; 761 cs4281_init(sc, 0); 762 cs4281_reset_codec(sc); 763 764 /* restore ac97 registers */ 765 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 766 767 /* restore DMA related status */ 768 if (sc->sc_prun) { 769 cs4281_set_dac_rate(sc, sc->sc_prate); 770 BA0WRITE4(sc, CS4281_DBA0, dba0); 771 BA0WRITE4(sc, CS4281_DBC0, dbc0); 772 BA0WRITE4(sc, CS4281_DMR0, dmr0); 773 BA0WRITE4(sc, CS4281_DCR0, dcr0); 774 } 775 if (sc->sc_rrun) { 776 cs4281_set_adc_rate(sc, sc->sc_rrate); 777 BA0WRITE4(sc, CS4281_DBA1, dba1); 778 BA0WRITE4(sc, CS4281_DBC1, dbc1); 779 BA0WRITE4(sc, CS4281_DMR1, dmr1); 780 BA0WRITE4(sc, CS4281_DCR1, dcr1); 781 } 782 /* enable intterupts */ 783 if (sc->sc_prun || sc->sc_rrun) 784 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 785 break; 786 case PWR_SOFTSUSPEND: 787 case PWR_SOFTSTANDBY: 788 case PWR_SOFTRESUME: 789 break; 790 } 791 } 792 793 /* control AC97 codec */ 794 static int 795 cs4281_reset_codec(void *addr) 796 { 797 struct cs428x_softc *sc; 798 uint16_t data; 799 uint32_t dat32; 800 int n; 801 802 sc = addr; 803 804 DPRINTFN(3, ("cs4281_reset_codec\n")); 805 806 /* Reset codec */ 807 BA0WRITE4(sc, CS428X_ACCTL, 0); 808 delay(50); /* delay 50us */ 809 810 BA0WRITE4(sc, CS4281_SPMC, 0); 811 delay(100); /* delay 100us */ 812 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 813 #if defined(ENABLE_SECONDARY_CODEC) 814 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 815 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 816 #endif 817 delay(50000); /* XXX: delay 50ms */ 818 819 /* Enable ASYNC generation */ 820 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 821 822 /* Wait for codec ready. Linux driver waits 50ms here */ 823 n = 0; 824 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 825 delay(100); 826 if (++n > 1000) { 827 printf("reset_codec: AC97 codec ready timeout\n"); 828 return ETIMEDOUT; 829 } 830 } 831 #if defined(ENABLE_SECONDARY_CODEC) 832 /* secondary codec ready*/ 833 n = 0; 834 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 835 delay(100); 836 if (++n > 1000) 837 return 0; 838 } 839 #endif 840 /* Set the serial timing configuration */ 841 /* XXX: undocumented but the Linux driver do this */ 842 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 843 844 /* Wait for codec ready signal */ 845 n = 0; 846 do { 847 delay(1000); 848 if (++n > 1000) { 849 printf("%s: timeout waiting for codec ready\n", 850 sc->sc_dev.dv_xname); 851 return ETIMEDOUT; 852 } 853 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 854 } while (dat32 == 0); 855 856 /* Enable Valid Frame output on ASDOUT */ 857 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 858 859 /* Wait until codec calibration is finished. Codec register 26h */ 860 n = 0; 861 do { 862 delay(1); 863 if (++n > 1000) { 864 printf("%s: timeout waiting for codec calibration\n", 865 sc->sc_dev.dv_xname); 866 return ETIMEDOUT; 867 } 868 cs428x_read_codec(sc, AC97_REG_POWER, &data); 869 } while ((data & 0x0f) != 0x0f); 870 871 /* Set the serial timing configuration again */ 872 /* XXX: undocumented but the Linux driver do this */ 873 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 874 875 /* Wait until we've sampled input slots 3 & 4 as valid */ 876 n = 0; 877 do { 878 delay(1000); 879 if (++n > 1000) { 880 printf("%s: timeout waiting for sampled input slots as valid\n", 881 sc->sc_dev.dv_xname); 882 return ETIMEDOUT; 883 } 884 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 885 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 886 887 /* Start digital data transfer of audio data to the codec */ 888 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 889 return 0; 890 } 891 892 893 /* Internal functions */ 894 895 /* convert sample rate to register value */ 896 static uint8_t 897 cs4281_sr2regval(int rate) 898 { 899 uint8_t retval; 900 901 /* We don't have to change here. but anyway ... */ 902 if (rate > 48000) 903 rate = 48000; 904 if (rate < 6023) 905 rate = 6023; 906 907 switch (rate) { 908 case 8000: 909 retval = 5; 910 break; 911 case 11025: 912 retval = 4; 913 break; 914 case 16000: 915 retval = 3; 916 break; 917 case 22050: 918 retval = 2; 919 break; 920 case 44100: 921 retval = 1; 922 break; 923 case 48000: 924 retval = 0; 925 break; 926 default: 927 retval = 1536000/rate; /* == 24576000/(rate*16) */ 928 } 929 return retval; 930 } 931 932 static void 933 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 934 { 935 936 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 937 } 938 939 static void 940 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 941 { 942 943 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 944 } 945 946 static int 947 cs4281_init(struct cs428x_softc *sc, int init) 948 { 949 int n; 950 uint16_t data; 951 uint32_t dat32; 952 953 /* set "Configuration Write Protect" register to 954 * 0x4281 to allow to write */ 955 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 956 957 /* 958 * Unset "Full Power-Down bit of Extended PCI Power Management 959 * Control" register to release the reset state. 960 */ 961 dat32 = BA0READ4(sc, CS4281_EPPMC); 962 if (dat32 & EPPMC_FPDN) { 963 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 964 } 965 966 /* Start PLL out in known state */ 967 BA0WRITE4(sc, CS4281_CLKCR1, 0); 968 /* Start serial ports out in known state */ 969 BA0WRITE4(sc, CS4281_SERMC, 0); 970 971 /* Reset codec */ 972 BA0WRITE4(sc, CS428X_ACCTL, 0); 973 delay(50); /* delay 50us */ 974 975 BA0WRITE4(sc, CS4281_SPMC, 0); 976 delay(100); /* delay 100us */ 977 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 978 #if defined(ENABLE_SECONDARY_CODEC) 979 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 980 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 981 #endif 982 delay(50000); /* XXX: delay 50ms */ 983 984 /* Turn on Sound System clocks based on ABITCLK */ 985 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 986 delay(50000); /* XXX: delay 50ms */ 987 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 988 989 /* Set enables for sections that are needed in the SSPM registers */ 990 BA0WRITE4(sc, CS4281_SSPM, 991 SSPM_MIXEN | /* Mixer */ 992 SSPM_CSRCEN | /* Capture SRC */ 993 SSPM_PSRCEN | /* Playback SRC */ 994 SSPM_JSEN | /* Joystick */ 995 SSPM_ACLEN | /* AC LINK */ 996 SSPM_FMEN /* FM */ 997 ); 998 999 /* Wait for clock stabilization */ 1000 n = 0; 1001 #if 1 1002 /* what document says */ 1003 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1004 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1005 delay(100); 1006 if (++n > 1000) { 1007 printf("%s: timeout waiting for clock stabilization\n", 1008 sc->sc_dev.dv_xname); 1009 return -1; 1010 } 1011 } 1012 #else 1013 /* Cirrus driver for Linux does */ 1014 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1015 delay(1000); 1016 if (++n > 1000) { 1017 printf("%s: timeout waiting for clock stabilization\n", 1018 sc->sc_dev.dv_xname); 1019 return -1; 1020 } 1021 } 1022 #endif 1023 1024 /* Enable ASYNC generation */ 1025 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1026 1027 /* Wait for codec ready. Linux driver waits 50ms here */ 1028 n = 0; 1029 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1030 delay(100); 1031 if (++n > 1000) { 1032 printf("%s: timeout waiting for codec ready\n", 1033 sc->sc_dev.dv_xname); 1034 return -1; 1035 } 1036 } 1037 1038 #if defined(ENABLE_SECONDARY_CODEC) 1039 /* secondary codec ready*/ 1040 n = 0; 1041 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1042 delay(100); 1043 if (++n > 1000) { 1044 printf("%s: timeout waiting for secondary codec ready\n", 1045 sc->sc_dev.dv_xname); 1046 return -1; 1047 } 1048 } 1049 #endif 1050 1051 /* Set the serial timing configuration */ 1052 /* XXX: undocumented but the Linux driver do this */ 1053 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1054 1055 /* Wait for codec ready signal */ 1056 n = 0; 1057 do { 1058 delay(1000); 1059 if (++n > 1000) { 1060 printf("%s: timeout waiting for codec ready\n", 1061 sc->sc_dev.dv_xname); 1062 return -1; 1063 } 1064 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1065 } while (dat32 == 0); 1066 1067 /* Enable Valid Frame output on ASDOUT */ 1068 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1069 1070 /* Wait until codec calibration is finished. codec register 26h */ 1071 n = 0; 1072 do { 1073 delay(1); 1074 if (++n > 1000) { 1075 printf("%s: timeout waiting for codec calibration\n", 1076 sc->sc_dev.dv_xname); 1077 return -1; 1078 } 1079 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1080 } while ((data & 0x0f) != 0x0f); 1081 1082 /* Set the serial timing configuration again */ 1083 /* XXX: undocumented but the Linux driver do this */ 1084 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1085 1086 /* Wait until we've sampled input slots 3 & 4 as valid */ 1087 n = 0; 1088 do { 1089 delay(1000); 1090 if (++n > 1000) { 1091 printf("%s: timeout waiting for sampled input slots as valid\n", 1092 sc->sc_dev.dv_xname); 1093 return -1; 1094 } 1095 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1096 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1097 1098 /* Start digital data transfer of audio data to the codec */ 1099 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1100 1101 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1102 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1103 1104 /* Power on the DAC */ 1105 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1106 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1107 1108 /* Wait until we sample a DAC ready state. 1109 * Not documented, but Linux driver does. 1110 */ 1111 for (n = 0; n < 32; ++n) { 1112 delay(1000); 1113 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1114 if (data & 0x02) 1115 break; 1116 } 1117 1118 /* Power on the ADC */ 1119 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1120 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1121 1122 /* Wait until we sample ADC ready state. 1123 * Not documented, but Linux driver does. 1124 */ 1125 for (n = 0; n < 32; ++n) { 1126 delay(1000); 1127 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1128 if (data & 0x01) 1129 break; 1130 } 1131 1132 #if 0 1133 /* Initialize AC-Link features */ 1134 /* variable sample-rate support */ 1135 mem = BA0READ4(sc, CS4281_SERMC); 1136 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1137 BA0WRITE4(sc, CS4281_SERMC, mem); 1138 /* XXX: more... */ 1139 1140 /* Initialize SSCR register features */ 1141 /* XXX: hardware volume setting */ 1142 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1143 #endif 1144 1145 /* disable Sound Blaster Pro emulation */ 1146 /* XXX: 1147 * Cannot set since the documents does not describe which bit is 1148 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1149 * we can ignore it.*/ 1150 #if 0 1151 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1152 #endif 1153 1154 /* map AC97 PCM playback to DMA Channel 0 */ 1155 /* Reset FEN bit to setup first */ 1156 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1157 /* 1158 *| RS[4:0]/| | 1159 *| LS[4:0] | AC97 | Slot Function 1160 *|---------+--------+-------------------- 1161 *| 0 | 3 | Left PCM Playback 1162 *| 1 | 4 | Right PCM Playback 1163 *| 2 | 5 | Phone Line 1 DAC 1164 *| 3 | 6 | Center PCM Playback 1165 *.... 1166 * quoted from Table 29(p109) 1167 */ 1168 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1169 0x00 << 16 | /* LS[4:0] = 0 see above */ 1170 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1171 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1172 BA0WRITE4(sc, CS4281_FCR0, dat32); 1173 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1174 1175 /* map AC97 PCM record to DMA Channel 1 */ 1176 /* Reset FEN bit to setup first */ 1177 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1178 /* 1179 *| RS[4:0]/| 1180 *| LS[4:0] | AC97 | Slot Function 1181 *|---------+------+------------------- 1182 *| 10 | 3 | Left PCM Record 1183 *| 11 | 4 | Right PCM Record 1184 *| 12 | 5 | Phone Line 1 ADC 1185 *| 13 | 6 | Mic ADC 1186 *.... 1187 * quoted from Table 30(p109) 1188 */ 1189 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1190 0x0a << 16 | /* LS[4:0] = 10 See above */ 1191 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1192 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1193 1194 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1195 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1196 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1197 1198 #if 0 1199 /* Disable DMA Channel 2, 3 */ 1200 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1201 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1202 #endif 1203 1204 /* Set the SRC Slot Assignment accordingly */ 1205 /*| PLSS[4:0]/ 1206 *| PRSS[4:0] | AC97 | Slot Function 1207 *|-----------+------+---------------- 1208 *| 0 | 3 | Left PCM Playback 1209 *| 1 | 4 | Right PCM Playback 1210 *| 2 | 5 | phone line 1 DAC 1211 *| 3 | 6 | Center PCM Playback 1212 *| 4 | 7 | Left Surround PCM Playback 1213 *| 5 | 8 | Right Surround PCM Playback 1214 *...... 1215 * 1216 *| CLSS[4:0]/ 1217 *| CRSS[4:0] | AC97 | Codec |Slot Function 1218 *|-----------+------+-------+----------------- 1219 *| 10 | 3 |Primary| Left PCM Record 1220 *| 11 | 4 |Primary| Right PCM Record 1221 *| 12 | 5 |Primary| Phone Line 1 ADC 1222 *| 13 | 6 |Primary| Mic ADC 1223 *|..... 1224 *| 20 | 3 | Sec. | Left PCM Record 1225 *| 21 | 4 | Sec. | Right PCM Record 1226 *| 22 | 5 | Sec. | Phone Line 1 ADC 1227 *| 23 | 6 | Sec. | Mic ADC 1228 */ 1229 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1230 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1231 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1232 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1233 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1234 1235 /* Set interrupt to occurred at Half and Full terminal 1236 * count interrupt enable for DMA channel 0 and 1. 1237 * To keep DMA stop, set MSK. 1238 */ 1239 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1240 BA0WRITE4(sc, CS4281_DCR0, dat32); 1241 BA0WRITE4(sc, CS4281_DCR1, dat32); 1242 1243 /* Set Auto-Initialize Contorl enable */ 1244 BA0WRITE4(sc, CS4281_DMR0, 1245 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1246 BA0WRITE4(sc, CS4281_DMR1, 1247 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1248 1249 /* Clear DMA Mask in HIMR */ 1250 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1251 BA0WRITE4(sc, CS4281_HIMR, 1252 BA0READ4(sc, CS4281_HIMR) & dat32); 1253 1254 /* set current status */ 1255 if (init != 0) { 1256 sc->sc_prun = 0; 1257 sc->sc_rrun = 0; 1258 } 1259 1260 /* setup playback volume */ 1261 BA0WRITE4(sc, CS4281_PPRVC, 7); 1262 BA0WRITE4(sc, CS4281_PPLVC, 7); 1263 1264 return 0; 1265 } 1266
Indexes created Tue Sep 30 20:09:53 GMT 2025