cs4281.c revision 1.34.6.1
1 /* $NetBSD: cs4281.c,v 1.34.6.1 2007/10/04 19:53:09 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.34.6.1 2007/10/04 19:53:09 joerg Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(struct device *, struct cfdata *, void *); 84 static void cs4281_attach(struct device *, struct device *, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static void cs4281_suspend(device_t); 110 static void cs4281_resume(device_t); 111 112 static const struct audio_hw_if cs4281_hw_if = { 113 NULL, /* open */ 114 NULL, /* close */ 115 NULL, 116 cs4281_query_encoding, 117 cs4281_set_params, 118 cs428x_round_blocksize, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 NULL, 124 cs4281_halt_output, 125 cs4281_halt_input, 126 NULL, 127 cs4281_getdev, 128 NULL, 129 cs428x_mixer_set_port, 130 cs428x_mixer_get_port, 131 cs428x_query_devinfo, 132 cs428x_malloc, 133 cs428x_free, 134 cs428x_round_buffersize, 135 cs428x_mappage, 136 cs428x_get_props, 137 cs4281_trigger_output, 138 cs4281_trigger_input, 139 NULL, 140 NULL, 141 }; 142 143 #if NMIDI > 0 && 0 144 /* Midi Interface */ 145 static void cs4281_midi_close(void*); 146 static void cs4281_midi_getinfo(void *, struct midi_info *); 147 static int cs4281_midi_open(void *, int, void (*)(void *, int), 148 void (*)(void *), void *); 149 static int cs4281_midi_output(void *, int); 150 151 static const struct midi_hw_if cs4281_midi_hw_if = { 152 cs4281_midi_open, 153 cs4281_midi_close, 154 cs4281_midi_output, 155 cs4281_midi_getinfo, 156 0, 157 }; 158 #endif 159 160 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 161 cs4281_match, cs4281_attach, NULL, NULL); 162 163 static struct audio_device cs4281_device = { 164 "CS4281", 165 "", 166 "cs4281" 167 }; 168 169 170 static int 171 cs4281_match(struct device *parent, struct cfdata *match, 172 void *aux) 173 { 174 struct pci_attach_args *pa; 175 176 pa = (struct pci_attach_args *)aux; 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 178 return 0; 179 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 180 return 1; 181 return 0; 182 } 183 184 static void 185 cs4281_attach(struct device *parent, struct device *self, void *aux) 186 { 187 struct cs428x_softc *sc; 188 struct pci_attach_args *pa; 189 pci_chipset_tag_t pc; 190 char const *intrstr; 191 pcireg_t reg; 192 char devinfo[256]; 193 int error; 194 pnp_status_t pnp_status; 195 196 sc = (struct cs428x_softc *)self; 197 pa = (struct pci_attach_args *)aux; 198 pc = pa->pa_pc; 199 aprint_naive(": Audio controller\n"); 200 201 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 202 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 203 PCI_REVISION(pa->pa_class)); 204 205 sc->sc_pc = pa->pa_pc; 206 sc->sc_pt = pa->pa_tag; 207 208 /* Map I/O register */ 209 if (pci_mapreg_map(pa, PCI_BA0, 210 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 211 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 212 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 213 return; 214 } 215 if (pci_mapreg_map(pa, PCI_BA1, 216 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 217 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 218 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 219 return; 220 } 221 222 sc->sc_dmatag = pa->pa_dmat; 223 224 /* power up chip */ 225 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 226 pci_activate_null)) && error != EOPNOTSUPP) { 227 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 228 error); 229 return; 230 } 231 232 /* Enable the device (set bus master flag) */ 233 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 234 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 235 reg | PCI_COMMAND_MASTER_ENABLE); 236 237 #if 0 238 /* LATENCY_TIMER setting */ 239 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 240 if (PCI_LATTIMER(temp1) < 32) { 241 temp1 &= 0xffff00ff; 242 temp1 |= 0x00002000; 243 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 244 } 245 #endif 246 247 /* Map and establish the interrupt. */ 248 if (pci_intr_map(pa, &sc->intrh)) { 249 aprint_error("%s: couldn't map interrupt\n", 250 sc->sc_dev.dv_xname); 251 return; 252 } 253 intrstr = pci_intr_string(pc, sc->intrh); 254 255 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 256 cs4281_intr, sc); 257 if (sc->sc_ih == NULL) { 258 aprint_error("%s: couldn't establish interrupt", 259 sc->sc_dev.dv_xname); 260 if (intrstr != NULL) 261 aprint_normal(" at %s", intrstr); 262 aprint_normal("\n"); 263 return; 264 } 265 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 266 267 /* 268 * Sound System start-up 269 */ 270 if (cs4281_init(sc, 1) != 0) 271 return; 272 273 sc->type = TYPE_CS4281; 274 sc->halt_input = cs4281_halt_input; 275 sc->halt_output = cs4281_halt_output; 276 277 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 278 sc->dma_align = 0x10; 279 sc->hw_blocksize = sc->dma_size / 2; 280 281 /* AC 97 attachment */ 282 sc->host_if.arg = sc; 283 sc->host_if.attach = cs428x_attach_codec; 284 sc->host_if.read = cs428x_read_codec; 285 sc->host_if.write = cs428x_write_codec; 286 sc->host_if.reset = cs4281_reset_codec; 287 if (ac97_attach(&sc->host_if, self) != 0) { 288 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 289 return; 290 } 291 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 292 293 #if NMIDI > 0 && 0 294 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 295 #endif 296 297 pnp_status = pci_generic_power_register(self, pa->pa_pc, pa->pa_tag, 298 cs4281_suspend, cs4281_resume); 299 if (pnp_status != PNP_STATUS_SUCCESS) { 300 aprint_error("%s: couldn't establish power handler\n", 301 device_xname(self)); 302 } 303 } 304 305 static int 306 cs4281_intr(void *p) 307 { 308 struct cs428x_softc *sc; 309 uint32_t intr, hdsr0, hdsr1; 310 char *empty_dma; 311 int handled; 312 313 sc = p; 314 handled = 0; 315 hdsr0 = 0; 316 hdsr1 = 0; 317 318 /* grab interrupt register */ 319 intr = BA0READ4(sc, CS4281_HISR); 320 321 DPRINTF(("cs4281_intr:")); 322 /* not for me */ 323 if ((intr & HISR_INTENA) == 0) { 324 /* clear the interrupt register */ 325 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 326 return 0; 327 } 328 329 if (intr & HISR_DMA0) 330 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 331 if (intr & HISR_DMA1) 332 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 333 /* clear the interrupt register */ 334 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 335 336 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 337 intr, hdsr0, hdsr1)); 338 339 /* Playback Interrupt */ 340 if (intr & HISR_DMA0) { 341 handled = 1; 342 if (sc->sc_prun) { 343 DPRINTF((" PB DMA 0x%x(%d)", 344 (int)BA0READ4(sc, CS4281_DCA0), 345 (int)BA0READ4(sc, CS4281_DCC0))); 346 if ((sc->sc_pi%sc->sc_pcount) == 0) 347 sc->sc_pintr(sc->sc_parg); 348 /* copy buffer */ 349 ++sc->sc_pi; 350 empty_dma = sc->sc_pdma->addr; 351 if (sc->sc_pi&1) 352 empty_dma += sc->hw_blocksize; 353 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 354 sc->sc_pn += sc->hw_blocksize; 355 if (sc->sc_pn >= sc->sc_pe) 356 sc->sc_pn = sc->sc_ps; 357 } else { 358 printf("%s: unexpected play intr\n", 359 sc->sc_dev.dv_xname); 360 } 361 } 362 if (intr & HISR_DMA1) { 363 handled = 1; 364 if (sc->sc_rrun) { 365 /* copy from DMA */ 366 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 367 (int)BA0READ4(sc, CS4281_DCC1))); 368 ++sc->sc_ri; 369 empty_dma = sc->sc_rdma->addr; 370 if ((sc->sc_ri & 1) == 0) 371 empty_dma += sc->hw_blocksize; 372 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 373 sc->sc_rn += sc->hw_blocksize; 374 if (sc->sc_rn >= sc->sc_re) 375 sc->sc_rn = sc->sc_rs; 376 if ((sc->sc_ri % sc->sc_rcount) == 0) 377 sc->sc_rintr(sc->sc_rarg); 378 } else { 379 printf("%s: unexpected record intr\n", 380 sc->sc_dev.dv_xname); 381 } 382 } 383 DPRINTF(("\n")); 384 385 return handled; 386 } 387 388 static int 389 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 390 { 391 392 switch (fp->index) { 393 case 0: 394 strcpy(fp->name, AudioEulinear); 395 fp->encoding = AUDIO_ENCODING_ULINEAR; 396 fp->precision = 8; 397 fp->flags = 0; 398 break; 399 case 1: 400 strcpy(fp->name, AudioEmulaw); 401 fp->encoding = AUDIO_ENCODING_ULAW; 402 fp->precision = 8; 403 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 404 break; 405 case 2: 406 strcpy(fp->name, AudioEalaw); 407 fp->encoding = AUDIO_ENCODING_ALAW; 408 fp->precision = 8; 409 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 410 break; 411 case 3: 412 strcpy(fp->name, AudioEslinear); 413 fp->encoding = AUDIO_ENCODING_SLINEAR; 414 fp->precision = 8; 415 fp->flags = 0; 416 break; 417 case 4: 418 strcpy(fp->name, AudioEslinear_le); 419 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 420 fp->precision = 16; 421 fp->flags = 0; 422 break; 423 case 5: 424 strcpy(fp->name, AudioEulinear_le); 425 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 426 fp->precision = 16; 427 fp->flags = 0; 428 break; 429 case 6: 430 strcpy(fp->name, AudioEslinear_be); 431 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 432 fp->precision = 16; 433 fp->flags = 0; 434 break; 435 case 7: 436 strcpy(fp->name, AudioEulinear_be); 437 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 438 fp->precision = 16; 439 fp->flags = 0; 440 break; 441 default: 442 return EINVAL; 443 } 444 return 0; 445 } 446 447 static int 448 cs4281_set_params(void *addr, int setmode, int usemode, 449 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 450 stream_filter_list_t *rfil) 451 { 452 audio_params_t hw; 453 struct cs428x_softc *sc; 454 audio_params_t *p; 455 stream_filter_list_t *fil; 456 int mode; 457 458 sc = addr; 459 for (mode = AUMODE_RECORD; mode != -1; 460 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 461 if ((setmode & mode) == 0) 462 continue; 463 464 p = mode == AUMODE_PLAY ? play : rec; 465 466 if (p == play) { 467 DPRINTFN(5, 468 ("play: sample=%u precision=%u channels=%u\n", 469 p->sample_rate, p->precision, p->channels)); 470 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 471 (p->precision != 8 && p->precision != 16) || 472 (p->channels != 1 && p->channels != 2)) { 473 return EINVAL; 474 } 475 } else { 476 DPRINTFN(5, 477 ("rec: sample=%u precision=%u channels=%u\n", 478 p->sample_rate, p->precision, p->channels)); 479 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 480 (p->precision != 8 && p->precision != 16) || 481 (p->channels != 1 && p->channels != 2)) { 482 return EINVAL; 483 } 484 } 485 hw = *p; 486 fil = mode == AUMODE_PLAY ? pfil : rfil; 487 488 switch (p->encoding) { 489 case AUDIO_ENCODING_SLINEAR_BE: 490 break; 491 case AUDIO_ENCODING_SLINEAR_LE: 492 break; 493 case AUDIO_ENCODING_ULINEAR_BE: 494 break; 495 case AUDIO_ENCODING_ULINEAR_LE: 496 break; 497 case AUDIO_ENCODING_ULAW: 498 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 499 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 500 : linear8_to_mulaw, &hw); 501 break; 502 case AUDIO_ENCODING_ALAW: 503 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 504 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 505 : linear8_to_alaw, &hw); 506 break; 507 default: 508 return EINVAL; 509 } 510 } 511 512 /* set sample rate */ 513 cs4281_set_dac_rate(sc, play->sample_rate); 514 cs4281_set_adc_rate(sc, rec->sample_rate); 515 return 0; 516 } 517 518 static int 519 cs4281_halt_output(void *addr) 520 { 521 struct cs428x_softc *sc; 522 523 sc = addr; 524 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 525 sc->sc_prun = 0; 526 return 0; 527 } 528 529 static int 530 cs4281_halt_input(void *addr) 531 { 532 struct cs428x_softc *sc; 533 534 sc = addr; 535 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 536 sc->sc_rrun = 0; 537 return 0; 538 } 539 540 static int 541 cs4281_getdev(void *addr, struct audio_device *retp) 542 { 543 544 *retp = cs4281_device; 545 return 0; 546 } 547 548 static int 549 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 550 void (*intr)(void *), void *arg, 551 const audio_params_t *param) 552 { 553 struct cs428x_softc *sc; 554 uint32_t fmt; 555 struct cs428x_dma *p; 556 int dma_count; 557 558 sc = addr; 559 fmt = 0; 560 #ifdef DIAGNOSTIC 561 if (sc->sc_prun) 562 printf("cs4281_trigger_output: already running\n"); 563 #endif 564 sc->sc_prun = 1; 565 566 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 567 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 568 sc->sc_pintr = intr; 569 sc->sc_parg = arg; 570 571 /* stop playback DMA */ 572 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 573 574 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 575 param->precision, param->channels, param->encoding)); 576 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 577 continue; 578 if (p == NULL) { 579 printf("cs4281_trigger_output: bad addr %p\n", start); 580 return EINVAL; 581 } 582 583 sc->sc_pcount = blksize / sc->hw_blocksize; 584 sc->sc_ps = (char *)start; 585 sc->sc_pe = (char *)end; 586 sc->sc_pdma = p; 587 sc->sc_pbuf = KERNADDR(p); 588 sc->sc_pi = 0; 589 sc->sc_pn = sc->sc_ps; 590 if (blksize >= sc->dma_size) { 591 sc->sc_pn = sc->sc_ps + sc->dma_size; 592 memcpy(sc->sc_pbuf, start, sc->dma_size); 593 ++sc->sc_pi; 594 } else { 595 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 596 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 597 } 598 599 dma_count = sc->dma_size; 600 if (param->precision != 8) 601 dma_count /= 2; /* 16 bit */ 602 if (param->channels > 1) 603 dma_count /= 2; /* Stereo */ 604 605 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 606 (int)DMAADDR(p), dma_count)); 607 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 608 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 609 610 /* set playback format */ 611 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 612 if (param->precision == 8) 613 fmt |= DMRn_SIZE8; 614 if (param->channels == 1) 615 fmt |= DMRn_MONO; 616 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 617 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 618 fmt |= DMRn_BEND; 619 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 620 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 621 fmt |= DMRn_USIGN; 622 BA0WRITE4(sc, CS4281_DMR0, fmt); 623 624 /* set sample rate */ 625 sc->sc_prate = param->sample_rate; 626 cs4281_set_dac_rate(sc, param->sample_rate); 627 628 /* start DMA */ 629 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 630 /* Enable interrupts */ 631 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 632 633 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 634 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 635 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 636 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 637 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 638 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 639 BA0READ4(sc, CS4281_DACSR))); 640 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 641 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 642 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 643 644 return 0; 645 } 646 647 static int 648 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 649 void (*intr)(void *), void *arg, 650 const audio_params_t *param) 651 { 652 struct cs428x_softc *sc; 653 struct cs428x_dma *p; 654 uint32_t fmt; 655 int dma_count; 656 657 sc = addr; 658 fmt = 0; 659 #ifdef DIAGNOSTIC 660 if (sc->sc_rrun) 661 printf("cs4281_trigger_input: already running\n"); 662 #endif 663 sc->sc_rrun = 1; 664 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 665 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 666 sc->sc_rintr = intr; 667 sc->sc_rarg = arg; 668 669 /* stop recording DMA */ 670 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 671 672 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 673 continue; 674 if (!p) { 675 printf("cs4281_trigger_input: bad addr %p\n", start); 676 return EINVAL; 677 } 678 679 sc->sc_rcount = blksize / sc->hw_blocksize; 680 sc->sc_rs = (char *)start; 681 sc->sc_re = (char *)end; 682 sc->sc_rdma = p; 683 sc->sc_rbuf = KERNADDR(p); 684 sc->sc_ri = 0; 685 sc->sc_rn = sc->sc_rs; 686 687 dma_count = sc->dma_size; 688 if (param->precision != 8) 689 dma_count /= 2; 690 if (param->channels > 1) 691 dma_count /= 2; 692 693 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 694 (int)DMAADDR(p), dma_count)); 695 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 696 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 697 698 /* set recording format */ 699 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 700 if (param->precision == 8) 701 fmt |= DMRn_SIZE8; 702 if (param->channels == 1) 703 fmt |= DMRn_MONO; 704 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 705 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 706 fmt |= DMRn_BEND; 707 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 708 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 709 fmt |= DMRn_USIGN; 710 BA0WRITE4(sc, CS4281_DMR1, fmt); 711 712 /* set sample rate */ 713 sc->sc_rrate = param->sample_rate; 714 cs4281_set_adc_rate(sc, param->sample_rate); 715 716 /* Start DMA */ 717 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 718 /* Enable interrupts */ 719 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 720 721 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 722 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 723 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 724 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 725 726 return 0; 727 } 728 729 static void 730 cs4281_suspend(device_t dv) 731 { 732 struct cs428x_softc *sc = device_private(dv); 733 734 /* save current playback status */ 735 if (sc->sc_prun) { 736 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 737 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 738 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 739 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 740 } 741 742 /* save current capture status */ 743 if (sc->sc_rrun) { 744 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 745 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 746 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 747 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 748 } 749 /* Stop DMA */ 750 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 751 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 752 } 753 754 static void 755 cs4281_resume(device_t dv) 756 { 757 struct cs428x_softc *sc = device_private(dv); 758 759 cs4281_init(sc, 0); 760 cs4281_reset_codec(sc); 761 762 /* restore ac97 registers */ 763 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 764 765 /* restore DMA related status */ 766 if (sc->sc_prun) { 767 cs4281_set_dac_rate(sc, sc->sc_prate); 768 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 769 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 770 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 771 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 772 } 773 if (sc->sc_rrun) { 774 cs4281_set_adc_rate(sc, sc->sc_rrate); 775 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 776 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 777 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 778 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 779 } 780 /* enable intterupts */ 781 if (sc->sc_prun || sc->sc_rrun) 782 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 783 } 784 785 /* control AC97 codec */ 786 static int 787 cs4281_reset_codec(void *addr) 788 { 789 struct cs428x_softc *sc; 790 uint16_t data; 791 uint32_t dat32; 792 int n; 793 794 sc = addr; 795 796 DPRINTFN(3, ("cs4281_reset_codec\n")); 797 798 /* Reset codec */ 799 BA0WRITE4(sc, CS428X_ACCTL, 0); 800 delay(50); /* delay 50us */ 801 802 BA0WRITE4(sc, CS4281_SPMC, 0); 803 delay(100); /* delay 100us */ 804 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 805 #if defined(ENABLE_SECONDARY_CODEC) 806 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 807 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 808 #endif 809 delay(50000); /* XXX: delay 50ms */ 810 811 /* Enable ASYNC generation */ 812 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 813 814 /* Wait for codec ready. Linux driver waits 50ms here */ 815 n = 0; 816 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 817 delay(100); 818 if (++n > 1000) { 819 printf("reset_codec: AC97 codec ready timeout\n"); 820 return ETIMEDOUT; 821 } 822 } 823 #if defined(ENABLE_SECONDARY_CODEC) 824 /* secondary codec ready*/ 825 n = 0; 826 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 827 delay(100); 828 if (++n > 1000) 829 return 0; 830 } 831 #endif 832 /* Set the serial timing configuration */ 833 /* XXX: undocumented but the Linux driver do this */ 834 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 835 836 /* Wait for codec ready signal */ 837 n = 0; 838 do { 839 delay(1000); 840 if (++n > 1000) { 841 printf("%s: timeout waiting for codec ready\n", 842 sc->sc_dev.dv_xname); 843 return ETIMEDOUT; 844 } 845 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 846 } while (dat32 == 0); 847 848 /* Enable Valid Frame output on ASDOUT */ 849 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 850 851 /* Wait until codec calibration is finished. Codec register 26h */ 852 n = 0; 853 do { 854 delay(1); 855 if (++n > 1000) { 856 printf("%s: timeout waiting for codec calibration\n", 857 sc->sc_dev.dv_xname); 858 return ETIMEDOUT; 859 } 860 cs428x_read_codec(sc, AC97_REG_POWER, &data); 861 } while ((data & 0x0f) != 0x0f); 862 863 /* Set the serial timing configuration again */ 864 /* XXX: undocumented but the Linux driver do this */ 865 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 866 867 /* Wait until we've sampled input slots 3 & 4 as valid */ 868 n = 0; 869 do { 870 delay(1000); 871 if (++n > 1000) { 872 printf("%s: timeout waiting for sampled input slots as valid\n", 873 sc->sc_dev.dv_xname); 874 return ETIMEDOUT; 875 } 876 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 877 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 878 879 /* Start digital data transfer of audio data to the codec */ 880 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 881 return 0; 882 } 883 884 885 /* Internal functions */ 886 887 /* convert sample rate to register value */ 888 static uint8_t 889 cs4281_sr2regval(int rate) 890 { 891 uint8_t retval; 892 893 /* We don't have to change here. but anyway ... */ 894 if (rate > 48000) 895 rate = 48000; 896 if (rate < 6023) 897 rate = 6023; 898 899 switch (rate) { 900 case 8000: 901 retval = 5; 902 break; 903 case 11025: 904 retval = 4; 905 break; 906 case 16000: 907 retval = 3; 908 break; 909 case 22050: 910 retval = 2; 911 break; 912 case 44100: 913 retval = 1; 914 break; 915 case 48000: 916 retval = 0; 917 break; 918 default: 919 retval = 1536000/rate; /* == 24576000/(rate*16) */ 920 } 921 return retval; 922 } 923 924 static void 925 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 926 { 927 928 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 929 } 930 931 static void 932 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 933 { 934 935 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 936 } 937 938 static int 939 cs4281_init(struct cs428x_softc *sc, int init) 940 { 941 int n; 942 uint16_t data; 943 uint32_t dat32; 944 945 /* set "Configuration Write Protect" register to 946 * 0x4281 to allow to write */ 947 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 948 949 /* 950 * Unset "Full Power-Down bit of Extended PCI Power Management 951 * Control" register to release the reset state. 952 */ 953 dat32 = BA0READ4(sc, CS4281_EPPMC); 954 if (dat32 & EPPMC_FPDN) { 955 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 956 } 957 958 /* Start PLL out in known state */ 959 BA0WRITE4(sc, CS4281_CLKCR1, 0); 960 /* Start serial ports out in known state */ 961 BA0WRITE4(sc, CS4281_SERMC, 0); 962 963 /* Reset codec */ 964 BA0WRITE4(sc, CS428X_ACCTL, 0); 965 delay(50); /* delay 50us */ 966 967 BA0WRITE4(sc, CS4281_SPMC, 0); 968 delay(100); /* delay 100us */ 969 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 970 #if defined(ENABLE_SECONDARY_CODEC) 971 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 972 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 973 #endif 974 delay(50000); /* XXX: delay 50ms */ 975 976 /* Turn on Sound System clocks based on ABITCLK */ 977 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 978 delay(50000); /* XXX: delay 50ms */ 979 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 980 981 /* Set enables for sections that are needed in the SSPM registers */ 982 BA0WRITE4(sc, CS4281_SSPM, 983 SSPM_MIXEN | /* Mixer */ 984 SSPM_CSRCEN | /* Capture SRC */ 985 SSPM_PSRCEN | /* Playback SRC */ 986 SSPM_JSEN | /* Joystick */ 987 SSPM_ACLEN | /* AC LINK */ 988 SSPM_FMEN /* FM */ 989 ); 990 991 /* Wait for clock stabilization */ 992 n = 0; 993 #if 1 994 /* what document says */ 995 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 996 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 997 delay(100); 998 if (++n > 1000) { 999 printf("%s: timeout waiting for clock stabilization\n", 1000 sc->sc_dev.dv_xname); 1001 return -1; 1002 } 1003 } 1004 #else 1005 /* Cirrus driver for Linux does */ 1006 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1007 delay(1000); 1008 if (++n > 1000) { 1009 printf("%s: timeout waiting for clock stabilization\n", 1010 sc->sc_dev.dv_xname); 1011 return -1; 1012 } 1013 } 1014 #endif 1015 1016 /* Enable ASYNC generation */ 1017 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1018 1019 /* Wait for codec ready. Linux driver waits 50ms here */ 1020 n = 0; 1021 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1022 delay(100); 1023 if (++n > 1000) { 1024 printf("%s: timeout waiting for codec ready\n", 1025 sc->sc_dev.dv_xname); 1026 return -1; 1027 } 1028 } 1029 1030 #if defined(ENABLE_SECONDARY_CODEC) 1031 /* secondary codec ready*/ 1032 n = 0; 1033 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1034 delay(100); 1035 if (++n > 1000) { 1036 printf("%s: timeout waiting for secondary codec ready\n", 1037 sc->sc_dev.dv_xname); 1038 return -1; 1039 } 1040 } 1041 #endif 1042 1043 /* Set the serial timing configuration */ 1044 /* XXX: undocumented but the Linux driver do this */ 1045 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1046 1047 /* Wait for codec ready signal */ 1048 n = 0; 1049 do { 1050 delay(1000); 1051 if (++n > 1000) { 1052 printf("%s: timeout waiting for codec ready\n", 1053 sc->sc_dev.dv_xname); 1054 return -1; 1055 } 1056 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1057 } while (dat32 == 0); 1058 1059 /* Enable Valid Frame output on ASDOUT */ 1060 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1061 1062 /* Wait until codec calibration is finished. codec register 26h */ 1063 n = 0; 1064 do { 1065 delay(1); 1066 if (++n > 1000) { 1067 printf("%s: timeout waiting for codec calibration\n", 1068 sc->sc_dev.dv_xname); 1069 return -1; 1070 } 1071 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1072 } while ((data & 0x0f) != 0x0f); 1073 1074 /* Set the serial timing configuration again */ 1075 /* XXX: undocumented but the Linux driver do this */ 1076 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1077 1078 /* Wait until we've sampled input slots 3 & 4 as valid */ 1079 n = 0; 1080 do { 1081 delay(1000); 1082 if (++n > 1000) { 1083 printf("%s: timeout waiting for sampled input slots as valid\n", 1084 sc->sc_dev.dv_xname); 1085 return -1; 1086 } 1087 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1088 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1089 1090 /* Start digital data transfer of audio data to the codec */ 1091 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1092 1093 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1094 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1095 1096 /* Power on the DAC */ 1097 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1098 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1099 1100 /* Wait until we sample a DAC ready state. 1101 * Not documented, but Linux driver does. 1102 */ 1103 for (n = 0; n < 32; ++n) { 1104 delay(1000); 1105 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1106 if (data & 0x02) 1107 break; 1108 } 1109 1110 /* Power on the ADC */ 1111 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1112 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1113 1114 /* Wait until we sample ADC ready state. 1115 * Not documented, but Linux driver does. 1116 */ 1117 for (n = 0; n < 32; ++n) { 1118 delay(1000); 1119 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1120 if (data & 0x01) 1121 break; 1122 } 1123 1124 #if 0 1125 /* Initialize AC-Link features */ 1126 /* variable sample-rate support */ 1127 mem = BA0READ4(sc, CS4281_SERMC); 1128 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1129 BA0WRITE4(sc, CS4281_SERMC, mem); 1130 /* XXX: more... */ 1131 1132 /* Initialize SSCR register features */ 1133 /* XXX: hardware volume setting */ 1134 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1135 #endif 1136 1137 /* disable Sound Blaster Pro emulation */ 1138 /* XXX: 1139 * Cannot set since the documents does not describe which bit is 1140 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1141 * we can ignore it.*/ 1142 #if 0 1143 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1144 #endif 1145 1146 /* map AC97 PCM playback to DMA Channel 0 */ 1147 /* Reset FEN bit to setup first */ 1148 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1149 /* 1150 *| RS[4:0]/| | 1151 *| LS[4:0] | AC97 | Slot Function 1152 *|---------+--------+-------------------- 1153 *| 0 | 3 | Left PCM Playback 1154 *| 1 | 4 | Right PCM Playback 1155 *| 2 | 5 | Phone Line 1 DAC 1156 *| 3 | 6 | Center PCM Playback 1157 *.... 1158 * quoted from Table 29(p109) 1159 */ 1160 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1161 0x00 << 16 | /* LS[4:0] = 0 see above */ 1162 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1163 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1164 BA0WRITE4(sc, CS4281_FCR0, dat32); 1165 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1166 1167 /* map AC97 PCM record to DMA Channel 1 */ 1168 /* Reset FEN bit to setup first */ 1169 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1170 /* 1171 *| RS[4:0]/| 1172 *| LS[4:0] | AC97 | Slot Function 1173 *|---------+------+------------------- 1174 *| 10 | 3 | Left PCM Record 1175 *| 11 | 4 | Right PCM Record 1176 *| 12 | 5 | Phone Line 1 ADC 1177 *| 13 | 6 | Mic ADC 1178 *.... 1179 * quoted from Table 30(p109) 1180 */ 1181 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1182 0x0a << 16 | /* LS[4:0] = 10 See above */ 1183 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1184 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1185 1186 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1187 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1188 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1189 1190 #if 0 1191 /* Disable DMA Channel 2, 3 */ 1192 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1193 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1194 #endif 1195 1196 /* Set the SRC Slot Assignment accordingly */ 1197 /*| PLSS[4:0]/ 1198 *| PRSS[4:0] | AC97 | Slot Function 1199 *|-----------+------+---------------- 1200 *| 0 | 3 | Left PCM Playback 1201 *| 1 | 4 | Right PCM Playback 1202 *| 2 | 5 | phone line 1 DAC 1203 *| 3 | 6 | Center PCM Playback 1204 *| 4 | 7 | Left Surround PCM Playback 1205 *| 5 | 8 | Right Surround PCM Playback 1206 *...... 1207 * 1208 *| CLSS[4:0]/ 1209 *| CRSS[4:0] | AC97 | Codec |Slot Function 1210 *|-----------+------+-------+----------------- 1211 *| 10 | 3 |Primary| Left PCM Record 1212 *| 11 | 4 |Primary| Right PCM Record 1213 *| 12 | 5 |Primary| Phone Line 1 ADC 1214 *| 13 | 6 |Primary| Mic ADC 1215 *|..... 1216 *| 20 | 3 | Sec. | Left PCM Record 1217 *| 21 | 4 | Sec. | Right PCM Record 1218 *| 22 | 5 | Sec. | Phone Line 1 ADC 1219 *| 23 | 6 | Sec. | Mic ADC 1220 */ 1221 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1222 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1223 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1224 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1225 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1226 1227 /* Set interrupt to occurred at Half and Full terminal 1228 * count interrupt enable for DMA channel 0 and 1. 1229 * To keep DMA stop, set MSK. 1230 */ 1231 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1232 BA0WRITE4(sc, CS4281_DCR0, dat32); 1233 BA0WRITE4(sc, CS4281_DCR1, dat32); 1234 1235 /* Set Auto-Initialize Contorl enable */ 1236 BA0WRITE4(sc, CS4281_DMR0, 1237 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1238 BA0WRITE4(sc, CS4281_DMR1, 1239 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1240 1241 /* Clear DMA Mask in HIMR */ 1242 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1243 BA0WRITE4(sc, CS4281_HIMR, 1244 BA0READ4(sc, CS4281_HIMR) & dat32); 1245 1246 /* set current status */ 1247 if (init != 0) { 1248 sc->sc_prun = 0; 1249 sc->sc_rrun = 0; 1250 } 1251 1252 /* setup playback volume */ 1253 BA0WRITE4(sc, CS4281_PPRVC, 7); 1254 BA0WRITE4(sc, CS4281_PPLVC, 7); 1255 1256 return 0; 1257 } 1258
Indexes created Thu Oct 02 07:10:07 GMT 2025