cs4281.c revision 1.4.2.4
1 /* $NetBSD: cs4281.c,v 1.4.2.4 2001/12/27 11:56:54 he Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/malloc.h> 49 #include <sys/fcntl.h> 50 #include <sys/device.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 54 #include <dev/pci/pcidevs.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/cs4281reg.h> 57 #include <dev/pci/cs428xreg.h> 58 59 #include <sys/audioio.h> 60 #include <dev/audio_if.h> 61 #include <dev/midi_if.h> 62 #include <dev/mulaw.h> 63 #include <dev/auconv.h> 64 65 #include <dev/ic/ac97reg.h> 66 #include <dev/ic/ac97var.h> 67 68 #include <dev/pci/cs428x.h> 69 70 #include <machine/bus.h> 71 72 #if defined(ENABLE_SECONDARY_CODEC) 73 #define MAX_CHANNELS (4) 74 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 75 #else 76 #define MAX_CHANNELS (2) 77 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 78 #endif 79 80 /* IF functions for audio driver */ 81 int cs4281_match(struct device *, struct cfdata *, void *); 82 void cs4281_attach(struct device *, struct device *, void *); 83 int cs4281_intr(void *); 84 int cs4281_query_encoding(void *, struct audio_encoding *); 85 int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 86 int cs4281_halt_output(void *); 87 int cs4281_halt_input(void *); 88 int cs4281_getdev(void *, struct audio_device *); 89 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 90 void *, struct audio_params *); 91 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 92 void *, struct audio_params *); 93 94 void cs4281_reset_codec(void *); 95 96 /* Internal functions */ 97 u_int8_t cs4281_sr2regval(int); 98 void cs4281_set_dac_rate(struct cs428x_softc *, int); 99 void cs4281_set_adc_rate(struct cs428x_softc *, int); 100 int cs4281_init(struct cs428x_softc *, int); 101 102 /* Power Management */ 103 void cs4281_power(int, void *); 104 105 struct audio_hw_if cs4281_hw_if = { 106 cs428x_open, 107 cs428x_close, 108 NULL, 109 cs4281_query_encoding, 110 cs4281_set_params, 111 cs428x_round_blocksize, 112 NULL, 113 NULL, 114 NULL, 115 NULL, 116 NULL, 117 cs4281_halt_output, 118 cs4281_halt_input, 119 NULL, 120 cs4281_getdev, 121 NULL, 122 cs428x_mixer_set_port, 123 cs428x_mixer_get_port, 124 cs428x_query_devinfo, 125 cs428x_malloc, 126 cs428x_free, 127 cs428x_round_buffersize, 128 cs428x_mappage, 129 cs428x_get_props, 130 cs4281_trigger_output, 131 cs4281_trigger_input, 132 }; 133 134 #if NMIDI > 0 && 0 135 /* Midi Interface */ 136 void cs4281_midi_close(void*); 137 void cs4281_midi_getinfo(void *, struct midi_info *); 138 int cs4281_midi_open(void *, int, void (*)(void *, int), 139 void (*)(void *), void *); 140 int cs4281_midi_output(void *, int); 141 142 struct midi_hw_if cs4281_midi_hw_if = { 143 cs4281_midi_open, 144 cs4281_midi_close, 145 cs4281_midi_output, 146 cs4281_midi_getinfo, 147 0, 148 }; 149 #endif 150 151 struct cfattach clct_ca = { 152 sizeof(struct cs428x_softc), cs4281_match, cs4281_attach 153 }; 154 155 struct audio_device cs4281_device = { 156 "CS4281", 157 "", 158 "cs4281" 159 }; 160 161 162 int 163 cs4281_match(parent, match, aux) 164 struct device *parent; 165 struct cfdata *match; 166 void *aux; 167 { 168 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 169 170 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 171 return 0; 172 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 173 return 1; 174 return 0; 175 } 176 177 void 178 cs4281_attach(parent, self, aux) 179 struct device *parent; 180 struct device *self; 181 void *aux; 182 { 183 struct cs428x_softc *sc = (struct cs428x_softc *)self; 184 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 185 pci_chipset_tag_t pc = pa->pa_pc; 186 char const *intrstr; 187 pci_intr_handle_t ih; 188 pcireg_t reg; 189 char devinfo[256]; 190 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 191 192 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 193 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 194 195 /* Map I/O register */ 196 if (pci_mapreg_map(pa, PCI_BA0, 197 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 198 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 199 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 200 return; 201 } 202 if (pci_mapreg_map(pa, PCI_BA1, 203 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 204 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 205 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 206 return; 207 } 208 209 sc->sc_dmatag = pa->pa_dmat; 210 211 /* 212 * Set Power State D0. 213 * Without do this, 0xffffffff is read from all registers after 214 * using Windows. 215 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 216 */ 217 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 218 &pci_pwrmgmt_cap_reg, 0)) { 219 220 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 221 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 222 pci_pwrmgmt_csr_reg); 223 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 224 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 225 (reg & ~PCI_PMCSR_STATE_MASK) | 226 PCI_PMCSR_STATE_D0); 227 } 228 } 229 230 /* Enable the device (set bus master flag) */ 231 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 233 reg | PCI_COMMAND_MASTER_ENABLE); 234 235 #if 0 236 /* LATENCY_TIMER setting */ 237 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 238 if ( PCI_LATTIMER(temp1) < 32 ) { 239 temp1 &= 0xffff00ff; 240 temp1 |= 0x00002000; 241 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 242 } 243 #endif 244 245 /* Map and establish the interrupt. */ 246 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 247 pa->pa_intrline, &ih)) { 248 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 249 return; 250 } 251 intrstr = pci_intr_string(pc, ih); 252 253 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 254 if (sc->sc_ih == NULL) { 255 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 256 if (intrstr != NULL) 257 printf(" at %s", intrstr); 258 printf("\n"); 259 return; 260 } 261 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 262 263 /* 264 * Sound System start-up 265 */ 266 if (cs4281_init(sc,1) != 0) 267 return; 268 269 sc->type = TYPE_CS4281; 270 sc->halt_input = cs4281_halt_input; 271 sc->halt_output = cs4281_halt_output; 272 273 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 274 sc->dma_align = 0x10; 275 sc->hw_blocksize = sc->dma_size / 2; 276 277 /* AC 97 attachment */ 278 sc->host_if.arg = sc; 279 sc->host_if.attach = cs428x_attach_codec; 280 sc->host_if.read = cs428x_read_codec; 281 sc->host_if.write = cs428x_write_codec; 282 sc->host_if.reset = cs4281_reset_codec; 283 if (ac97_attach(&sc->host_if) != 0) { 284 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 285 return; 286 } 287 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 288 289 #if NMIDI > 0 && 0 290 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 291 #endif 292 293 sc->sc_suspend = PWR_RESUME; 294 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 295 } 296 297 int 298 cs4281_intr(p) 299 void *p; 300 { 301 struct cs428x_softc *sc = p; 302 u_int32_t intr, hdsr0, hdsr1; 303 char *empty_dma; 304 int handled = 0; 305 306 hdsr0 = 0; 307 hdsr1 = 0; 308 309 /* grab interrupt register */ 310 intr = BA0READ4(sc, CS4281_HISR); 311 312 DPRINTF(("cs4281_intr:")); 313 /* not for me */ 314 if ((intr & HISR_INTENA) == 0) { 315 /* clear the interrupt register */ 316 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 317 return 0; 318 } 319 320 if (intr & HISR_DMA0) 321 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 322 if (intr & HISR_DMA1) 323 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 324 /* clear the interrupt register */ 325 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 326 327 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 328 intr, hdsr0, hdsr1)); 329 330 /* Playback Interrupt */ 331 if (intr & HISR_DMA0) { 332 handled = 1; 333 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 334 (int)BA0READ4(sc, CS4281_DCC0))); 335 if (sc->sc_pintr) { 336 if ((sc->sc_pi%sc->sc_pcount) == 0) 337 sc->sc_pintr(sc->sc_parg); 338 } else { 339 printf("unexpected play intr\n"); 340 } 341 /* copy buffer */ 342 ++sc->sc_pi; 343 empty_dma = sc->sc_pdma->addr; 344 if (sc->sc_pi&1) 345 empty_dma += sc->hw_blocksize; 346 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 347 sc->sc_pn += sc->hw_blocksize; 348 if (sc->sc_pn >= sc->sc_pe) 349 sc->sc_pn = sc->sc_ps; 350 } 351 if (intr & HISR_DMA1) { 352 handled = 1; 353 /* copy from dma */ 354 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 355 (int)BA0READ4(sc, CS4281_DCC1))); 356 ++sc->sc_ri; 357 empty_dma = sc->sc_rdma->addr; 358 if ((sc->sc_ri & 1) == 0) 359 empty_dma += sc->hw_blocksize; 360 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 361 if (sc->sc_rn >= sc->sc_re) 362 sc->sc_rn = sc->sc_rs; 363 if (sc->sc_rintr) { 364 if ((sc->sc_ri % sc->sc_rcount) == 0) 365 sc->sc_rintr(sc->sc_rarg); 366 } else { 367 printf("unexpected record intr\n"); 368 } 369 } 370 DPRINTF(("\n")); 371 372 return handled; 373 } 374 375 int 376 cs4281_query_encoding(addr, fp) 377 void *addr; 378 struct audio_encoding *fp; 379 { 380 switch (fp->index) { 381 case 0: 382 strcpy(fp->name, AudioEulinear); 383 fp->encoding = AUDIO_ENCODING_ULINEAR; 384 fp->precision = 8; 385 fp->flags = 0; 386 break; 387 case 1: 388 strcpy(fp->name, AudioEmulaw); 389 fp->encoding = AUDIO_ENCODING_ULAW; 390 fp->precision = 8; 391 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 392 break; 393 case 2: 394 strcpy(fp->name, AudioEalaw); 395 fp->encoding = AUDIO_ENCODING_ALAW; 396 fp->precision = 8; 397 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 398 break; 399 case 3: 400 strcpy(fp->name, AudioEslinear); 401 fp->encoding = AUDIO_ENCODING_SLINEAR; 402 fp->precision = 8; 403 fp->flags = 0; 404 break; 405 case 4: 406 strcpy(fp->name, AudioEslinear_le); 407 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 408 fp->precision = 16; 409 fp->flags = 0; 410 break; 411 case 5: 412 strcpy(fp->name, AudioEulinear_le); 413 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 414 fp->precision = 16; 415 fp->flags = 0; 416 break; 417 case 6: 418 strcpy(fp->name, AudioEslinear_be); 419 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 420 fp->precision = 16; 421 fp->flags = 0; 422 break; 423 case 7: 424 strcpy(fp->name, AudioEulinear_be); 425 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 426 fp->precision = 16; 427 fp->flags = 0; 428 break; 429 default: 430 return EINVAL; 431 } 432 return 0; 433 } 434 435 int 436 cs4281_set_params(addr, setmode, usemode, play, rec) 437 void *addr; 438 int setmode, usemode; 439 struct audio_params *play, *rec; 440 { 441 struct cs428x_softc *sc = addr; 442 struct audio_params *p; 443 int mode; 444 445 for (mode = AUMODE_RECORD; mode != -1; 446 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 447 if ((setmode & mode) == 0) 448 continue; 449 450 p = mode == AUMODE_PLAY ? play : rec; 451 452 if (p == play) { 453 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 454 p->sample_rate, p->precision, p->channels)); 455 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 456 (p->precision != 8 && p->precision != 16) || 457 (p->channels != 1 && p->channels != 2)) { 458 return (EINVAL); 459 } 460 } else { 461 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 462 p->sample_rate, p->precision, p->channels)); 463 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 464 (p->precision != 8 && p->precision != 16) || 465 (p->channels != 1 && p->channels != 2)) { 466 return (EINVAL); 467 } 468 } 469 p->factor = 1; 470 p->sw_code = 0; 471 472 switch (p->encoding) { 473 case AUDIO_ENCODING_SLINEAR_BE: 474 break; 475 case AUDIO_ENCODING_SLINEAR_LE: 476 break; 477 case AUDIO_ENCODING_ULINEAR_BE: 478 break; 479 case AUDIO_ENCODING_ULINEAR_LE: 480 break; 481 case AUDIO_ENCODING_ULAW: 482 if (mode == AUMODE_PLAY) { 483 p->sw_code = mulaw_to_slinear8; 484 } else { 485 p->sw_code = slinear8_to_mulaw; 486 } 487 break; 488 case AUDIO_ENCODING_ALAW: 489 if (mode == AUMODE_PLAY) { 490 p->sw_code = alaw_to_slinear8; 491 } else { 492 p->sw_code = slinear8_to_alaw; 493 } 494 break; 495 default: 496 return (EINVAL); 497 } 498 } 499 500 /* set sample rate */ 501 cs4281_set_dac_rate(sc, play->sample_rate); 502 cs4281_set_adc_rate(sc, rec->sample_rate); 503 return 0; 504 } 505 506 int 507 cs4281_halt_output(addr) 508 void *addr; 509 { 510 struct cs428x_softc *sc = addr; 511 512 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 513 sc->sc_prun = 0; 514 return 0; 515 } 516 517 int 518 cs4281_halt_input(addr) 519 void *addr; 520 { 521 struct cs428x_softc *sc = addr; 522 523 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 524 sc->sc_rrun = 0; 525 return 0; 526 } 527 528 int 529 cs4281_getdev(addr, retp) 530 void *addr; 531 struct audio_device *retp; 532 { 533 *retp = cs4281_device; 534 return 0; 535 } 536 537 int 538 cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 539 void *addr; 540 void *start, *end; 541 int blksize; 542 void (*intr) __P((void *)); 543 void *arg; 544 struct audio_params *param; 545 { 546 struct cs428x_softc *sc = addr; 547 u_int32_t fmt=0; 548 struct cs428x_dma *p; 549 int dma_count; 550 551 #ifdef DIAGNOSTIC 552 if (sc->sc_prun) 553 printf("cs4281_trigger_output: already running\n"); 554 #endif 555 sc->sc_prun = 1; 556 557 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 558 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 559 sc->sc_pintr = intr; 560 sc->sc_parg = arg; 561 562 /* stop playback DMA */ 563 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 564 565 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 566 param->precision, param->factor, param->channels, 567 param->encoding)); 568 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 569 ; 570 if (p == NULL) { 571 printf("cs4281_trigger_output: bad addr %p\n", start); 572 return (EINVAL); 573 } 574 575 sc->sc_pcount = blksize / sc->hw_blocksize; 576 sc->sc_ps = (char *)start; 577 sc->sc_pe = (char *)end; 578 sc->sc_pdma = p; 579 sc->sc_pbuf = KERNADDR(p); 580 sc->sc_pi = 0; 581 sc->sc_pn = sc->sc_ps; 582 if (blksize >= sc->dma_size) { 583 sc->sc_pn = sc->sc_ps + sc->dma_size; 584 memcpy(sc->sc_pbuf, start, sc->dma_size); 585 ++sc->sc_pi; 586 } else { 587 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 588 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 589 } 590 591 dma_count = sc->dma_size; 592 if (param->precision * param->factor != 8) 593 dma_count /= 2; /* 16 bit */ 594 if (param->channels > 1) 595 dma_count /= 2; /* Stereo */ 596 597 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 598 (int)DMAADDR(p), dma_count)); 599 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 600 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 601 602 /* set playback format */ 603 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 604 if (param->precision * param->factor == 8) 605 fmt |= DMRn_SIZE8; 606 if (param->channels == 1) 607 fmt |= DMRn_MONO; 608 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 609 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 610 fmt |= DMRn_BEND; 611 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 612 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 613 fmt |= DMRn_USIGN; 614 BA0WRITE4(sc, CS4281_DMR0, fmt); 615 616 /* set sample rate */ 617 sc->sc_prate = param->sample_rate; 618 cs4281_set_dac_rate(sc, param->sample_rate); 619 620 /* start DMA */ 621 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 622 /* Enable interrupts */ 623 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 624 625 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 626 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 627 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 628 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 629 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 630 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 631 BA0READ4(sc, CS4281_DACSR))); 632 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 633 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 634 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 635 636 return 0; 637 } 638 639 int 640 cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 641 void *addr; 642 void *start, *end; 643 int blksize; 644 void (*intr) __P((void *)); 645 void *arg; 646 struct audio_params *param; 647 { 648 struct cs428x_softc *sc = addr; 649 struct cs428x_dma *p; 650 u_int32_t fmt=0; 651 int dma_count; 652 653 #ifdef DIAGNOSTIC 654 if (sc->sc_rrun) 655 printf("cs4281_trigger_input: already running\n"); 656 #endif 657 sc->sc_rrun = 1; 658 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 659 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 660 sc->sc_rintr = intr; 661 sc->sc_rarg = arg; 662 663 /* stop recording DMA */ 664 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 665 666 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 667 ; 668 if (!p) { 669 printf("cs4281_trigger_input: bad addr %p\n", start); 670 return (EINVAL); 671 } 672 673 sc->sc_rcount = blksize / sc->hw_blocksize; 674 sc->sc_rs = (char *)start; 675 sc->sc_re = (char *)end; 676 sc->sc_rdma = p; 677 sc->sc_rbuf = KERNADDR(p); 678 sc->sc_ri = 0; 679 sc->sc_rn = sc->sc_rs; 680 681 dma_count = sc->dma_size; 682 if (param->precision * param->factor == 8) 683 dma_count /= 2; 684 if (param->channels > 1) 685 dma_count /= 2; 686 687 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 688 (int)DMAADDR(p), dma_count)); 689 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 690 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 691 692 /* set recording format */ 693 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 694 if (param->precision * param->factor == 8) 695 fmt |= DMRn_SIZE8; 696 if (param->channels == 1) 697 fmt |= DMRn_MONO; 698 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 699 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 700 fmt |= DMRn_BEND; 701 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 702 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 703 fmt |= DMRn_USIGN; 704 BA0WRITE4(sc, CS4281_DMR1, fmt); 705 706 /* set sample rate */ 707 sc->sc_rrate = param->sample_rate; 708 cs4281_set_adc_rate(sc, param->sample_rate); 709 710 /* Start DMA */ 711 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 712 /* Enable interrupts */ 713 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 714 715 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 716 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 717 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 718 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 719 720 return 0; 721 } 722 723 /* Power Hook */ 724 void 725 cs4281_power(why, v) 726 int why; 727 void *v; 728 { 729 struct cs428x_softc *sc = (struct cs428x_softc *)v; 730 static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 731 static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 732 733 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 734 switch (why) { 735 case PWR_SUSPEND: 736 case PWR_STANDBY: 737 sc->sc_suspend = why; 738 739 /* save current playback status */ 740 if (sc->sc_prun) { 741 dcr0 = BA0READ4(sc, CS4281_DCR0); 742 dmr0 = BA0READ4(sc, CS4281_DMR0); 743 dbc0 = BA0READ4(sc, CS4281_DBC0); 744 dba0 = BA0READ4(sc, CS4281_DBA0); 745 } 746 747 /* save current capture status */ 748 if (sc->sc_rrun) { 749 dcr1 = BA0READ4(sc, CS4281_DCR1); 750 dmr1 = BA0READ4(sc, CS4281_DMR1); 751 dbc1 = BA0READ4(sc, CS4281_DBC1); 752 dba1 = BA0READ4(sc, CS4281_DBA1); 753 } 754 /* Stop DMA */ 755 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 756 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 757 break; 758 case PWR_RESUME: 759 if (sc->sc_suspend == PWR_RESUME) { 760 printf("cs4281_power: odd, resume without suspend.\n"); 761 sc->sc_suspend = why; 762 return; 763 } 764 sc->sc_suspend = why; 765 cs4281_init(sc,0); 766 cs4281_reset_codec(sc); 767 768 /* restore ac97 registers */ 769 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 770 771 /* restore DMA related status */ 772 if (sc->sc_prun) { 773 cs4281_set_dac_rate(sc, sc->sc_prate); 774 BA0WRITE4(sc, CS4281_DBA0, dba0); 775 BA0WRITE4(sc, CS4281_DBC0, dbc0); 776 BA0WRITE4(sc, CS4281_DMR0, dmr0); 777 BA0WRITE4(sc, CS4281_DCR0, dcr0); 778 } 779 if (sc->sc_rrun) { 780 cs4281_set_adc_rate(sc, sc->sc_rrate); 781 BA0WRITE4(sc, CS4281_DBA1, dba1); 782 BA0WRITE4(sc, CS4281_DBC1, dbc1); 783 BA0WRITE4(sc, CS4281_DMR1, dmr1); 784 BA0WRITE4(sc, CS4281_DCR1, dcr1); 785 } 786 /* enable intterupts */ 787 if (sc->sc_prun || sc->sc_rrun) 788 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 789 break; 790 case PWR_SOFTSUSPEND: 791 case PWR_SOFTSTANDBY: 792 case PWR_SOFTRESUME: 793 break; 794 } 795 } 796 797 /* control AC97 codec */ 798 void 799 cs4281_reset_codec(void *addr) 800 { 801 struct cs428x_softc *sc; 802 u_int16_t data; 803 u_int32_t dat32; 804 int n; 805 806 sc = addr; 807 808 DPRINTFN(3,("cs4281_reset_codec\n")); 809 810 /* Reset codec */ 811 BA0WRITE4(sc, CS428X_ACCTL, 0); 812 delay(50); /* delay 50us */ 813 814 BA0WRITE4(sc, CS4281_SPMC, 0); 815 delay(100); /* delay 100us */ 816 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 817 #if defined(ENABLE_SECONDARY_CODEC) 818 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 819 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 820 #endif 821 delay(50000); /* XXX: delay 50ms */ 822 823 /* Enable ASYNC generation */ 824 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 825 826 /* Wait for Codec ready. Linux driver wait 50ms here */ 827 n = 0; 828 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 829 delay(100); 830 if (++n > 1000) { 831 printf("reset_codec: AC97 codec ready timeout\n"); 832 return; 833 } 834 } 835 #if defined(ENABLE_SECONDARY_CODEC) 836 /* secondary codec ready*/ 837 n = 0; 838 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 839 delay(100); 840 if (++n > 1000) 841 return; 842 } 843 #endif 844 /* Set the serial timing configuration */ 845 /* XXX: undocumented but the Linux driver do this */ 846 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 847 848 /* Wait for Codec ready signal */ 849 n = 0; 850 do { 851 delay(1000); 852 if (++n > 1000) { 853 printf("%s: Timeout waiting for Codec ready\n", 854 sc->sc_dev.dv_xname); 855 return; 856 } 857 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 858 } while (dat32 == 0); 859 860 /* Enable Valid Frame output on ASDOUT */ 861 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 862 863 /* Wait until Codec Calibration is finished. Codec register 26h */ 864 n = 0; 865 do { 866 delay(1); 867 if (++n > 1000) { 868 printf("%s: Timeout waiting for Codec calibration\n", 869 sc->sc_dev.dv_xname); 870 return ; 871 } 872 cs428x_read_codec(sc, AC97_REG_POWER, &data); 873 } while ((data & 0x0f) != 0x0f); 874 875 /* Set the serial timing configuration again */ 876 /* XXX: undocumented but the Linux driver do this */ 877 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 878 879 /* Wait until we've sampled input slots 3 & 4 as valid */ 880 n = 0; 881 do { 882 delay(1000); 883 if (++n > 1000) { 884 printf("%s: Timeout waiting for sampled input slots as valid\n", 885 sc->sc_dev.dv_xname); 886 return; 887 } 888 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 889 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 890 891 /* Start digital data transfer of audio data to the codec */ 892 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 893 } 894 895 896 /* Internal functions */ 897 898 /* convert sample rate to register value */ 899 u_int8_t 900 cs4281_sr2regval(rate) 901 int rate; 902 { 903 u_int8_t retval; 904 905 /* We don't have to change here. but anyway ... */ 906 if (rate > 48000) 907 rate = 48000; 908 if (rate < 6023) 909 rate = 6023; 910 911 switch (rate) { 912 case 8000: 913 retval = 5; 914 break; 915 case 11025: 916 retval = 4; 917 break; 918 case 16000: 919 retval = 3; 920 break; 921 case 22050: 922 retval = 2; 923 break; 924 case 44100: 925 retval = 1; 926 break; 927 case 48000: 928 retval = 0; 929 break; 930 default: 931 retval = 1536000/rate; /* == 24576000/(rate*16) */ 932 } 933 return retval; 934 } 935 936 void 937 cs4281_set_adc_rate(sc, rate) 938 struct cs428x_softc *sc; 939 int rate; 940 { 941 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 942 } 943 944 void 945 cs4281_set_dac_rate(sc, rate) 946 struct cs428x_softc *sc; 947 int rate; 948 { 949 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 950 } 951 952 int 953 cs4281_init(sc, init) 954 struct cs428x_softc *sc; 955 int init; 956 { 957 int n; 958 u_int16_t data; 959 u_int32_t dat32; 960 961 /* set "Configuration Write Protect" register to 962 * 0x4281 to allow to write */ 963 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 964 965 /* 966 * Unset "Full Power-Down bit of Extended PCI Power Management 967 * Control" register to release the reset state. 968 */ 969 dat32 = BA0READ4(sc, CS4281_EPPMC); 970 if (dat32 & EPPMC_FPDN) { 971 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 972 } 973 974 /* Start PLL out in known state */ 975 BA0WRITE4(sc, CS4281_CLKCR1, 0); 976 /* Start serial ports out in known state */ 977 BA0WRITE4(sc, CS4281_SERMC, 0); 978 979 /* Reset codec */ 980 BA0WRITE4(sc, CS428X_ACCTL, 0); 981 delay(50); /* delay 50us */ 982 983 BA0WRITE4(sc, CS4281_SPMC, 0); 984 delay(100); /* delay 100us */ 985 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 986 #if defined(ENABLE_SECONDARY_CODEC) 987 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 988 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 989 #endif 990 delay(50000); /* XXX: delay 50ms */ 991 992 /* Turn on Sound System clocks based on ABITCLK */ 993 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 994 delay(50000); /* XXX: delay 50ms */ 995 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 996 997 /* Set enables for sections that are needed in the SSPM registers */ 998 BA0WRITE4(sc, CS4281_SSPM, 999 SSPM_MIXEN | /* Mixer */ 1000 SSPM_CSRCEN | /* Capture SRC */ 1001 SSPM_PSRCEN | /* Playback SRC */ 1002 SSPM_JSEN | /* Joystick */ 1003 SSPM_ACLEN | /* AC LINK */ 1004 SSPM_FMEN /* FM */ 1005 ); 1006 1007 /* Wait for clock stabilization */ 1008 n = 0; 1009 #if 1 1010 /* what document says */ 1011 while ( ( BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1012 != (CLKCR1_DLLRDY | CLKCR1_CLKON )) { 1013 delay(100); 1014 if ( ++n > 1000 ) 1015 return -1; 1016 } 1017 #else 1018 /* Cirrus driver for Linux does */ 1019 while ( !(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1020 delay(1000); 1021 if ( ++n > 1000 ) 1022 return -1; 1023 } 1024 #endif 1025 1026 /* Enable ASYNC generation */ 1027 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1028 1029 /* Wait for Codec ready. Linux driver wait 50ms here */ 1030 n = 0; 1031 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1032 delay(100); 1033 if (++n > 1000) 1034 return -1; 1035 } 1036 1037 #if defined(ENABLE_SECONDARY_CODEC) 1038 /* secondary codec ready*/ 1039 n = 0; 1040 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1041 delay(100); 1042 if (++n > 1000) 1043 return -1; 1044 } 1045 #endif 1046 1047 /* Set the serial timing configuration */ 1048 /* XXX: undocumented but the Linux driver do this */ 1049 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1050 1051 /* Wait for Codec ready signal */ 1052 n = 0; 1053 do { 1054 delay(1000); 1055 if (++n > 1000) { 1056 printf("%s: Timeout waiting for Codec ready\n", 1057 sc->sc_dev.dv_xname); 1058 return -1; 1059 } 1060 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1061 } while (dat32 == 0); 1062 1063 /* Enable Valid Frame output on ASDOUT */ 1064 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1065 1066 /* Wait until Codec Calibration is finished. Codec register 26h */ 1067 n = 0; 1068 do { 1069 delay(1); 1070 if (++n > 1000) { 1071 printf("%s: Timeout waiting for Codec calibration\n", 1072 sc->sc_dev.dv_xname); 1073 return -1; 1074 } 1075 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1076 } while ((data & 0x0f) != 0x0f); 1077 1078 /* Set the serial timing configuration again */ 1079 /* XXX: undocumented but the Linux driver do this */ 1080 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1081 1082 /* Wait until we've sampled input slots 3 & 4 as valid */ 1083 n = 0; 1084 do { 1085 delay(1000); 1086 if (++n > 1000) { 1087 printf("%s: Timeout waiting for sampled input slots as valid\n", 1088 sc->sc_dev.dv_xname); 1089 return -1; 1090 } 1091 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1092 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1093 1094 /* Start digital data transfer of audio data to the codec */ 1095 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1096 1097 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1098 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1099 1100 /* Power on the DAC */ 1101 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1102 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1103 1104 /* Wait until we sample a DAC ready state. 1105 * Not documented, but Linux driver does. 1106 */ 1107 for (n = 0; n < 32; ++n) { 1108 delay(1000); 1109 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1110 if (data & 0x02) 1111 break; 1112 } 1113 1114 /* Power on the ADC */ 1115 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1116 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1117 1118 /* Wait until we sample ADC ready state. 1119 * Not documented, but Linux driver does. 1120 */ 1121 for (n = 0; n < 32; ++n) { 1122 delay(1000); 1123 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1124 if (data & 0x01) 1125 break; 1126 } 1127 1128 #if 0 1129 /* Initialize AC-Link features */ 1130 /* variable sample-rate support */ 1131 mem = BA0READ4(sc, CS4281_SERMC); 1132 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1133 BA0WRITE4(sc, CS4281_SERMC, mem); 1134 /* XXX: more... */ 1135 1136 /* Initialize SSCR register features */ 1137 /* XXX: hardware volume setting */ 1138 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1139 #endif 1140 1141 /* disable Sound Blaster Pro emulation */ 1142 /* XXX: 1143 * Cannot set since the documents does not describe which bit is 1144 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1145 * we can ignore it.*/ 1146 #if 0 1147 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1148 #endif 1149 1150 /* map AC97 PCM playback to DMA Channel 0 */ 1151 /* Reset FEN bit to setup first */ 1152 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc,CS4281_FCR0) & ~FCRn_FEN)); 1153 /* 1154 *| RS[4:0]/| | 1155 *| LS[4:0] | AC97 | Slot Function 1156 *|---------+--------+-------------------- 1157 *| 0 | 3 | Left PCM Playback 1158 *| 1 | 4 | Right PCM Playback 1159 *| 2 | 5 | Phone Line 1 DAC 1160 *| 3 | 6 | Center PCM Playback 1161 *.... 1162 * quoted from Table 29(p109) 1163 */ 1164 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1165 0x00 << 16 | /* LS[4:0] = 0 see above */ 1166 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1167 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1168 BA0WRITE4(sc, CS4281_FCR0, dat32); 1169 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1170 1171 /* map AC97 PCM record to DMA Channel 1 */ 1172 /* Reset FEN bit to setup first */ 1173 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc,CS4281_FCR1) & ~FCRn_FEN)); 1174 /* 1175 *| RS[4:0]/| 1176 *| LS[4:0] | AC97 | Slot Function 1177 *|---------+------+------------------- 1178 *| 10 | 3 | Left PCM Record 1179 *| 11 | 4 | Right PCM Record 1180 *| 12 | 5 | Phone Line 1 ADC 1181 *| 13 | 6 | Mic ADC 1182 *.... 1183 * quoted from Table 30(p109) 1184 */ 1185 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1186 0x0a << 16 | /* LS[4:0] = 10 See above */ 1187 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1188 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1189 1190 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1191 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1192 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1193 1194 #if 0 1195 /* Disable DMA Channel 2, 3 */ 1196 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc,CS4281_FCR2) & ~FCRn_FEN)); 1197 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc,CS4281_FCR3) & ~FCRn_FEN)); 1198 #endif 1199 1200 /* Set the SRC Slot Assignment accordingly */ 1201 /*| PLSS[4:0]/ 1202 *| PRSS[4:0] | AC97 | Slot Function 1203 *|-----------+------+---------------- 1204 *| 0 | 3 | Left PCM Playback 1205 *| 1 | 4 | Right PCM Playback 1206 *| 2 | 5 | phone line 1 DAC 1207 *| 3 | 6 | Center PCM Playback 1208 *| 4 | 7 | Left Surround PCM Playback 1209 *| 5 | 8 | Right Surround PCM Playback 1210 *...... 1211 * 1212 *| CLSS[4:0]/ 1213 *| CRSS[4:0] | AC97 | Codec |Slot Function 1214 *|-----------+------+-------+----------------- 1215 *| 10 | 3 |Primary| Left PCM Record 1216 *| 11 | 4 |Primary| Right PCM Record 1217 *| 12 | 5 |Primary| Phone Line 1 ADC 1218 *| 13 | 6 |Primary| Mic ADC 1219 *|..... 1220 *| 20 | 3 | Sec. | Left PCM Record 1221 *| 21 | 4 | Sec. | Right PCM Record 1222 *| 22 | 5 | Sec. | Phone Line 1 ADC 1223 *| 23 | 6 | Sec. | Mic ADC 1224 */ 1225 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1226 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1227 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1228 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1229 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1230 1231 /* Set interrupt to occured at Half and Full terminal 1232 * count interrupt enable for DMA channel 0 and 1. 1233 * To keep DMA stop, set MSK. 1234 */ 1235 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1236 BA0WRITE4(sc, CS4281_DCR0, dat32); 1237 BA0WRITE4(sc, CS4281_DCR1, dat32); 1238 1239 /* Set Auto-Initialize Contorl enable */ 1240 BA0WRITE4(sc, CS4281_DMR0, 1241 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1242 BA0WRITE4(sc, CS4281_DMR1, 1243 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1244 1245 /* Clear DMA Mask in HIMR */ 1246 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1247 BA0WRITE4(sc, CS4281_HIMR, 1248 BA0READ4(sc, CS4281_HIMR) & dat32); 1249 1250 /* set current status */ 1251 if (init != 0) { 1252 sc->sc_prun = 0; 1253 sc->sc_rrun = 0; 1254 } 1255 1256 /* setup playback volume */ 1257 BA0WRITE4(sc, CS4281_PPRVC, 7); 1258 BA0WRITE4(sc, CS4281_PPLVC, 7); 1259 1260 return 0; 1261 } 1262
Indexes created Thu Oct 02 10:09:58 GMT 2025