cs4281.c revision 1.4.4.1
1 /* $NetBSD: cs4281.c,v 1.4.4.1 2002/01/10 19:56:30 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.4.4.1 2002/01/10 19:56:30 thorpej Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <machine/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 int cs4281_match(struct device *, struct cfdata *, void *); 84 void cs4281_attach(struct device *, struct device *, void *); 85 int cs4281_intr(void *); 86 int cs4281_query_encoding(void *, struct audio_encoding *); 87 int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 88 int cs4281_halt_output(void *); 89 int cs4281_halt_input(void *); 90 int cs4281_getdev(void *, struct audio_device *); 91 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 92 void *, struct audio_params *); 93 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 94 void *, struct audio_params *); 95 96 void cs4281_reset_codec(void *); 97 98 /* Internal functions */ 99 u_int8_t cs4281_sr2regval(int); 100 void cs4281_set_dac_rate(struct cs428x_softc *, int); 101 void cs4281_set_adc_rate(struct cs428x_softc *, int); 102 int cs4281_init(struct cs428x_softc *, int); 103 104 /* Power Management */ 105 void cs4281_power(int, void *); 106 107 struct audio_hw_if cs4281_hw_if = { 108 cs428x_open, 109 cs428x_close, 110 NULL, 111 cs4281_query_encoding, 112 cs4281_set_params, 113 cs428x_round_blocksize, 114 NULL, 115 NULL, 116 NULL, 117 NULL, 118 NULL, 119 cs4281_halt_output, 120 cs4281_halt_input, 121 NULL, 122 cs4281_getdev, 123 NULL, 124 cs428x_mixer_set_port, 125 cs428x_mixer_get_port, 126 cs428x_query_devinfo, 127 cs428x_malloc, 128 cs428x_free, 129 cs428x_round_buffersize, 130 cs428x_mappage, 131 cs428x_get_props, 132 cs4281_trigger_output, 133 cs4281_trigger_input, 134 NULL, 135 }; 136 137 #if NMIDI > 0 && 0 138 /* Midi Interface */ 139 void cs4281_midi_close(void*); 140 void cs4281_midi_getinfo(void *, struct midi_info *); 141 int cs4281_midi_open(void *, int, void (*)(void *, int), 142 void (*)(void *), void *); 143 int cs4281_midi_output(void *, int); 144 145 struct midi_hw_if cs4281_midi_hw_if = { 146 cs4281_midi_open, 147 cs4281_midi_close, 148 cs4281_midi_output, 149 cs4281_midi_getinfo, 150 0, 151 }; 152 #endif 153 154 struct cfattach clct_ca = { 155 sizeof(struct cs428x_softc), cs4281_match, cs4281_attach 156 }; 157 158 struct audio_device cs4281_device = { 159 "CS4281", 160 "", 161 "cs4281" 162 }; 163 164 165 int 166 cs4281_match(parent, match, aux) 167 struct device *parent; 168 struct cfdata *match; 169 void *aux; 170 { 171 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 172 173 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 174 return 0; 175 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 176 return 1; 177 return 0; 178 } 179 180 void 181 cs4281_attach(parent, self, aux) 182 struct device *parent; 183 struct device *self; 184 void *aux; 185 { 186 struct cs428x_softc *sc = (struct cs428x_softc *)self; 187 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 char const *intrstr; 190 pci_intr_handle_t ih; 191 pcireg_t reg; 192 char devinfo[256]; 193 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 194 195 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 196 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 197 198 /* Map I/O register */ 199 if (pci_mapreg_map(pa, PCI_BA0, 200 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 201 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 202 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 203 return; 204 } 205 if (pci_mapreg_map(pa, PCI_BA1, 206 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 207 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 208 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 209 return; 210 } 211 212 sc->sc_dmatag = pa->pa_dmat; 213 214 /* 215 * Set Power State D0. 216 * Without do this, 0xffffffff is read from all registers after 217 * using Windows. 218 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 219 */ 220 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 221 &pci_pwrmgmt_cap_reg, 0)) { 222 223 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 224 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 225 pci_pwrmgmt_csr_reg); 226 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 227 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 228 (reg & ~PCI_PMCSR_STATE_MASK) | 229 PCI_PMCSR_STATE_D0); 230 } 231 } 232 233 /* Enable the device (set bus master flag) */ 234 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 235 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 236 reg | PCI_COMMAND_MASTER_ENABLE); 237 238 #if 0 239 /* LATENCY_TIMER setting */ 240 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 241 if ( PCI_LATTIMER(temp1) < 32 ) { 242 temp1 &= 0xffff00ff; 243 temp1 |= 0x00002000; 244 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 245 } 246 #endif 247 248 /* Map and establish the interrupt. */ 249 if (pci_intr_map(pa, &ih)) { 250 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 251 return; 252 } 253 intrstr = pci_intr_string(pc, ih); 254 255 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 256 if (sc->sc_ih == NULL) { 257 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 258 if (intrstr != NULL) 259 printf(" at %s", intrstr); 260 printf("\n"); 261 return; 262 } 263 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 264 265 /* 266 * Sound System start-up 267 */ 268 if (cs4281_init(sc,1) != 0) 269 return; 270 271 sc->type = TYPE_CS4281; 272 sc->halt_input = cs4281_halt_input; 273 sc->halt_output = cs4281_halt_output; 274 275 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 276 sc->dma_align = 0x10; 277 sc->hw_blocksize = sc->dma_size / 2; 278 279 /* AC 97 attachment */ 280 sc->host_if.arg = sc; 281 sc->host_if.attach = cs428x_attach_codec; 282 sc->host_if.read = cs428x_read_codec; 283 sc->host_if.write = cs428x_write_codec; 284 sc->host_if.reset = cs4281_reset_codec; 285 if (ac97_attach(&sc->host_if) != 0) { 286 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 287 return; 288 } 289 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 290 291 #if NMIDI > 0 && 0 292 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 293 #endif 294 295 sc->sc_suspend = PWR_RESUME; 296 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 297 } 298 299 int 300 cs4281_intr(p) 301 void *p; 302 { 303 struct cs428x_softc *sc = p; 304 u_int32_t intr, hdsr0, hdsr1; 305 char *empty_dma; 306 int handled = 0; 307 308 hdsr0 = 0; 309 hdsr1 = 0; 310 311 /* grab interrupt register */ 312 intr = BA0READ4(sc, CS4281_HISR); 313 314 DPRINTF(("cs4281_intr:")); 315 /* not for me */ 316 if ((intr & HISR_INTENA) == 0) { 317 /* clear the interrupt register */ 318 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 319 return 0; 320 } 321 322 if (intr & HISR_DMA0) 323 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 324 if (intr & HISR_DMA1) 325 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 326 /* clear the interrupt register */ 327 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 328 329 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 330 intr, hdsr0, hdsr1)); 331 332 /* Playback Interrupt */ 333 if (intr & HISR_DMA0) { 334 handled = 1; 335 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 336 (int)BA0READ4(sc, CS4281_DCC0))); 337 if (sc->sc_pintr) { 338 if ((sc->sc_pi%sc->sc_pcount) == 0) 339 sc->sc_pintr(sc->sc_parg); 340 } else { 341 printf("unexpected play intr\n"); 342 } 343 /* copy buffer */ 344 ++sc->sc_pi; 345 empty_dma = sc->sc_pdma->addr; 346 if (sc->sc_pi&1) 347 empty_dma += sc->hw_blocksize; 348 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 349 sc->sc_pn += sc->hw_blocksize; 350 if (sc->sc_pn >= sc->sc_pe) 351 sc->sc_pn = sc->sc_ps; 352 } 353 if (intr & HISR_DMA1) { 354 handled = 1; 355 /* copy from dma */ 356 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 357 (int)BA0READ4(sc, CS4281_DCC1))); 358 ++sc->sc_ri; 359 empty_dma = sc->sc_rdma->addr; 360 if ((sc->sc_ri & 1) == 0) 361 empty_dma += sc->hw_blocksize; 362 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 363 if (sc->sc_rn >= sc->sc_re) 364 sc->sc_rn = sc->sc_rs; 365 if (sc->sc_rintr) { 366 if ((sc->sc_ri % sc->sc_rcount) == 0) 367 sc->sc_rintr(sc->sc_rarg); 368 } else { 369 printf("unexpected record intr\n"); 370 } 371 } 372 DPRINTF(("\n")); 373 374 return handled; 375 } 376 377 int 378 cs4281_query_encoding(addr, fp) 379 void *addr; 380 struct audio_encoding *fp; 381 { 382 switch (fp->index) { 383 case 0: 384 strcpy(fp->name, AudioEulinear); 385 fp->encoding = AUDIO_ENCODING_ULINEAR; 386 fp->precision = 8; 387 fp->flags = 0; 388 break; 389 case 1: 390 strcpy(fp->name, AudioEmulaw); 391 fp->encoding = AUDIO_ENCODING_ULAW; 392 fp->precision = 8; 393 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 394 break; 395 case 2: 396 strcpy(fp->name, AudioEalaw); 397 fp->encoding = AUDIO_ENCODING_ALAW; 398 fp->precision = 8; 399 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 400 break; 401 case 3: 402 strcpy(fp->name, AudioEslinear); 403 fp->encoding = AUDIO_ENCODING_SLINEAR; 404 fp->precision = 8; 405 fp->flags = 0; 406 break; 407 case 4: 408 strcpy(fp->name, AudioEslinear_le); 409 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 410 fp->precision = 16; 411 fp->flags = 0; 412 break; 413 case 5: 414 strcpy(fp->name, AudioEulinear_le); 415 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 416 fp->precision = 16; 417 fp->flags = 0; 418 break; 419 case 6: 420 strcpy(fp->name, AudioEslinear_be); 421 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 422 fp->precision = 16; 423 fp->flags = 0; 424 break; 425 case 7: 426 strcpy(fp->name, AudioEulinear_be); 427 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 428 fp->precision = 16; 429 fp->flags = 0; 430 break; 431 default: 432 return EINVAL; 433 } 434 return 0; 435 } 436 437 int 438 cs4281_set_params(addr, setmode, usemode, play, rec) 439 void *addr; 440 int setmode, usemode; 441 struct audio_params *play, *rec; 442 { 443 struct cs428x_softc *sc = addr; 444 struct audio_params *p; 445 int mode; 446 447 for (mode = AUMODE_RECORD; mode != -1; 448 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 449 if ((setmode & mode) == 0) 450 continue; 451 452 p = mode == AUMODE_PLAY ? play : rec; 453 454 if (p == play) { 455 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 456 p->sample_rate, p->precision, p->channels)); 457 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 458 (p->precision != 8 && p->precision != 16) || 459 (p->channels != 1 && p->channels != 2)) { 460 return (EINVAL); 461 } 462 } else { 463 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 464 p->sample_rate, p->precision, p->channels)); 465 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 466 (p->precision != 8 && p->precision != 16) || 467 (p->channels != 1 && p->channels != 2)) { 468 return (EINVAL); 469 } 470 } 471 p->factor = 1; 472 p->sw_code = 0; 473 474 switch (p->encoding) { 475 case AUDIO_ENCODING_SLINEAR_BE: 476 break; 477 case AUDIO_ENCODING_SLINEAR_LE: 478 break; 479 case AUDIO_ENCODING_ULINEAR_BE: 480 break; 481 case AUDIO_ENCODING_ULINEAR_LE: 482 break; 483 case AUDIO_ENCODING_ULAW: 484 if (mode == AUMODE_PLAY) { 485 p->sw_code = mulaw_to_slinear8; 486 } else { 487 p->sw_code = slinear8_to_mulaw; 488 } 489 break; 490 case AUDIO_ENCODING_ALAW: 491 if (mode == AUMODE_PLAY) { 492 p->sw_code = alaw_to_slinear8; 493 } else { 494 p->sw_code = slinear8_to_alaw; 495 } 496 break; 497 default: 498 return (EINVAL); 499 } 500 } 501 502 /* set sample rate */ 503 cs4281_set_dac_rate(sc, play->sample_rate); 504 cs4281_set_adc_rate(sc, rec->sample_rate); 505 return 0; 506 } 507 508 int 509 cs4281_halt_output(addr) 510 void *addr; 511 { 512 struct cs428x_softc *sc = addr; 513 514 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 515 sc->sc_prun = 0; 516 return 0; 517 } 518 519 int 520 cs4281_halt_input(addr) 521 void *addr; 522 { 523 struct cs428x_softc *sc = addr; 524 525 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 526 sc->sc_rrun = 0; 527 return 0; 528 } 529 530 int 531 cs4281_getdev(addr, retp) 532 void *addr; 533 struct audio_device *retp; 534 { 535 *retp = cs4281_device; 536 return 0; 537 } 538 539 int 540 cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 541 void *addr; 542 void *start, *end; 543 int blksize; 544 void (*intr) __P((void *)); 545 void *arg; 546 struct audio_params *param; 547 { 548 struct cs428x_softc *sc = addr; 549 u_int32_t fmt=0; 550 struct cs428x_dma *p; 551 int dma_count; 552 553 #ifdef DIAGNOSTIC 554 if (sc->sc_prun) 555 printf("cs4281_trigger_output: already running\n"); 556 #endif 557 sc->sc_prun = 1; 558 559 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 560 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 561 sc->sc_pintr = intr; 562 sc->sc_parg = arg; 563 564 /* stop playback DMA */ 565 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 566 567 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 568 param->precision, param->factor, param->channels, 569 param->encoding)); 570 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 571 ; 572 if (p == NULL) { 573 printf("cs4281_trigger_output: bad addr %p\n", start); 574 return (EINVAL); 575 } 576 577 sc->sc_pcount = blksize / sc->hw_blocksize; 578 sc->sc_ps = (char *)start; 579 sc->sc_pe = (char *)end; 580 sc->sc_pdma = p; 581 sc->sc_pbuf = KERNADDR(p); 582 sc->sc_pi = 0; 583 sc->sc_pn = sc->sc_ps; 584 if (blksize >= sc->dma_size) { 585 sc->sc_pn = sc->sc_ps + sc->dma_size; 586 memcpy(sc->sc_pbuf, start, sc->dma_size); 587 ++sc->sc_pi; 588 } else { 589 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 590 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 591 } 592 593 dma_count = sc->dma_size; 594 if (param->precision * param->factor != 8) 595 dma_count /= 2; /* 16 bit */ 596 if (param->channels > 1) 597 dma_count /= 2; /* Stereo */ 598 599 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 600 (int)DMAADDR(p), dma_count)); 601 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 602 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 603 604 /* set playback format */ 605 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 606 if (param->precision * param->factor == 8) 607 fmt |= DMRn_SIZE8; 608 if (param->channels == 1) 609 fmt |= DMRn_MONO; 610 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 611 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 612 fmt |= DMRn_BEND; 613 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 614 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 615 fmt |= DMRn_USIGN; 616 BA0WRITE4(sc, CS4281_DMR0, fmt); 617 618 /* set sample rate */ 619 sc->sc_prate = param->sample_rate; 620 cs4281_set_dac_rate(sc, param->sample_rate); 621 622 /* start DMA */ 623 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 624 /* Enable interrupts */ 625 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 626 627 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 628 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 629 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 630 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 631 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 632 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 633 BA0READ4(sc, CS4281_DACSR))); 634 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 635 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 636 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 637 638 return 0; 639 } 640 641 int 642 cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 643 void *addr; 644 void *start, *end; 645 int blksize; 646 void (*intr) __P((void *)); 647 void *arg; 648 struct audio_params *param; 649 { 650 struct cs428x_softc *sc = addr; 651 struct cs428x_dma *p; 652 u_int32_t fmt=0; 653 int dma_count; 654 655 #ifdef DIAGNOSTIC 656 if (sc->sc_rrun) 657 printf("cs4281_trigger_input: already running\n"); 658 #endif 659 sc->sc_rrun = 1; 660 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 661 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 662 sc->sc_rintr = intr; 663 sc->sc_rarg = arg; 664 665 /* stop recording DMA */ 666 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 667 668 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 669 ; 670 if (!p) { 671 printf("cs4281_trigger_input: bad addr %p\n", start); 672 return (EINVAL); 673 } 674 675 sc->sc_rcount = blksize / sc->hw_blocksize; 676 sc->sc_rs = (char *)start; 677 sc->sc_re = (char *)end; 678 sc->sc_rdma = p; 679 sc->sc_rbuf = KERNADDR(p); 680 sc->sc_ri = 0; 681 sc->sc_rn = sc->sc_rs; 682 683 dma_count = sc->dma_size; 684 if (param->precision * param->factor == 8) 685 dma_count /= 2; 686 if (param->channels > 1) 687 dma_count /= 2; 688 689 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 690 (int)DMAADDR(p), dma_count)); 691 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 692 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 693 694 /* set recording format */ 695 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 696 if (param->precision * param->factor == 8) 697 fmt |= DMRn_SIZE8; 698 if (param->channels == 1) 699 fmt |= DMRn_MONO; 700 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 701 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 702 fmt |= DMRn_BEND; 703 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 704 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 705 fmt |= DMRn_USIGN; 706 BA0WRITE4(sc, CS4281_DMR1, fmt); 707 708 /* set sample rate */ 709 sc->sc_rrate = param->sample_rate; 710 cs4281_set_adc_rate(sc, param->sample_rate); 711 712 /* Start DMA */ 713 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 714 /* Enable interrupts */ 715 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 716 717 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 718 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 719 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 720 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 721 722 return 0; 723 } 724 725 /* Power Hook */ 726 void 727 cs4281_power(why, v) 728 int why; 729 void *v; 730 { 731 struct cs428x_softc *sc = (struct cs428x_softc *)v; 732 static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 733 static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 734 735 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 736 switch (why) { 737 case PWR_SUSPEND: 738 case PWR_STANDBY: 739 sc->sc_suspend = why; 740 741 /* save current playback status */ 742 if (sc->sc_prun) { 743 dcr0 = BA0READ4(sc, CS4281_DCR0); 744 dmr0 = BA0READ4(sc, CS4281_DMR0); 745 dbc0 = BA0READ4(sc, CS4281_DBC0); 746 dba0 = BA0READ4(sc, CS4281_DBA0); 747 } 748 749 /* save current capture status */ 750 if (sc->sc_rrun) { 751 dcr1 = BA0READ4(sc, CS4281_DCR1); 752 dmr1 = BA0READ4(sc, CS4281_DMR1); 753 dbc1 = BA0READ4(sc, CS4281_DBC1); 754 dba1 = BA0READ4(sc, CS4281_DBA1); 755 } 756 /* Stop DMA */ 757 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 758 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 759 break; 760 case PWR_RESUME: 761 if (sc->sc_suspend == PWR_RESUME) { 762 printf("cs4281_power: odd, resume without suspend.\n"); 763 sc->sc_suspend = why; 764 return; 765 } 766 sc->sc_suspend = why; 767 cs4281_init(sc,0); 768 cs4281_reset_codec(sc); 769 770 /* restore ac97 registers */ 771 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 772 773 /* restore DMA related status */ 774 if (sc->sc_prun) { 775 cs4281_set_dac_rate(sc, sc->sc_prate); 776 BA0WRITE4(sc, CS4281_DBA0, dba0); 777 BA0WRITE4(sc, CS4281_DBC0, dbc0); 778 BA0WRITE4(sc, CS4281_DMR0, dmr0); 779 BA0WRITE4(sc, CS4281_DCR0, dcr0); 780 } 781 if (sc->sc_rrun) { 782 cs4281_set_adc_rate(sc, sc->sc_rrate); 783 BA0WRITE4(sc, CS4281_DBA1, dba1); 784 BA0WRITE4(sc, CS4281_DBC1, dbc1); 785 BA0WRITE4(sc, CS4281_DMR1, dmr1); 786 BA0WRITE4(sc, CS4281_DCR1, dcr1); 787 } 788 /* enable intterupts */ 789 if (sc->sc_prun || sc->sc_rrun) 790 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 791 break; 792 case PWR_SOFTSUSPEND: 793 case PWR_SOFTSTANDBY: 794 case PWR_SOFTRESUME: 795 break; 796 } 797 } 798 799 /* control AC97 codec */ 800 void 801 cs4281_reset_codec(void *addr) 802 { 803 struct cs428x_softc *sc; 804 u_int16_t data; 805 u_int32_t dat32; 806 int n; 807 808 sc = addr; 809 810 DPRINTFN(3,("cs4281_reset_codec\n")); 811 812 /* Reset codec */ 813 BA0WRITE4(sc, CS428X_ACCTL, 0); 814 delay(50); /* delay 50us */ 815 816 BA0WRITE4(sc, CS4281_SPMC, 0); 817 delay(100); /* delay 100us */ 818 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 819 #if defined(ENABLE_SECONDARY_CODEC) 820 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 821 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 822 #endif 823 delay(50000); /* XXX: delay 50ms */ 824 825 /* Enable ASYNC generation */ 826 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 827 828 /* Wait for Codec ready. Linux driver wait 50ms here */ 829 n = 0; 830 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 831 delay(100); 832 if (++n > 1000) { 833 printf("reset_codec: AC97 codec ready timeout\n"); 834 return; 835 } 836 } 837 #if defined(ENABLE_SECONDARY_CODEC) 838 /* secondary codec ready*/ 839 n = 0; 840 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 841 delay(100); 842 if (++n > 1000) 843 return; 844 } 845 #endif 846 /* Set the serial timing configuration */ 847 /* XXX: undocumented but the Linux driver do this */ 848 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 849 850 /* Wait for Codec ready signal */ 851 n = 0; 852 do { 853 delay(1000); 854 if (++n > 1000) { 855 printf("%s: Timeout waiting for Codec ready\n", 856 sc->sc_dev.dv_xname); 857 return; 858 } 859 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 860 } while (dat32 == 0); 861 862 /* Enable Valid Frame output on ASDOUT */ 863 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 864 865 /* Wait until Codec Calibration is finished. Codec register 26h */ 866 n = 0; 867 do { 868 delay(1); 869 if (++n > 1000) { 870 printf("%s: Timeout waiting for Codec calibration\n", 871 sc->sc_dev.dv_xname); 872 return ; 873 } 874 cs428x_read_codec(sc, AC97_REG_POWER, &data); 875 } while ((data & 0x0f) != 0x0f); 876 877 /* Set the serial timing configuration again */ 878 /* XXX: undocumented but the Linux driver do this */ 879 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 880 881 /* Wait until we've sampled input slots 3 & 4 as valid */ 882 n = 0; 883 do { 884 delay(1000); 885 if (++n > 1000) { 886 printf("%s: Timeout waiting for sampled input slots as valid\n", 887 sc->sc_dev.dv_xname); 888 return; 889 } 890 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 891 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 892 893 /* Start digital data transfer of audio data to the codec */ 894 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 895 } 896 897 898 /* Internal functions */ 899 900 /* convert sample rate to register value */ 901 u_int8_t 902 cs4281_sr2regval(rate) 903 int rate; 904 { 905 u_int8_t retval; 906 907 /* We don't have to change here. but anyway ... */ 908 if (rate > 48000) 909 rate = 48000; 910 if (rate < 6023) 911 rate = 6023; 912 913 switch (rate) { 914 case 8000: 915 retval = 5; 916 break; 917 case 11025: 918 retval = 4; 919 break; 920 case 16000: 921 retval = 3; 922 break; 923 case 22050: 924 retval = 2; 925 break; 926 case 44100: 927 retval = 1; 928 break; 929 case 48000: 930 retval = 0; 931 break; 932 default: 933 retval = 1536000/rate; /* == 24576000/(rate*16) */ 934 } 935 return retval; 936 } 937 938 void 939 cs4281_set_adc_rate(sc, rate) 940 struct cs428x_softc *sc; 941 int rate; 942 { 943 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 944 } 945 946 void 947 cs4281_set_dac_rate(sc, rate) 948 struct cs428x_softc *sc; 949 int rate; 950 { 951 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 952 } 953 954 int 955 cs4281_init(sc, init) 956 struct cs428x_softc *sc; 957 int init; 958 { 959 int n; 960 u_int16_t data; 961 u_int32_t dat32; 962 963 /* set "Configuration Write Protect" register to 964 * 0x4281 to allow to write */ 965 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 966 967 /* 968 * Unset "Full Power-Down bit of Extended PCI Power Management 969 * Control" register to release the reset state. 970 */ 971 dat32 = BA0READ4(sc, CS4281_EPPMC); 972 if (dat32 & EPPMC_FPDN) { 973 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 974 } 975 976 /* Start PLL out in known state */ 977 BA0WRITE4(sc, CS4281_CLKCR1, 0); 978 /* Start serial ports out in known state */ 979 BA0WRITE4(sc, CS4281_SERMC, 0); 980 981 /* Reset codec */ 982 BA0WRITE4(sc, CS428X_ACCTL, 0); 983 delay(50); /* delay 50us */ 984 985 BA0WRITE4(sc, CS4281_SPMC, 0); 986 delay(100); /* delay 100us */ 987 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 988 #if defined(ENABLE_SECONDARY_CODEC) 989 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 990 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 991 #endif 992 delay(50000); /* XXX: delay 50ms */ 993 994 /* Turn on Sound System clocks based on ABITCLK */ 995 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 996 delay(50000); /* XXX: delay 50ms */ 997 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 998 999 /* Set enables for sections that are needed in the SSPM registers */ 1000 BA0WRITE4(sc, CS4281_SSPM, 1001 SSPM_MIXEN | /* Mixer */ 1002 SSPM_CSRCEN | /* Capture SRC */ 1003 SSPM_PSRCEN | /* Playback SRC */ 1004 SSPM_JSEN | /* Joystick */ 1005 SSPM_ACLEN | /* AC LINK */ 1006 SSPM_FMEN /* FM */ 1007 ); 1008 1009 /* Wait for clock stabilization */ 1010 n = 0; 1011 #if 1 1012 /* what document says */ 1013 while ( ( BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1014 != (CLKCR1_DLLRDY | CLKCR1_CLKON )) { 1015 delay(100); 1016 if ( ++n > 1000 ) 1017 return -1; 1018 } 1019 #else 1020 /* Cirrus driver for Linux does */ 1021 while ( !(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1022 delay(1000); 1023 if ( ++n > 1000 ) 1024 return -1; 1025 } 1026 #endif 1027 1028 /* Enable ASYNC generation */ 1029 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1030 1031 /* Wait for Codec ready. Linux driver wait 50ms here */ 1032 n = 0; 1033 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1034 delay(100); 1035 if (++n > 1000) 1036 return -1; 1037 } 1038 1039 #if defined(ENABLE_SECONDARY_CODEC) 1040 /* secondary codec ready*/ 1041 n = 0; 1042 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1043 delay(100); 1044 if (++n > 1000) 1045 return -1; 1046 } 1047 #endif 1048 1049 /* Set the serial timing configuration */ 1050 /* XXX: undocumented but the Linux driver do this */ 1051 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1052 1053 /* Wait for Codec ready signal */ 1054 n = 0; 1055 do { 1056 delay(1000); 1057 if (++n > 1000) { 1058 printf("%s: Timeout waiting for Codec ready\n", 1059 sc->sc_dev.dv_xname); 1060 return -1; 1061 } 1062 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1063 } while (dat32 == 0); 1064 1065 /* Enable Valid Frame output on ASDOUT */ 1066 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1067 1068 /* Wait until Codec Calibration is finished. Codec register 26h */ 1069 n = 0; 1070 do { 1071 delay(1); 1072 if (++n > 1000) { 1073 printf("%s: Timeout waiting for Codec calibration\n", 1074 sc->sc_dev.dv_xname); 1075 return -1; 1076 } 1077 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1078 } while ((data & 0x0f) != 0x0f); 1079 1080 /* Set the serial timing configuration again */ 1081 /* XXX: undocumented but the Linux driver do this */ 1082 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1083 1084 /* Wait until we've sampled input slots 3 & 4 as valid */ 1085 n = 0; 1086 do { 1087 delay(1000); 1088 if (++n > 1000) { 1089 printf("%s: Timeout waiting for sampled input slots as valid\n", 1090 sc->sc_dev.dv_xname); 1091 return -1; 1092 } 1093 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1094 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1095 1096 /* Start digital data transfer of audio data to the codec */ 1097 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1098 1099 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1100 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1101 1102 /* Power on the DAC */ 1103 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1104 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1105 1106 /* Wait until we sample a DAC ready state. 1107 * Not documented, but Linux driver does. 1108 */ 1109 for (n = 0; n < 32; ++n) { 1110 delay(1000); 1111 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1112 if (data & 0x02) 1113 break; 1114 } 1115 1116 /* Power on the ADC */ 1117 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1118 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1119 1120 /* Wait until we sample ADC ready state. 1121 * Not documented, but Linux driver does. 1122 */ 1123 for (n = 0; n < 32; ++n) { 1124 delay(1000); 1125 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1126 if (data & 0x01) 1127 break; 1128 } 1129 1130 #if 0 1131 /* Initialize AC-Link features */ 1132 /* variable sample-rate support */ 1133 mem = BA0READ4(sc, CS4281_SERMC); 1134 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1135 BA0WRITE4(sc, CS4281_SERMC, mem); 1136 /* XXX: more... */ 1137 1138 /* Initialize SSCR register features */ 1139 /* XXX: hardware volume setting */ 1140 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1141 #endif 1142 1143 /* disable Sound Blaster Pro emulation */ 1144 /* XXX: 1145 * Cannot set since the documents does not describe which bit is 1146 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1147 * we can ignore it.*/ 1148 #if 0 1149 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1150 #endif 1151 1152 /* map AC97 PCM playback to DMA Channel 0 */ 1153 /* Reset FEN bit to setup first */ 1154 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc,CS4281_FCR0) & ~FCRn_FEN)); 1155 /* 1156 *| RS[4:0]/| | 1157 *| LS[4:0] | AC97 | Slot Function 1158 *|---------+--------+-------------------- 1159 *| 0 | 3 | Left PCM Playback 1160 *| 1 | 4 | Right PCM Playback 1161 *| 2 | 5 | Phone Line 1 DAC 1162 *| 3 | 6 | Center PCM Playback 1163 *.... 1164 * quoted from Table 29(p109) 1165 */ 1166 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1167 0x00 << 16 | /* LS[4:0] = 0 see above */ 1168 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1169 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1170 BA0WRITE4(sc, CS4281_FCR0, dat32); 1171 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1172 1173 /* map AC97 PCM record to DMA Channel 1 */ 1174 /* Reset FEN bit to setup first */ 1175 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc,CS4281_FCR1) & ~FCRn_FEN)); 1176 /* 1177 *| RS[4:0]/| 1178 *| LS[4:0] | AC97 | Slot Function 1179 *|---------+------+------------------- 1180 *| 10 | 3 | Left PCM Record 1181 *| 11 | 4 | Right PCM Record 1182 *| 12 | 5 | Phone Line 1 ADC 1183 *| 13 | 6 | Mic ADC 1184 *.... 1185 * quoted from Table 30(p109) 1186 */ 1187 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1188 0x0a << 16 | /* LS[4:0] = 10 See above */ 1189 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1190 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1191 1192 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1193 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1194 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1195 1196 #if 0 1197 /* Disable DMA Channel 2, 3 */ 1198 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc,CS4281_FCR2) & ~FCRn_FEN)); 1199 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc,CS4281_FCR3) & ~FCRn_FEN)); 1200 #endif 1201 1202 /* Set the SRC Slot Assignment accordingly */ 1203 /*| PLSS[4:0]/ 1204 *| PRSS[4:0] | AC97 | Slot Function 1205 *|-----------+------+---------------- 1206 *| 0 | 3 | Left PCM Playback 1207 *| 1 | 4 | Right PCM Playback 1208 *| 2 | 5 | phone line 1 DAC 1209 *| 3 | 6 | Center PCM Playback 1210 *| 4 | 7 | Left Surround PCM Playback 1211 *| 5 | 8 | Right Surround PCM Playback 1212 *...... 1213 * 1214 *| CLSS[4:0]/ 1215 *| CRSS[4:0] | AC97 | Codec |Slot Function 1216 *|-----------+------+-------+----------------- 1217 *| 10 | 3 |Primary| Left PCM Record 1218 *| 11 | 4 |Primary| Right PCM Record 1219 *| 12 | 5 |Primary| Phone Line 1 ADC 1220 *| 13 | 6 |Primary| Mic ADC 1221 *|..... 1222 *| 20 | 3 | Sec. | Left PCM Record 1223 *| 21 | 4 | Sec. | Right PCM Record 1224 *| 22 | 5 | Sec. | Phone Line 1 ADC 1225 *| 23 | 6 | Sec. | Mic ADC 1226 */ 1227 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1228 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1229 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1230 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1231 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1232 1233 /* Set interrupt to occurred at Half and Full terminal 1234 * count interrupt enable for DMA channel 0 and 1. 1235 * To keep DMA stop, set MSK. 1236 */ 1237 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1238 BA0WRITE4(sc, CS4281_DCR0, dat32); 1239 BA0WRITE4(sc, CS4281_DCR1, dat32); 1240 1241 /* Set Auto-Initialize Contorl enable */ 1242 BA0WRITE4(sc, CS4281_DMR0, 1243 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1244 BA0WRITE4(sc, CS4281_DMR1, 1245 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1246 1247 /* Clear DMA Mask in HIMR */ 1248 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1249 BA0WRITE4(sc, CS4281_HIMR, 1250 BA0READ4(sc, CS4281_HIMR) & dat32); 1251 1252 /* set current status */ 1253 if (init != 0) { 1254 sc->sc_prun = 0; 1255 sc->sc_rrun = 0; 1256 } 1257 1258 /* setup playback volume */ 1259 BA0WRITE4(sc, CS4281_PPRVC, 7); 1260 BA0WRITE4(sc, CS4281_PPLVC, 7); 1261 1262 return 0; 1263 } 1264
Indexes created Thu Oct 02 10:09:58 GMT 2025