cs4281.c revision 1.44.12.1
1 /* $NetBSD: cs4281.c,v 1.44.12.1 2011/11/19 21:49:42 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.44.12.1 2011/11/19 21:49:42 jmcneill Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <sys/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(device_t, cfdata_t, void *); 84 static void cs4281_attach(device_t, device_t, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static bool cs4281_suspend(device_t, const pmf_qual_t *); 110 static bool cs4281_resume(device_t, const pmf_qual_t *); 111 112 static const struct audio_hw_if cs4281_hw_if = { 113 NULL, /* open */ 114 NULL, /* close */ 115 NULL, 116 cs4281_query_encoding, 117 cs4281_set_params, 118 cs428x_round_blocksize, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 NULL, 124 cs4281_halt_output, 125 cs4281_halt_input, 126 NULL, 127 cs4281_getdev, 128 NULL, 129 cs428x_mixer_set_port, 130 cs428x_mixer_get_port, 131 cs428x_query_devinfo, 132 cs428x_malloc, 133 cs428x_free, 134 cs428x_round_buffersize, 135 cs428x_mappage, 136 cs428x_get_props, 137 cs4281_trigger_output, 138 cs4281_trigger_input, 139 NULL, 140 NULL, 141 cs428x_get_locks, 142 }; 143 144 #if NMIDI > 0 && 0 145 /* Midi Interface */ 146 static void cs4281_midi_close(void*); 147 static void cs4281_midi_getinfo(void *, struct midi_info *); 148 static int cs4281_midi_open(void *, int, void (*)(void *, int), 149 void (*)(void *), void *); 150 static int cs4281_midi_output(void *, int); 151 152 static const struct midi_hw_if cs4281_midi_hw_if = { 153 cs4281_midi_open, 154 cs4281_midi_close, 155 cs4281_midi_output, 156 cs4281_midi_getinfo, 157 0, 158 cs428x_get_locks, 159 }; 160 #endif 161 162 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 163 cs4281_match, cs4281_attach, NULL, NULL); 164 165 static struct audio_device cs4281_device = { 166 "CS4281", 167 "", 168 "cs4281" 169 }; 170 171 172 static int 173 cs4281_match(device_t parent, cfdata_t match, void *aux) 174 { 175 struct pci_attach_args *pa; 176 177 pa = (struct pci_attach_args *)aux; 178 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 179 return 0; 180 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 181 return 1; 182 return 0; 183 } 184 185 static void 186 cs4281_attach(device_t parent, device_t self, void *aux) 187 { 188 struct cs428x_softc *sc; 189 struct pci_attach_args *pa; 190 pci_chipset_tag_t pc; 191 char const *intrstr; 192 pcireg_t reg; 193 char devinfo[256]; 194 int error; 195 196 sc = device_private(self); 197 pa = (struct pci_attach_args *)aux; 198 pc = pa->pa_pc; 199 aprint_naive(": Audio controller\n"); 200 201 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 202 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 203 PCI_REVISION(pa->pa_class)); 204 205 sc->sc_pc = pa->pa_pc; 206 sc->sc_pt = pa->pa_tag; 207 208 /* Map I/O register */ 209 if (pci_mapreg_map(pa, PCI_BA0, 210 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 211 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 212 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n"); 213 return; 214 } 215 if (pci_mapreg_map(pa, PCI_BA1, 216 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 217 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 218 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n"); 219 return; 220 } 221 222 sc->sc_dmatag = pa->pa_dmat; 223 224 /* power up chip */ 225 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 226 pci_activate_null)) && error != EOPNOTSUPP) { 227 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 228 return; 229 } 230 231 /* Enable the device (set bus master flag) */ 232 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 233 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 234 reg | PCI_COMMAND_MASTER_ENABLE); 235 236 #if 0 237 /* LATENCY_TIMER setting */ 238 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 239 if (PCI_LATTIMER(temp1) < 32) { 240 temp1 &= 0xffff00ff; 241 temp1 |= 0x00002000; 242 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 243 } 244 #endif 245 246 /* Map and establish the interrupt. */ 247 if (pci_intr_map(pa, &sc->intrh)) { 248 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 249 return; 250 } 251 intrstr = pci_intr_string(pc, sc->intrh); 252 253 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 254 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 255 256 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_SCHED, 257 cs4281_intr, sc); 258 if (sc->sc_ih == NULL) { 259 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 260 if (intrstr != NULL) 261 aprint_error(" at %s", intrstr); 262 aprint_error("\n"); 263 mutex_destroy(&sc->sc_lock); 264 mutex_destroy(&sc->sc_intr_lock); 265 return; 266 } 267 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 268 269 /* 270 * Sound System start-up 271 */ 272 if (cs4281_init(sc, 1) != 0) { 273 mutex_destroy(&sc->sc_lock); 274 mutex_destroy(&sc->sc_intr_lock); 275 return; 276 } 277 278 sc->type = TYPE_CS4281; 279 sc->halt_input = cs4281_halt_input; 280 sc->halt_output = cs4281_halt_output; 281 282 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 283 sc->dma_align = 0x10; 284 sc->hw_blocksize = sc->dma_size / 2; 285 286 /* AC 97 attachment */ 287 sc->host_if.arg = sc; 288 sc->host_if.attach = cs428x_attach_codec; 289 sc->host_if.read = cs428x_read_codec; 290 sc->host_if.write = cs428x_write_codec; 291 sc->host_if.reset = cs4281_reset_codec; 292 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 293 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n"); 294 mutex_destroy(&sc->sc_lock); 295 mutex_destroy(&sc->sc_intr_lock); 296 return; 297 } 298 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 299 300 #if NMIDI > 0 && 0 301 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 302 #endif 303 304 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 305 aprint_error_dev(self, "couldn't establish power handler\n"); 306 } 307 308 static int 309 cs4281_intr(void *p) 310 { 311 struct cs428x_softc *sc; 312 uint32_t intr, hdsr0, hdsr1; 313 char *empty_dma; 314 int handled; 315 316 sc = p; 317 handled = 0; 318 hdsr0 = 0; 319 hdsr1 = 0; 320 321 mutex_spin_enter(&sc->sc_intr_lock); 322 323 /* grab interrupt register */ 324 intr = BA0READ4(sc, CS4281_HISR); 325 326 DPRINTF(("cs4281_intr:")); 327 /* not for me */ 328 if ((intr & HISR_INTENA) == 0) { 329 /* clear the interrupt register */ 330 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 331 mutex_spin_exit(&sc->sc_intr_lock); 332 return 0; 333 } 334 335 if (intr & HISR_DMA0) 336 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 337 if (intr & HISR_DMA1) 338 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 339 /* clear the interrupt register */ 340 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 341 342 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 343 intr, hdsr0, hdsr1)); 344 345 /* Playback Interrupt */ 346 if (intr & HISR_DMA0) { 347 handled = 1; 348 if (sc->sc_prun) { 349 DPRINTF((" PB DMA 0x%x(%d)", 350 (int)BA0READ4(sc, CS4281_DCA0), 351 (int)BA0READ4(sc, CS4281_DCC0))); 352 if ((sc->sc_pi%sc->sc_pcount) == 0) 353 sc->sc_pintr(sc->sc_parg); 354 /* copy buffer */ 355 ++sc->sc_pi; 356 empty_dma = sc->sc_pdma->addr; 357 if (sc->sc_pi&1) 358 empty_dma += sc->hw_blocksize; 359 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 360 sc->sc_pn += sc->hw_blocksize; 361 if (sc->sc_pn >= sc->sc_pe) 362 sc->sc_pn = sc->sc_ps; 363 } else { 364 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n"); 365 } 366 } 367 if (intr & HISR_DMA1) { 368 handled = 1; 369 if (sc->sc_rrun) { 370 /* copy from DMA */ 371 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 372 (int)BA0READ4(sc, CS4281_DCC1))); 373 ++sc->sc_ri; 374 empty_dma = sc->sc_rdma->addr; 375 if ((sc->sc_ri & 1) == 0) 376 empty_dma += sc->hw_blocksize; 377 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 378 sc->sc_rn += sc->hw_blocksize; 379 if (sc->sc_rn >= sc->sc_re) 380 sc->sc_rn = sc->sc_rs; 381 if ((sc->sc_ri % sc->sc_rcount) == 0) 382 sc->sc_rintr(sc->sc_rarg); 383 } else { 384 aprint_error_dev(&sc->sc_dev, 385 "unexpected record intr\n"); 386 } 387 } 388 DPRINTF(("\n")); 389 390 mutex_spin_exit(&sc->sc_intr_lock); 391 392 return handled; 393 } 394 395 static int 396 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 397 { 398 399 switch (fp->index) { 400 case 0: 401 strcpy(fp->name, AudioEulinear); 402 fp->encoding = AUDIO_ENCODING_ULINEAR; 403 fp->precision = 8; 404 fp->flags = 0; 405 break; 406 case 1: 407 strcpy(fp->name, AudioEmulaw); 408 fp->encoding = AUDIO_ENCODING_ULAW; 409 fp->precision = 8; 410 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 411 break; 412 case 2: 413 strcpy(fp->name, AudioEalaw); 414 fp->encoding = AUDIO_ENCODING_ALAW; 415 fp->precision = 8; 416 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 417 break; 418 case 3: 419 strcpy(fp->name, AudioEslinear); 420 fp->encoding = AUDIO_ENCODING_SLINEAR; 421 fp->precision = 8; 422 fp->flags = 0; 423 break; 424 case 4: 425 strcpy(fp->name, AudioEslinear_le); 426 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 427 fp->precision = 16; 428 fp->flags = 0; 429 break; 430 case 5: 431 strcpy(fp->name, AudioEulinear_le); 432 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 433 fp->precision = 16; 434 fp->flags = 0; 435 break; 436 case 6: 437 strcpy(fp->name, AudioEslinear_be); 438 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 439 fp->precision = 16; 440 fp->flags = 0; 441 break; 442 case 7: 443 strcpy(fp->name, AudioEulinear_be); 444 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 445 fp->precision = 16; 446 fp->flags = 0; 447 break; 448 default: 449 return EINVAL; 450 } 451 return 0; 452 } 453 454 static int 455 cs4281_set_params(void *addr, int setmode, int usemode, 456 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 457 stream_filter_list_t *rfil) 458 { 459 audio_params_t hw; 460 struct cs428x_softc *sc; 461 audio_params_t *p; 462 stream_filter_list_t *fil; 463 int mode; 464 465 sc = addr; 466 for (mode = AUMODE_RECORD; mode != -1; 467 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 468 if ((setmode & mode) == 0) 469 continue; 470 471 p = mode == AUMODE_PLAY ? play : rec; 472 473 if (p == play) { 474 DPRINTFN(5, 475 ("play: sample=%u precision=%u channels=%u\n", 476 p->sample_rate, p->precision, p->channels)); 477 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 478 (p->precision != 8 && p->precision != 16) || 479 (p->channels != 1 && p->channels != 2)) { 480 return EINVAL; 481 } 482 } else { 483 DPRINTFN(5, 484 ("rec: sample=%u precision=%u channels=%u\n", 485 p->sample_rate, p->precision, p->channels)); 486 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 487 (p->precision != 8 && p->precision != 16) || 488 (p->channels != 1 && p->channels != 2)) { 489 return EINVAL; 490 } 491 } 492 hw = *p; 493 fil = mode == AUMODE_PLAY ? pfil : rfil; 494 495 switch (p->encoding) { 496 case AUDIO_ENCODING_SLINEAR_BE: 497 break; 498 case AUDIO_ENCODING_SLINEAR_LE: 499 break; 500 case AUDIO_ENCODING_ULINEAR_BE: 501 break; 502 case AUDIO_ENCODING_ULINEAR_LE: 503 break; 504 case AUDIO_ENCODING_ULAW: 505 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 506 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 507 : linear8_to_mulaw, &hw); 508 break; 509 case AUDIO_ENCODING_ALAW: 510 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 511 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 512 : linear8_to_alaw, &hw); 513 break; 514 default: 515 return EINVAL; 516 } 517 } 518 519 /* set sample rate */ 520 cs4281_set_dac_rate(sc, play->sample_rate); 521 cs4281_set_adc_rate(sc, rec->sample_rate); 522 return 0; 523 } 524 525 static int 526 cs4281_halt_output(void *addr) 527 { 528 struct cs428x_softc *sc; 529 530 sc = addr; 531 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 532 sc->sc_prun = 0; 533 return 0; 534 } 535 536 static int 537 cs4281_halt_input(void *addr) 538 { 539 struct cs428x_softc *sc; 540 541 sc = addr; 542 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 543 sc->sc_rrun = 0; 544 return 0; 545 } 546 547 static int 548 cs4281_getdev(void *addr, struct audio_device *retp) 549 { 550 551 *retp = cs4281_device; 552 return 0; 553 } 554 555 static int 556 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 557 void (*intr)(void *), void *arg, 558 const audio_params_t *param) 559 { 560 struct cs428x_softc *sc; 561 uint32_t fmt; 562 struct cs428x_dma *p; 563 int dma_count; 564 565 sc = addr; 566 fmt = 0; 567 #ifdef DIAGNOSTIC 568 if (sc->sc_prun) 569 printf("cs4281_trigger_output: already running\n"); 570 #endif 571 sc->sc_prun = 1; 572 573 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 574 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 575 sc->sc_pintr = intr; 576 sc->sc_parg = arg; 577 578 /* stop playback DMA */ 579 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 580 581 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 582 param->precision, param->channels, param->encoding)); 583 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 584 continue; 585 if (p == NULL) { 586 printf("cs4281_trigger_output: bad addr %p\n", start); 587 return EINVAL; 588 } 589 590 sc->sc_pcount = blksize / sc->hw_blocksize; 591 sc->sc_ps = (char *)start; 592 sc->sc_pe = (char *)end; 593 sc->sc_pdma = p; 594 sc->sc_pbuf = KERNADDR(p); 595 sc->sc_pi = 0; 596 sc->sc_pn = sc->sc_ps; 597 if (blksize >= sc->dma_size) { 598 sc->sc_pn = sc->sc_ps + sc->dma_size; 599 memcpy(sc->sc_pbuf, start, sc->dma_size); 600 ++sc->sc_pi; 601 } else { 602 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 603 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 604 } 605 606 dma_count = sc->dma_size; 607 if (param->precision != 8) 608 dma_count /= 2; /* 16 bit */ 609 if (param->channels > 1) 610 dma_count /= 2; /* Stereo */ 611 612 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 613 (int)DMAADDR(p), dma_count)); 614 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 615 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 616 617 /* set playback format */ 618 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 619 if (param->precision == 8) 620 fmt |= DMRn_SIZE8; 621 if (param->channels == 1) 622 fmt |= DMRn_MONO; 623 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 624 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 625 fmt |= DMRn_BEND; 626 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 627 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 628 fmt |= DMRn_USIGN; 629 BA0WRITE4(sc, CS4281_DMR0, fmt); 630 631 /* set sample rate */ 632 sc->sc_prate = param->sample_rate; 633 cs4281_set_dac_rate(sc, param->sample_rate); 634 635 /* start DMA */ 636 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 637 /* Enable interrupts */ 638 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 639 640 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 641 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 642 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 643 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 644 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 645 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 646 BA0READ4(sc, CS4281_DACSR))); 647 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 648 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 649 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 650 651 return 0; 652 } 653 654 static int 655 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 656 void (*intr)(void *), void *arg, 657 const audio_params_t *param) 658 { 659 struct cs428x_softc *sc; 660 struct cs428x_dma *p; 661 uint32_t fmt; 662 int dma_count; 663 664 sc = addr; 665 fmt = 0; 666 #ifdef DIAGNOSTIC 667 if (sc->sc_rrun) 668 printf("cs4281_trigger_input: already running\n"); 669 #endif 670 sc->sc_rrun = 1; 671 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 672 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 673 sc->sc_rintr = intr; 674 sc->sc_rarg = arg; 675 676 /* stop recording DMA */ 677 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 678 679 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 680 continue; 681 if (!p) { 682 printf("cs4281_trigger_input: bad addr %p\n", start); 683 return EINVAL; 684 } 685 686 sc->sc_rcount = blksize / sc->hw_blocksize; 687 sc->sc_rs = (char *)start; 688 sc->sc_re = (char *)end; 689 sc->sc_rdma = p; 690 sc->sc_rbuf = KERNADDR(p); 691 sc->sc_ri = 0; 692 sc->sc_rn = sc->sc_rs; 693 694 dma_count = sc->dma_size; 695 if (param->precision != 8) 696 dma_count /= 2; 697 if (param->channels > 1) 698 dma_count /= 2; 699 700 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 701 (int)DMAADDR(p), dma_count)); 702 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 703 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 704 705 /* set recording format */ 706 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 707 if (param->precision == 8) 708 fmt |= DMRn_SIZE8; 709 if (param->channels == 1) 710 fmt |= DMRn_MONO; 711 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 712 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 713 fmt |= DMRn_BEND; 714 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 715 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 716 fmt |= DMRn_USIGN; 717 BA0WRITE4(sc, CS4281_DMR1, fmt); 718 719 /* set sample rate */ 720 sc->sc_rrate = param->sample_rate; 721 cs4281_set_adc_rate(sc, param->sample_rate); 722 723 /* Start DMA */ 724 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 725 /* Enable interrupts */ 726 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 727 728 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 729 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 730 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 731 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 732 733 return 0; 734 } 735 736 static bool 737 cs4281_suspend(device_t dv, const pmf_qual_t *qual) 738 { 739 struct cs428x_softc *sc = device_private(dv); 740 741 mutex_enter(&sc->sc_lock); 742 mutex_spin_exit(&sc->sc_intr_lock); 743 744 /* save current playback status */ 745 if (sc->sc_prun) { 746 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 747 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 748 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 749 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 750 } 751 752 /* save current capture status */ 753 if (sc->sc_rrun) { 754 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 755 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 756 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 757 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 758 } 759 /* Stop DMA */ 760 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 761 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 762 763 mutex_spin_exit(&sc->sc_intr_lock); 764 mutex_exit(&sc->sc_lock); 765 766 return true; 767 } 768 769 static bool 770 cs4281_resume(device_t dv, const pmf_qual_t *qual) 771 { 772 struct cs428x_softc *sc = device_private(dv); 773 774 mutex_enter(&sc->sc_lock); 775 mutex_spin_enter(&sc->sc_intr_lock); 776 777 cs4281_init(sc, 0); 778 cs4281_reset_codec(sc); 779 780 /* restore ac97 registers */ 781 mutex_spin_exit(&sc->sc_intr_lock); 782 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 783 mutex_spin_enter(&sc->sc_intr_lock); 784 785 /* restore DMA related status */ 786 if (sc->sc_prun) { 787 cs4281_set_dac_rate(sc, sc->sc_prate); 788 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 789 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 790 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 791 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 792 } 793 if (sc->sc_rrun) { 794 cs4281_set_adc_rate(sc, sc->sc_rrate); 795 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 796 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 797 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 798 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 799 } 800 /* enable intterupts */ 801 if (sc->sc_prun || sc->sc_rrun) 802 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 803 804 mutex_spin_exit(&sc->sc_intr_lock); 805 mutex_exit(&sc->sc_lock); 806 807 return true; 808 } 809 810 /* control AC97 codec */ 811 static int 812 cs4281_reset_codec(void *addr) 813 { 814 struct cs428x_softc *sc; 815 uint16_t data; 816 uint32_t dat32; 817 int n; 818 819 sc = addr; 820 821 DPRINTFN(3, ("cs4281_reset_codec\n")); 822 823 /* Reset codec */ 824 BA0WRITE4(sc, CS428X_ACCTL, 0); 825 delay(50); /* delay 50us */ 826 827 BA0WRITE4(sc, CS4281_SPMC, 0); 828 delay(100); /* delay 100us */ 829 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 830 #if defined(ENABLE_SECONDARY_CODEC) 831 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 832 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 833 #endif 834 delay(50000); /* XXX: delay 50ms */ 835 836 /* Enable ASYNC generation */ 837 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 838 839 /* Wait for codec ready. Linux driver waits 50ms here */ 840 n = 0; 841 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 842 delay(100); 843 if (++n > 1000) { 844 printf("reset_codec: AC97 codec ready timeout\n"); 845 return ETIMEDOUT; 846 } 847 } 848 #if defined(ENABLE_SECONDARY_CODEC) 849 /* secondary codec ready*/ 850 n = 0; 851 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 852 delay(100); 853 if (++n > 1000) 854 return 0; 855 } 856 #endif 857 /* Set the serial timing configuration */ 858 /* XXX: undocumented but the Linux driver do this */ 859 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 860 861 /* Wait for codec ready signal */ 862 n = 0; 863 do { 864 delay(1000); 865 if (++n > 1000) { 866 aprint_error_dev(&sc->sc_dev, 867 "timeout waiting for codec ready\n"); 868 return ETIMEDOUT; 869 } 870 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 871 } while (dat32 == 0); 872 873 /* Enable Valid Frame output on ASDOUT */ 874 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 875 876 /* Wait until codec calibration is finished. Codec register 26h */ 877 n = 0; 878 do { 879 delay(1); 880 if (++n > 1000) { 881 aprint_error_dev(&sc->sc_dev, 882 "timeout waiting for codec calibration\n"); 883 return ETIMEDOUT; 884 } 885 cs428x_read_codec(sc, AC97_REG_POWER, &data); 886 } while ((data & 0x0f) != 0x0f); 887 888 /* Set the serial timing configuration again */ 889 /* XXX: undocumented but the Linux driver do this */ 890 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 891 892 /* Wait until we've sampled input slots 3 & 4 as valid */ 893 n = 0; 894 do { 895 delay(1000); 896 if (++n > 1000) { 897 aprint_error_dev(&sc->sc_dev, "timeout waiting for " 898 "sampled input slots as valid\n"); 899 return ETIMEDOUT; 900 } 901 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 902 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 903 904 /* Start digital data transfer of audio data to the codec */ 905 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 906 return 0; 907 } 908 909 910 /* Internal functions */ 911 912 /* convert sample rate to register value */ 913 static uint8_t 914 cs4281_sr2regval(int rate) 915 { 916 uint8_t retval; 917 918 /* We don't have to change here. but anyway ... */ 919 if (rate > 48000) 920 rate = 48000; 921 if (rate < 6023) 922 rate = 6023; 923 924 switch (rate) { 925 case 8000: 926 retval = 5; 927 break; 928 case 11025: 929 retval = 4; 930 break; 931 case 16000: 932 retval = 3; 933 break; 934 case 22050: 935 retval = 2; 936 break; 937 case 44100: 938 retval = 1; 939 break; 940 case 48000: 941 retval = 0; 942 break; 943 default: 944 retval = 1536000/rate; /* == 24576000/(rate*16) */ 945 } 946 return retval; 947 } 948 949 static void 950 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 951 { 952 953 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 954 } 955 956 static void 957 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 958 { 959 960 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 961 } 962 963 static int 964 cs4281_init(struct cs428x_softc *sc, int init) 965 { 966 int n; 967 uint16_t data; 968 uint32_t dat32; 969 970 /* set "Configuration Write Protect" register to 971 * 0x4281 to allow to write */ 972 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 973 974 /* 975 * Unset "Full Power-Down bit of Extended PCI Power Management 976 * Control" register to release the reset state. 977 */ 978 dat32 = BA0READ4(sc, CS4281_EPPMC); 979 if (dat32 & EPPMC_FPDN) { 980 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 981 } 982 983 /* Start PLL out in known state */ 984 BA0WRITE4(sc, CS4281_CLKCR1, 0); 985 /* Start serial ports out in known state */ 986 BA0WRITE4(sc, CS4281_SERMC, 0); 987 988 /* Reset codec */ 989 BA0WRITE4(sc, CS428X_ACCTL, 0); 990 delay(50); /* delay 50us */ 991 992 BA0WRITE4(sc, CS4281_SPMC, 0); 993 delay(100); /* delay 100us */ 994 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 995 #if defined(ENABLE_SECONDARY_CODEC) 996 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 997 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 998 #endif 999 delay(50000); /* XXX: delay 50ms */ 1000 1001 /* Turn on Sound System clocks based on ABITCLK */ 1002 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 1003 delay(50000); /* XXX: delay 50ms */ 1004 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1005 1006 /* Set enables for sections that are needed in the SSPM registers */ 1007 BA0WRITE4(sc, CS4281_SSPM, 1008 SSPM_MIXEN | /* Mixer */ 1009 SSPM_CSRCEN | /* Capture SRC */ 1010 SSPM_PSRCEN | /* Playback SRC */ 1011 SSPM_JSEN | /* Joystick */ 1012 SSPM_ACLEN | /* AC LINK */ 1013 SSPM_FMEN /* FM */ 1014 ); 1015 1016 /* Wait for clock stabilization */ 1017 n = 0; 1018 #if 1 1019 /* what document says */ 1020 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1021 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1022 delay(100); 1023 if (++n > 1000) { 1024 aprint_error_dev(&sc->sc_dev, 1025 "timeout waiting for clock stabilization\n"); 1026 return -1; 1027 } 1028 } 1029 #else 1030 /* Cirrus driver for Linux does */ 1031 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1032 delay(1000); 1033 if (++n > 1000) { 1034 aprint_error_dev(&sc->sc_dev, 1035 "timeout waiting for clock stabilization\n"); 1036 return -1; 1037 } 1038 } 1039 #endif 1040 1041 /* Enable ASYNC generation */ 1042 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1043 1044 /* Wait for codec ready. Linux driver waits 50ms here */ 1045 n = 0; 1046 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1047 delay(100); 1048 if (++n > 1000) { 1049 aprint_error_dev(&sc->sc_dev, 1050 "timeout waiting for codec ready\n"); 1051 return -1; 1052 } 1053 } 1054 1055 #if defined(ENABLE_SECONDARY_CODEC) 1056 /* secondary codec ready*/ 1057 n = 0; 1058 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1059 delay(100); 1060 if (++n > 1000) { 1061 aprint_error_dev(&sc->sc_dev, 1062 "timeout waiting for secondary codec ready\n"); 1063 return -1; 1064 } 1065 } 1066 #endif 1067 1068 /* Set the serial timing configuration */ 1069 /* XXX: undocumented but the Linux driver do this */ 1070 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1071 1072 /* Wait for codec ready signal */ 1073 n = 0; 1074 do { 1075 delay(1000); 1076 if (++n > 1000) { 1077 aprint_error_dev(&sc->sc_dev, 1078 "timeout waiting for codec ready\n"); 1079 return -1; 1080 } 1081 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1082 } while (dat32 == 0); 1083 1084 /* Enable Valid Frame output on ASDOUT */ 1085 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1086 1087 /* Wait until codec calibration is finished. codec register 26h */ 1088 n = 0; 1089 do { 1090 delay(1); 1091 if (++n > 1000) { 1092 aprint_error_dev(&sc->sc_dev, 1093 "timeout waiting for codec calibration\n"); 1094 return -1; 1095 } 1096 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1097 } while ((data & 0x0f) != 0x0f); 1098 1099 /* Set the serial timing configuration again */ 1100 /* XXX: undocumented but the Linux driver do this */ 1101 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1102 1103 /* Wait until we've sampled input slots 3 & 4 as valid */ 1104 n = 0; 1105 do { 1106 delay(1000); 1107 if (++n > 1000) { 1108 aprint_error_dev(&sc->sc_dev, "timeout waiting for " 1109 "sampled input slots as valid\n"); 1110 return -1; 1111 } 1112 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1113 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1114 1115 /* Start digital data transfer of audio data to the codec */ 1116 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1117 1118 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1119 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1120 1121 /* Power on the DAC */ 1122 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1123 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1124 1125 /* Wait until we sample a DAC ready state. 1126 * Not documented, but Linux driver does. 1127 */ 1128 for (n = 0; n < 32; ++n) { 1129 delay(1000); 1130 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1131 if (data & 0x02) 1132 break; 1133 } 1134 1135 /* Power on the ADC */ 1136 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1137 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1138 1139 /* Wait until we sample ADC ready state. 1140 * Not documented, but Linux driver does. 1141 */ 1142 for (n = 0; n < 32; ++n) { 1143 delay(1000); 1144 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1145 if (data & 0x01) 1146 break; 1147 } 1148 1149 #if 0 1150 /* Initialize AC-Link features */ 1151 /* variable sample-rate support */ 1152 mem = BA0READ4(sc, CS4281_SERMC); 1153 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1154 BA0WRITE4(sc, CS4281_SERMC, mem); 1155 /* XXX: more... */ 1156 1157 /* Initialize SSCR register features */ 1158 /* XXX: hardware volume setting */ 1159 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1160 #endif 1161 1162 /* disable Sound Blaster Pro emulation */ 1163 /* XXX: 1164 * Cannot set since the documents does not describe which bit is 1165 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1166 * we can ignore it.*/ 1167 #if 0 1168 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1169 #endif 1170 1171 /* map AC97 PCM playback to DMA Channel 0 */ 1172 /* Reset FEN bit to setup first */ 1173 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1174 /* 1175 *| RS[4:0]/| | 1176 *| LS[4:0] | AC97 | Slot Function 1177 *|---------+--------+-------------------- 1178 *| 0 | 3 | Left PCM Playback 1179 *| 1 | 4 | Right PCM Playback 1180 *| 2 | 5 | Phone Line 1 DAC 1181 *| 3 | 6 | Center PCM Playback 1182 *.... 1183 * quoted from Table 29(p109) 1184 */ 1185 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1186 0x00 << 16 | /* LS[4:0] = 0 see above */ 1187 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1188 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1189 BA0WRITE4(sc, CS4281_FCR0, dat32); 1190 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1191 1192 /* map AC97 PCM record to DMA Channel 1 */ 1193 /* Reset FEN bit to setup first */ 1194 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1195 /* 1196 *| RS[4:0]/| 1197 *| LS[4:0] | AC97 | Slot Function 1198 *|---------+------+------------------- 1199 *| 10 | 3 | Left PCM Record 1200 *| 11 | 4 | Right PCM Record 1201 *| 12 | 5 | Phone Line 1 ADC 1202 *| 13 | 6 | Mic ADC 1203 *.... 1204 * quoted from Table 30(p109) 1205 */ 1206 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1207 0x0a << 16 | /* LS[4:0] = 10 See above */ 1208 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1209 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1210 1211 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1212 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1213 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1214 1215 #if 0 1216 /* Disable DMA Channel 2, 3 */ 1217 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1218 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1219 #endif 1220 1221 /* Set the SRC Slot Assignment accordingly */ 1222 /*| PLSS[4:0]/ 1223 *| PRSS[4:0] | AC97 | Slot Function 1224 *|-----------+------+---------------- 1225 *| 0 | 3 | Left PCM Playback 1226 *| 1 | 4 | Right PCM Playback 1227 *| 2 | 5 | phone line 1 DAC 1228 *| 3 | 6 | Center PCM Playback 1229 *| 4 | 7 | Left Surround PCM Playback 1230 *| 5 | 8 | Right Surround PCM Playback 1231 *...... 1232 * 1233 *| CLSS[4:0]/ 1234 *| CRSS[4:0] | AC97 | Codec |Slot Function 1235 *|-----------+------+-------+----------------- 1236 *| 10 | 3 |Primary| Left PCM Record 1237 *| 11 | 4 |Primary| Right PCM Record 1238 *| 12 | 5 |Primary| Phone Line 1 ADC 1239 *| 13 | 6 |Primary| Mic ADC 1240 *|..... 1241 *| 20 | 3 | Sec. | Left PCM Record 1242 *| 21 | 4 | Sec. | Right PCM Record 1243 *| 22 | 5 | Sec. | Phone Line 1 ADC 1244 *| 23 | 6 | Sec. | Mic ADC 1245 */ 1246 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1247 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1248 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1249 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1250 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1251 1252 /* Set interrupt to occurred at Half and Full terminal 1253 * count interrupt enable for DMA channel 0 and 1. 1254 * To keep DMA stop, set MSK. 1255 */ 1256 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1257 BA0WRITE4(sc, CS4281_DCR0, dat32); 1258 BA0WRITE4(sc, CS4281_DCR1, dat32); 1259 1260 /* Set Auto-Initialize Contorl enable */ 1261 BA0WRITE4(sc, CS4281_DMR0, 1262 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1263 BA0WRITE4(sc, CS4281_DMR1, 1264 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1265 1266 /* Clear DMA Mask in HIMR */ 1267 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1268 BA0WRITE4(sc, CS4281_HIMR, 1269 BA0READ4(sc, CS4281_HIMR) & dat32); 1270 1271 /* set current status */ 1272 if (init != 0) { 1273 sc->sc_prun = 0; 1274 sc->sc_rrun = 0; 1275 } 1276 1277 /* setup playback volume */ 1278 BA0WRITE4(sc, CS4281_PPRVC, 7); 1279 BA0WRITE4(sc, CS4281_PPLVC, 7); 1280 1281 return 0; 1282 } 1283
Indexes created Thu Oct 02 07:10:07 GMT 2025