cs4281.c revision 1.47
1 /* $NetBSD: cs4281.c,v 1.47 2012/01/30 19:41:19 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.47 2012/01/30 19:41:19 drochner Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <sys/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(device_t, cfdata_t, void *); 84 static void cs4281_attach(device_t, device_t, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static bool cs4281_suspend(device_t, const pmf_qual_t *); 110 static bool cs4281_resume(device_t, const pmf_qual_t *); 111 112 static const struct audio_hw_if cs4281_hw_if = { 113 NULL, /* open */ 114 NULL, /* close */ 115 NULL, 116 cs4281_query_encoding, 117 cs4281_set_params, 118 cs428x_round_blocksize, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 NULL, 124 cs4281_halt_output, 125 cs4281_halt_input, 126 NULL, 127 cs4281_getdev, 128 NULL, 129 cs428x_mixer_set_port, 130 cs428x_mixer_get_port, 131 cs428x_query_devinfo, 132 cs428x_malloc, 133 cs428x_free, 134 cs428x_round_buffersize, 135 cs428x_mappage, 136 cs428x_get_props, 137 cs4281_trigger_output, 138 cs4281_trigger_input, 139 NULL, 140 cs428x_get_locks, 141 }; 142 143 #if NMIDI > 0 && 0 144 /* Midi Interface */ 145 static void cs4281_midi_close(void*); 146 static void cs4281_midi_getinfo(void *, struct midi_info *); 147 static int cs4281_midi_open(void *, int, void (*)(void *, int), 148 void (*)(void *), void *); 149 static int cs4281_midi_output(void *, int); 150 151 static const struct midi_hw_if cs4281_midi_hw_if = { 152 cs4281_midi_open, 153 cs4281_midi_close, 154 cs4281_midi_output, 155 cs4281_midi_getinfo, 156 0, 157 cs428x_get_locks, 158 }; 159 #endif 160 161 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 162 cs4281_match, cs4281_attach, NULL, NULL); 163 164 static struct audio_device cs4281_device = { 165 "CS4281", 166 "", 167 "cs4281" 168 }; 169 170 171 static int 172 cs4281_match(device_t parent, cfdata_t match, void *aux) 173 { 174 struct pci_attach_args *pa; 175 176 pa = (struct pci_attach_args *)aux; 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 178 return 0; 179 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 180 return 1; 181 return 0; 182 } 183 184 static void 185 cs4281_attach(device_t parent, device_t self, void *aux) 186 { 187 struct cs428x_softc *sc; 188 struct pci_attach_args *pa; 189 pci_chipset_tag_t pc; 190 char const *intrstr; 191 pcireg_t reg; 192 int error; 193 194 sc = device_private(self); 195 pa = (struct pci_attach_args *)aux; 196 pc = pa->pa_pc; 197 198 pci_aprint_devinfo(pa, "Audio controller"); 199 200 sc->sc_pc = pa->pa_pc; 201 sc->sc_pt = pa->pa_tag; 202 203 /* Map I/O register */ 204 if (pci_mapreg_map(pa, PCI_BA0, 205 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 206 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 207 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n"); 208 return; 209 } 210 if (pci_mapreg_map(pa, PCI_BA1, 211 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 212 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 213 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n"); 214 return; 215 } 216 217 sc->sc_dmatag = pa->pa_dmat; 218 219 /* power up chip */ 220 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 221 pci_activate_null)) && error != EOPNOTSUPP) { 222 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 223 return; 224 } 225 226 /* Enable the device (set bus master flag) */ 227 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 228 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 229 reg | PCI_COMMAND_MASTER_ENABLE); 230 231 #if 0 232 /* LATENCY_TIMER setting */ 233 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 234 if (PCI_LATTIMER(temp1) < 32) { 235 temp1 &= 0xffff00ff; 236 temp1 |= 0x00002000; 237 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 238 } 239 #endif 240 241 /* Map and establish the interrupt. */ 242 if (pci_intr_map(pa, &sc->intrh)) { 243 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 244 return; 245 } 246 intrstr = pci_intr_string(pc, sc->intrh); 247 248 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 249 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 250 251 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 252 cs4281_intr, sc); 253 if (sc->sc_ih == NULL) { 254 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 255 if (intrstr != NULL) 256 aprint_error(" at %s", intrstr); 257 aprint_error("\n"); 258 mutex_destroy(&sc->sc_lock); 259 mutex_destroy(&sc->sc_intr_lock); 260 return; 261 } 262 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 263 264 /* 265 * Sound System start-up 266 */ 267 if (cs4281_init(sc, 1) != 0) { 268 mutex_destroy(&sc->sc_lock); 269 mutex_destroy(&sc->sc_intr_lock); 270 return; 271 } 272 273 sc->type = TYPE_CS4281; 274 sc->halt_input = cs4281_halt_input; 275 sc->halt_output = cs4281_halt_output; 276 277 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 278 sc->dma_align = 0x10; 279 sc->hw_blocksize = sc->dma_size / 2; 280 281 /* AC 97 attachment */ 282 sc->host_if.arg = sc; 283 sc->host_if.attach = cs428x_attach_codec; 284 sc->host_if.read = cs428x_read_codec; 285 sc->host_if.write = cs428x_write_codec; 286 sc->host_if.reset = cs4281_reset_codec; 287 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 288 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n"); 289 mutex_destroy(&sc->sc_lock); 290 mutex_destroy(&sc->sc_intr_lock); 291 return; 292 } 293 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 294 295 #if NMIDI > 0 && 0 296 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 297 #endif 298 299 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 300 aprint_error_dev(self, "couldn't establish power handler\n"); 301 } 302 303 static int 304 cs4281_intr(void *p) 305 { 306 struct cs428x_softc *sc; 307 uint32_t intr, hdsr0, hdsr1; 308 char *empty_dma; 309 int handled; 310 311 sc = p; 312 handled = 0; 313 hdsr0 = 0; 314 hdsr1 = 0; 315 316 mutex_spin_enter(&sc->sc_intr_lock); 317 318 /* grab interrupt register */ 319 intr = BA0READ4(sc, CS4281_HISR); 320 321 DPRINTF(("cs4281_intr:")); 322 /* not for me */ 323 if ((intr & HISR_INTENA) == 0) { 324 /* clear the interrupt register */ 325 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 326 mutex_spin_exit(&sc->sc_intr_lock); 327 return 0; 328 } 329 330 if (intr & HISR_DMA0) 331 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 332 if (intr & HISR_DMA1) 333 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 334 /* clear the interrupt register */ 335 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 336 337 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 338 intr, hdsr0, hdsr1)); 339 340 /* Playback Interrupt */ 341 if (intr & HISR_DMA0) { 342 handled = 1; 343 if (sc->sc_prun) { 344 DPRINTF((" PB DMA 0x%x(%d)", 345 (int)BA0READ4(sc, CS4281_DCA0), 346 (int)BA0READ4(sc, CS4281_DCC0))); 347 if ((sc->sc_pi%sc->sc_pcount) == 0) 348 sc->sc_pintr(sc->sc_parg); 349 /* copy buffer */ 350 ++sc->sc_pi; 351 empty_dma = sc->sc_pdma->addr; 352 if (sc->sc_pi&1) 353 empty_dma += sc->hw_blocksize; 354 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 355 sc->sc_pn += sc->hw_blocksize; 356 if (sc->sc_pn >= sc->sc_pe) 357 sc->sc_pn = sc->sc_ps; 358 } else { 359 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n"); 360 } 361 } 362 if (intr & HISR_DMA1) { 363 handled = 1; 364 if (sc->sc_rrun) { 365 /* copy from DMA */ 366 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 367 (int)BA0READ4(sc, CS4281_DCC1))); 368 ++sc->sc_ri; 369 empty_dma = sc->sc_rdma->addr; 370 if ((sc->sc_ri & 1) == 0) 371 empty_dma += sc->hw_blocksize; 372 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 373 sc->sc_rn += sc->hw_blocksize; 374 if (sc->sc_rn >= sc->sc_re) 375 sc->sc_rn = sc->sc_rs; 376 if ((sc->sc_ri % sc->sc_rcount) == 0) 377 sc->sc_rintr(sc->sc_rarg); 378 } else { 379 aprint_error_dev(&sc->sc_dev, 380 "unexpected record intr\n"); 381 } 382 } 383 DPRINTF(("\n")); 384 385 mutex_spin_exit(&sc->sc_intr_lock); 386 387 return handled; 388 } 389 390 static int 391 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 392 { 393 394 switch (fp->index) { 395 case 0: 396 strcpy(fp->name, AudioEulinear); 397 fp->encoding = AUDIO_ENCODING_ULINEAR; 398 fp->precision = 8; 399 fp->flags = 0; 400 break; 401 case 1: 402 strcpy(fp->name, AudioEmulaw); 403 fp->encoding = AUDIO_ENCODING_ULAW; 404 fp->precision = 8; 405 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 406 break; 407 case 2: 408 strcpy(fp->name, AudioEalaw); 409 fp->encoding = AUDIO_ENCODING_ALAW; 410 fp->precision = 8; 411 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 412 break; 413 case 3: 414 strcpy(fp->name, AudioEslinear); 415 fp->encoding = AUDIO_ENCODING_SLINEAR; 416 fp->precision = 8; 417 fp->flags = 0; 418 break; 419 case 4: 420 strcpy(fp->name, AudioEslinear_le); 421 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 422 fp->precision = 16; 423 fp->flags = 0; 424 break; 425 case 5: 426 strcpy(fp->name, AudioEulinear_le); 427 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 428 fp->precision = 16; 429 fp->flags = 0; 430 break; 431 case 6: 432 strcpy(fp->name, AudioEslinear_be); 433 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 434 fp->precision = 16; 435 fp->flags = 0; 436 break; 437 case 7: 438 strcpy(fp->name, AudioEulinear_be); 439 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 440 fp->precision = 16; 441 fp->flags = 0; 442 break; 443 default: 444 return EINVAL; 445 } 446 return 0; 447 } 448 449 static int 450 cs4281_set_params(void *addr, int setmode, int usemode, 451 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 452 stream_filter_list_t *rfil) 453 { 454 audio_params_t hw; 455 struct cs428x_softc *sc; 456 audio_params_t *p; 457 stream_filter_list_t *fil; 458 int mode; 459 460 sc = addr; 461 for (mode = AUMODE_RECORD; mode != -1; 462 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 463 if ((setmode & mode) == 0) 464 continue; 465 466 p = mode == AUMODE_PLAY ? play : rec; 467 468 if (p == play) { 469 DPRINTFN(5, 470 ("play: sample=%u precision=%u channels=%u\n", 471 p->sample_rate, p->precision, p->channels)); 472 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 473 (p->precision != 8 && p->precision != 16) || 474 (p->channels != 1 && p->channels != 2)) { 475 return EINVAL; 476 } 477 } else { 478 DPRINTFN(5, 479 ("rec: sample=%u precision=%u channels=%u\n", 480 p->sample_rate, p->precision, p->channels)); 481 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 482 (p->precision != 8 && p->precision != 16) || 483 (p->channels != 1 && p->channels != 2)) { 484 return EINVAL; 485 } 486 } 487 hw = *p; 488 fil = mode == AUMODE_PLAY ? pfil : rfil; 489 490 switch (p->encoding) { 491 case AUDIO_ENCODING_SLINEAR_BE: 492 break; 493 case AUDIO_ENCODING_SLINEAR_LE: 494 break; 495 case AUDIO_ENCODING_ULINEAR_BE: 496 break; 497 case AUDIO_ENCODING_ULINEAR_LE: 498 break; 499 case AUDIO_ENCODING_ULAW: 500 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 501 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 502 : linear8_to_mulaw, &hw); 503 break; 504 case AUDIO_ENCODING_ALAW: 505 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 506 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 507 : linear8_to_alaw, &hw); 508 break; 509 default: 510 return EINVAL; 511 } 512 } 513 514 /* set sample rate */ 515 cs4281_set_dac_rate(sc, play->sample_rate); 516 cs4281_set_adc_rate(sc, rec->sample_rate); 517 return 0; 518 } 519 520 static int 521 cs4281_halt_output(void *addr) 522 { 523 struct cs428x_softc *sc; 524 525 sc = addr; 526 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 527 sc->sc_prun = 0; 528 return 0; 529 } 530 531 static int 532 cs4281_halt_input(void *addr) 533 { 534 struct cs428x_softc *sc; 535 536 sc = addr; 537 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 538 sc->sc_rrun = 0; 539 return 0; 540 } 541 542 static int 543 cs4281_getdev(void *addr, struct audio_device *retp) 544 { 545 546 *retp = cs4281_device; 547 return 0; 548 } 549 550 static int 551 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 552 void (*intr)(void *), void *arg, 553 const audio_params_t *param) 554 { 555 struct cs428x_softc *sc; 556 uint32_t fmt; 557 struct cs428x_dma *p; 558 int dma_count; 559 560 sc = addr; 561 fmt = 0; 562 #ifdef DIAGNOSTIC 563 if (sc->sc_prun) 564 printf("cs4281_trigger_output: already running\n"); 565 #endif 566 sc->sc_prun = 1; 567 568 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 569 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 570 sc->sc_pintr = intr; 571 sc->sc_parg = arg; 572 573 /* stop playback DMA */ 574 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 575 576 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 577 param->precision, param->channels, param->encoding)); 578 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 579 continue; 580 if (p == NULL) { 581 printf("cs4281_trigger_output: bad addr %p\n", start); 582 return EINVAL; 583 } 584 585 sc->sc_pcount = blksize / sc->hw_blocksize; 586 sc->sc_ps = (char *)start; 587 sc->sc_pe = (char *)end; 588 sc->sc_pdma = p; 589 sc->sc_pbuf = KERNADDR(p); 590 sc->sc_pi = 0; 591 sc->sc_pn = sc->sc_ps; 592 if (blksize >= sc->dma_size) { 593 sc->sc_pn = sc->sc_ps + sc->dma_size; 594 memcpy(sc->sc_pbuf, start, sc->dma_size); 595 ++sc->sc_pi; 596 } else { 597 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 598 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 599 } 600 601 dma_count = sc->dma_size; 602 if (param->precision != 8) 603 dma_count /= 2; /* 16 bit */ 604 if (param->channels > 1) 605 dma_count /= 2; /* Stereo */ 606 607 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 608 (int)DMAADDR(p), dma_count)); 609 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 610 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 611 612 /* set playback format */ 613 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 614 if (param->precision == 8) 615 fmt |= DMRn_SIZE8; 616 if (param->channels == 1) 617 fmt |= DMRn_MONO; 618 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 619 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 620 fmt |= DMRn_BEND; 621 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 622 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 623 fmt |= DMRn_USIGN; 624 BA0WRITE4(sc, CS4281_DMR0, fmt); 625 626 /* set sample rate */ 627 sc->sc_prate = param->sample_rate; 628 cs4281_set_dac_rate(sc, param->sample_rate); 629 630 /* start DMA */ 631 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 632 /* Enable interrupts */ 633 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 634 635 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 636 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 637 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 638 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 639 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 640 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 641 BA0READ4(sc, CS4281_DACSR))); 642 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 643 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 644 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 645 646 return 0; 647 } 648 649 static int 650 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 651 void (*intr)(void *), void *arg, 652 const audio_params_t *param) 653 { 654 struct cs428x_softc *sc; 655 struct cs428x_dma *p; 656 uint32_t fmt; 657 int dma_count; 658 659 sc = addr; 660 fmt = 0; 661 #ifdef DIAGNOSTIC 662 if (sc->sc_rrun) 663 printf("cs4281_trigger_input: already running\n"); 664 #endif 665 sc->sc_rrun = 1; 666 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 667 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 668 sc->sc_rintr = intr; 669 sc->sc_rarg = arg; 670 671 /* stop recording DMA */ 672 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 673 674 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 675 continue; 676 if (!p) { 677 printf("cs4281_trigger_input: bad addr %p\n", start); 678 return EINVAL; 679 } 680 681 sc->sc_rcount = blksize / sc->hw_blocksize; 682 sc->sc_rs = (char *)start; 683 sc->sc_re = (char *)end; 684 sc->sc_rdma = p; 685 sc->sc_rbuf = KERNADDR(p); 686 sc->sc_ri = 0; 687 sc->sc_rn = sc->sc_rs; 688 689 dma_count = sc->dma_size; 690 if (param->precision != 8) 691 dma_count /= 2; 692 if (param->channels > 1) 693 dma_count /= 2; 694 695 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 696 (int)DMAADDR(p), dma_count)); 697 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 698 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 699 700 /* set recording format */ 701 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 702 if (param->precision == 8) 703 fmt |= DMRn_SIZE8; 704 if (param->channels == 1) 705 fmt |= DMRn_MONO; 706 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 707 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 708 fmt |= DMRn_BEND; 709 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 710 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 711 fmt |= DMRn_USIGN; 712 BA0WRITE4(sc, CS4281_DMR1, fmt); 713 714 /* set sample rate */ 715 sc->sc_rrate = param->sample_rate; 716 cs4281_set_adc_rate(sc, param->sample_rate); 717 718 /* Start DMA */ 719 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 720 /* Enable interrupts */ 721 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 722 723 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 724 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 725 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 726 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 727 728 return 0; 729 } 730 731 static bool 732 cs4281_suspend(device_t dv, const pmf_qual_t *qual) 733 { 734 struct cs428x_softc *sc = device_private(dv); 735 736 mutex_enter(&sc->sc_lock); 737 mutex_spin_exit(&sc->sc_intr_lock); 738 739 /* save current playback status */ 740 if (sc->sc_prun) { 741 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 742 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 743 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 744 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 745 } 746 747 /* save current capture status */ 748 if (sc->sc_rrun) { 749 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 750 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 751 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 752 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 753 } 754 /* Stop DMA */ 755 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 756 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 757 758 mutex_spin_exit(&sc->sc_intr_lock); 759 mutex_exit(&sc->sc_lock); 760 761 return true; 762 } 763 764 static bool 765 cs4281_resume(device_t dv, const pmf_qual_t *qual) 766 { 767 struct cs428x_softc *sc = device_private(dv); 768 769 mutex_enter(&sc->sc_lock); 770 mutex_spin_enter(&sc->sc_intr_lock); 771 772 cs4281_init(sc, 0); 773 cs4281_reset_codec(sc); 774 775 /* restore ac97 registers */ 776 mutex_spin_exit(&sc->sc_intr_lock); 777 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 778 mutex_spin_enter(&sc->sc_intr_lock); 779 780 /* restore DMA related status */ 781 if (sc->sc_prun) { 782 cs4281_set_dac_rate(sc, sc->sc_prate); 783 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 784 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 785 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 786 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 787 } 788 if (sc->sc_rrun) { 789 cs4281_set_adc_rate(sc, sc->sc_rrate); 790 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 791 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 792 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 793 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 794 } 795 /* enable intterupts */ 796 if (sc->sc_prun || sc->sc_rrun) 797 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 798 799 mutex_spin_exit(&sc->sc_intr_lock); 800 mutex_exit(&sc->sc_lock); 801 802 return true; 803 } 804 805 /* control AC97 codec */ 806 static int 807 cs4281_reset_codec(void *addr) 808 { 809 struct cs428x_softc *sc; 810 uint16_t data; 811 uint32_t dat32; 812 int n; 813 814 sc = addr; 815 816 DPRINTFN(3, ("cs4281_reset_codec\n")); 817 818 /* Reset codec */ 819 BA0WRITE4(sc, CS428X_ACCTL, 0); 820 delay(50); /* delay 50us */ 821 822 BA0WRITE4(sc, CS4281_SPMC, 0); 823 delay(100); /* delay 100us */ 824 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 825 #if defined(ENABLE_SECONDARY_CODEC) 826 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 827 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 828 #endif 829 delay(50000); /* XXX: delay 50ms */ 830 831 /* Enable ASYNC generation */ 832 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 833 834 /* Wait for codec ready. Linux driver waits 50ms here */ 835 n = 0; 836 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 837 delay(100); 838 if (++n > 1000) { 839 printf("reset_codec: AC97 codec ready timeout\n"); 840 return ETIMEDOUT; 841 } 842 } 843 #if defined(ENABLE_SECONDARY_CODEC) 844 /* secondary codec ready*/ 845 n = 0; 846 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 847 delay(100); 848 if (++n > 1000) 849 return 0; 850 } 851 #endif 852 /* Set the serial timing configuration */ 853 /* XXX: undocumented but the Linux driver do this */ 854 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 855 856 /* Wait for codec ready signal */ 857 n = 0; 858 do { 859 delay(1000); 860 if (++n > 1000) { 861 aprint_error_dev(&sc->sc_dev, 862 "timeout waiting for codec ready\n"); 863 return ETIMEDOUT; 864 } 865 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 866 } while (dat32 == 0); 867 868 /* Enable Valid Frame output on ASDOUT */ 869 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 870 871 /* Wait until codec calibration is finished. Codec register 26h */ 872 n = 0; 873 do { 874 delay(1); 875 if (++n > 1000) { 876 aprint_error_dev(&sc->sc_dev, 877 "timeout waiting for codec calibration\n"); 878 return ETIMEDOUT; 879 } 880 cs428x_read_codec(sc, AC97_REG_POWER, &data); 881 } while ((data & 0x0f) != 0x0f); 882 883 /* Set the serial timing configuration again */ 884 /* XXX: undocumented but the Linux driver do this */ 885 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 886 887 /* Wait until we've sampled input slots 3 & 4 as valid */ 888 n = 0; 889 do { 890 delay(1000); 891 if (++n > 1000) { 892 aprint_error_dev(&sc->sc_dev, "timeout waiting for " 893 "sampled input slots as valid\n"); 894 return ETIMEDOUT; 895 } 896 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 897 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 898 899 /* Start digital data transfer of audio data to the codec */ 900 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 901 return 0; 902 } 903 904 905 /* Internal functions */ 906 907 /* convert sample rate to register value */ 908 static uint8_t 909 cs4281_sr2regval(int rate) 910 { 911 uint8_t retval; 912 913 /* We don't have to change here. but anyway ... */ 914 if (rate > 48000) 915 rate = 48000; 916 if (rate < 6023) 917 rate = 6023; 918 919 switch (rate) { 920 case 8000: 921 retval = 5; 922 break; 923 case 11025: 924 retval = 4; 925 break; 926 case 16000: 927 retval = 3; 928 break; 929 case 22050: 930 retval = 2; 931 break; 932 case 44100: 933 retval = 1; 934 break; 935 case 48000: 936 retval = 0; 937 break; 938 default: 939 retval = 1536000/rate; /* == 24576000/(rate*16) */ 940 } 941 return retval; 942 } 943 944 static void 945 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 946 { 947 948 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 949 } 950 951 static void 952 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 953 { 954 955 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 956 } 957 958 static int 959 cs4281_init(struct cs428x_softc *sc, int init) 960 { 961 int n; 962 uint16_t data; 963 uint32_t dat32; 964 965 /* set "Configuration Write Protect" register to 966 * 0x4281 to allow to write */ 967 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 968 969 /* 970 * Unset "Full Power-Down bit of Extended PCI Power Management 971 * Control" register to release the reset state. 972 */ 973 dat32 = BA0READ4(sc, CS4281_EPPMC); 974 if (dat32 & EPPMC_FPDN) { 975 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 976 } 977 978 /* Start PLL out in known state */ 979 BA0WRITE4(sc, CS4281_CLKCR1, 0); 980 /* Start serial ports out in known state */ 981 BA0WRITE4(sc, CS4281_SERMC, 0); 982 983 /* Reset codec */ 984 BA0WRITE4(sc, CS428X_ACCTL, 0); 985 delay(50); /* delay 50us */ 986 987 BA0WRITE4(sc, CS4281_SPMC, 0); 988 delay(100); /* delay 100us */ 989 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 990 #if defined(ENABLE_SECONDARY_CODEC) 991 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 992 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 993 #endif 994 delay(50000); /* XXX: delay 50ms */ 995 996 /* Turn on Sound System clocks based on ABITCLK */ 997 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 998 delay(50000); /* XXX: delay 50ms */ 999 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1000 1001 /* Set enables for sections that are needed in the SSPM registers */ 1002 BA0WRITE4(sc, CS4281_SSPM, 1003 SSPM_MIXEN | /* Mixer */ 1004 SSPM_CSRCEN | /* Capture SRC */ 1005 SSPM_PSRCEN | /* Playback SRC */ 1006 SSPM_JSEN | /* Joystick */ 1007 SSPM_ACLEN | /* AC LINK */ 1008 SSPM_FMEN /* FM */ 1009 ); 1010 1011 /* Wait for clock stabilization */ 1012 n = 0; 1013 #if 1 1014 /* what document says */ 1015 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1016 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1017 delay(100); 1018 if (++n > 1000) { 1019 aprint_error_dev(&sc->sc_dev, 1020 "timeout waiting for clock stabilization\n"); 1021 return -1; 1022 } 1023 } 1024 #else 1025 /* Cirrus driver for Linux does */ 1026 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1027 delay(1000); 1028 if (++n > 1000) { 1029 aprint_error_dev(&sc->sc_dev, 1030 "timeout waiting for clock stabilization\n"); 1031 return -1; 1032 } 1033 } 1034 #endif 1035 1036 /* Enable ASYNC generation */ 1037 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1038 1039 /* Wait for codec ready. Linux driver waits 50ms here */ 1040 n = 0; 1041 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1042 delay(100); 1043 if (++n > 1000) { 1044 aprint_error_dev(&sc->sc_dev, 1045 "timeout waiting for codec ready\n"); 1046 return -1; 1047 } 1048 } 1049 1050 #if defined(ENABLE_SECONDARY_CODEC) 1051 /* secondary codec ready*/ 1052 n = 0; 1053 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1054 delay(100); 1055 if (++n > 1000) { 1056 aprint_error_dev(&sc->sc_dev, 1057 "timeout waiting for secondary codec ready\n"); 1058 return -1; 1059 } 1060 } 1061 #endif 1062 1063 /* Set the serial timing configuration */ 1064 /* XXX: undocumented but the Linux driver do this */ 1065 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1066 1067 /* Wait for codec ready signal */ 1068 n = 0; 1069 do { 1070 delay(1000); 1071 if (++n > 1000) { 1072 aprint_error_dev(&sc->sc_dev, 1073 "timeout waiting for codec ready\n"); 1074 return -1; 1075 } 1076 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1077 } while (dat32 == 0); 1078 1079 /* Enable Valid Frame output on ASDOUT */ 1080 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1081 1082 /* Wait until codec calibration is finished. codec register 26h */ 1083 n = 0; 1084 do { 1085 delay(1); 1086 if (++n > 1000) { 1087 aprint_error_dev(&sc->sc_dev, 1088 "timeout waiting for codec calibration\n"); 1089 return -1; 1090 } 1091 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1092 } while ((data & 0x0f) != 0x0f); 1093 1094 /* Set the serial timing configuration again */ 1095 /* XXX: undocumented but the Linux driver do this */ 1096 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1097 1098 /* Wait until we've sampled input slots 3 & 4 as valid */ 1099 n = 0; 1100 do { 1101 delay(1000); 1102 if (++n > 1000) { 1103 aprint_error_dev(&sc->sc_dev, "timeout waiting for " 1104 "sampled input slots as valid\n"); 1105 return -1; 1106 } 1107 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1108 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1109 1110 /* Start digital data transfer of audio data to the codec */ 1111 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1112 1113 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1114 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1115 1116 /* Power on the DAC */ 1117 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1118 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1119 1120 /* Wait until we sample a DAC ready state. 1121 * Not documented, but Linux driver does. 1122 */ 1123 for (n = 0; n < 32; ++n) { 1124 delay(1000); 1125 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1126 if (data & 0x02) 1127 break; 1128 } 1129 1130 /* Power on the ADC */ 1131 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1132 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1133 1134 /* Wait until we sample ADC ready state. 1135 * Not documented, but Linux driver does. 1136 */ 1137 for (n = 0; n < 32; ++n) { 1138 delay(1000); 1139 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1140 if (data & 0x01) 1141 break; 1142 } 1143 1144 #if 0 1145 /* Initialize AC-Link features */ 1146 /* variable sample-rate support */ 1147 mem = BA0READ4(sc, CS4281_SERMC); 1148 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1149 BA0WRITE4(sc, CS4281_SERMC, mem); 1150 /* XXX: more... */ 1151 1152 /* Initialize SSCR register features */ 1153 /* XXX: hardware volume setting */ 1154 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1155 #endif 1156 1157 /* disable Sound Blaster Pro emulation */ 1158 /* XXX: 1159 * Cannot set since the documents does not describe which bit is 1160 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1161 * we can ignore it.*/ 1162 #if 0 1163 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1164 #endif 1165 1166 /* map AC97 PCM playback to DMA Channel 0 */ 1167 /* Reset FEN bit to setup first */ 1168 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1169 /* 1170 *| RS[4:0]/| | 1171 *| LS[4:0] | AC97 | Slot Function 1172 *|---------+--------+-------------------- 1173 *| 0 | 3 | Left PCM Playback 1174 *| 1 | 4 | Right PCM Playback 1175 *| 2 | 5 | Phone Line 1 DAC 1176 *| 3 | 6 | Center PCM Playback 1177 *.... 1178 * quoted from Table 29(p109) 1179 */ 1180 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1181 0x00 << 16 | /* LS[4:0] = 0 see above */ 1182 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1183 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1184 BA0WRITE4(sc, CS4281_FCR0, dat32); 1185 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1186 1187 /* map AC97 PCM record to DMA Channel 1 */ 1188 /* Reset FEN bit to setup first */ 1189 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1190 /* 1191 *| RS[4:0]/| 1192 *| LS[4:0] | AC97 | Slot Function 1193 *|---------+------+------------------- 1194 *| 10 | 3 | Left PCM Record 1195 *| 11 | 4 | Right PCM Record 1196 *| 12 | 5 | Phone Line 1 ADC 1197 *| 13 | 6 | Mic ADC 1198 *.... 1199 * quoted from Table 30(p109) 1200 */ 1201 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1202 0x0a << 16 | /* LS[4:0] = 10 See above */ 1203 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1204 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1205 1206 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1207 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1208 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1209 1210 #if 0 1211 /* Disable DMA Channel 2, 3 */ 1212 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1213 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1214 #endif 1215 1216 /* Set the SRC Slot Assignment accordingly */ 1217 /*| PLSS[4:0]/ 1218 *| PRSS[4:0] | AC97 | Slot Function 1219 *|-----------+------+---------------- 1220 *| 0 | 3 | Left PCM Playback 1221 *| 1 | 4 | Right PCM Playback 1222 *| 2 | 5 | phone line 1 DAC 1223 *| 3 | 6 | Center PCM Playback 1224 *| 4 | 7 | Left Surround PCM Playback 1225 *| 5 | 8 | Right Surround PCM Playback 1226 *...... 1227 * 1228 *| CLSS[4:0]/ 1229 *| CRSS[4:0] | AC97 | Codec |Slot Function 1230 *|-----------+------+-------+----------------- 1231 *| 10 | 3 |Primary| Left PCM Record 1232 *| 11 | 4 |Primary| Right PCM Record 1233 *| 12 | 5 |Primary| Phone Line 1 ADC 1234 *| 13 | 6 |Primary| Mic ADC 1235 *|..... 1236 *| 20 | 3 | Sec. | Left PCM Record 1237 *| 21 | 4 | Sec. | Right PCM Record 1238 *| 22 | 5 | Sec. | Phone Line 1 ADC 1239 *| 23 | 6 | Sec. | Mic ADC 1240 */ 1241 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1242 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1243 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1244 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1245 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1246 1247 /* Set interrupt to occurred at Half and Full terminal 1248 * count interrupt enable for DMA channel 0 and 1. 1249 * To keep DMA stop, set MSK. 1250 */ 1251 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1252 BA0WRITE4(sc, CS4281_DCR0, dat32); 1253 BA0WRITE4(sc, CS4281_DCR1, dat32); 1254 1255 /* Set Auto-Initialize Contorl enable */ 1256 BA0WRITE4(sc, CS4281_DMR0, 1257 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1258 BA0WRITE4(sc, CS4281_DMR1, 1259 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1260 1261 /* Clear DMA Mask in HIMR */ 1262 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1263 BA0WRITE4(sc, CS4281_HIMR, 1264 BA0READ4(sc, CS4281_HIMR) & dat32); 1265 1266 /* set current status */ 1267 if (init != 0) { 1268 sc->sc_prun = 0; 1269 sc->sc_rrun = 0; 1270 } 1271 1272 /* setup playback volume */ 1273 BA0WRITE4(sc, CS4281_PPRVC, 7); 1274 BA0WRITE4(sc, CS4281_PPLVC, 7); 1275 1276 return 0; 1277 } 1278
Indexes created Tue Sep 30 20:09:53 GMT 2025