cs4281.c revision 1.50
1 /* $NetBSD: cs4281.c,v 1.50 2013/10/16 19:32:30 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.50 2013/10/16 19:32:30 christos Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <sys/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(device_t, cfdata_t, void *); 84 static void cs4281_attach(device_t, device_t, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static bool cs4281_suspend(device_t, const pmf_qual_t *); 110 static bool cs4281_resume(device_t, const pmf_qual_t *); 111 112 static const struct audio_hw_if cs4281_hw_if = { 113 NULL, /* open */ 114 NULL, /* close */ 115 NULL, 116 cs4281_query_encoding, 117 cs4281_set_params, 118 cs428x_round_blocksize, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 NULL, 124 cs4281_halt_output, 125 cs4281_halt_input, 126 NULL, 127 cs4281_getdev, 128 NULL, 129 cs428x_mixer_set_port, 130 cs428x_mixer_get_port, 131 cs428x_query_devinfo, 132 cs428x_malloc, 133 cs428x_free, 134 cs428x_round_buffersize, 135 cs428x_mappage, 136 cs428x_get_props, 137 cs4281_trigger_output, 138 cs4281_trigger_input, 139 NULL, 140 cs428x_get_locks, 141 }; 142 143 #if NMIDI > 0 && 0 144 /* Midi Interface */ 145 static void cs4281_midi_close(void*); 146 static void cs4281_midi_getinfo(void *, struct midi_info *); 147 static int cs4281_midi_open(void *, int, void (*)(void *, int), 148 void (*)(void *), void *); 149 static int cs4281_midi_output(void *, int); 150 151 static const struct midi_hw_if cs4281_midi_hw_if = { 152 cs4281_midi_open, 153 cs4281_midi_close, 154 cs4281_midi_output, 155 cs4281_midi_getinfo, 156 0, 157 cs428x_get_locks, 158 }; 159 #endif 160 161 CFATTACH_DECL_NEW(clct, sizeof(struct cs428x_softc), 162 cs4281_match, cs4281_attach, NULL, NULL); 163 164 static struct audio_device cs4281_device = { 165 "CS4281", 166 "", 167 "cs4281" 168 }; 169 170 171 static int 172 cs4281_match(device_t parent, cfdata_t match, void *aux) 173 { 174 struct pci_attach_args *pa; 175 176 pa = (struct pci_attach_args *)aux; 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 178 return 0; 179 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 180 return 1; 181 return 0; 182 } 183 184 static void 185 cs4281_attach(device_t parent, device_t self, void *aux) 186 { 187 struct cs428x_softc *sc; 188 struct pci_attach_args *pa; 189 pci_chipset_tag_t pc; 190 char const *intrstr; 191 pcireg_t reg; 192 int error; 193 194 sc = device_private(self); 195 sc->sc_dev = self; 196 pa = (struct pci_attach_args *)aux; 197 pc = pa->pa_pc; 198 199 pci_aprint_devinfo(pa, "Audio controller"); 200 201 sc->sc_pc = pa->pa_pc; 202 sc->sc_pt = pa->pa_tag; 203 204 /* Map I/O register */ 205 if (pci_mapreg_map(pa, PCI_BA0, 206 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 207 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 208 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 209 return; 210 } 211 if (pci_mapreg_map(pa, PCI_BA1, 212 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 213 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 214 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 215 return; 216 } 217 218 sc->sc_dmatag = pa->pa_dmat; 219 220 /* power up chip */ 221 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 222 pci_activate_null)) && error != EOPNOTSUPP) { 223 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 224 return; 225 } 226 227 /* Enable the device (set bus master flag) */ 228 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 229 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 230 reg | PCI_COMMAND_MASTER_ENABLE); 231 232 #if 0 233 /* LATENCY_TIMER setting */ 234 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 235 if (PCI_LATTIMER(temp1) < 32) { 236 temp1 &= 0xffff00ff; 237 temp1 |= 0x00002000; 238 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 239 } 240 #endif 241 242 /* Map and establish the interrupt. */ 243 if (pci_intr_map(pa, &sc->intrh)) { 244 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 245 return; 246 } 247 intrstr = pci_intr_string(pc, sc->intrh); 248 249 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 250 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 251 252 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 253 cs4281_intr, sc); 254 if (sc->sc_ih == NULL) { 255 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 256 if (intrstr != NULL) 257 aprint_error(" at %s", intrstr); 258 aprint_error("\n"); 259 mutex_destroy(&sc->sc_lock); 260 mutex_destroy(&sc->sc_intr_lock); 261 return; 262 } 263 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 264 265 /* 266 * Sound System start-up 267 */ 268 if (cs4281_init(sc, 1) != 0) { 269 mutex_destroy(&sc->sc_lock); 270 mutex_destroy(&sc->sc_intr_lock); 271 return; 272 } 273 274 sc->type = TYPE_CS4281; 275 sc->halt_input = cs4281_halt_input; 276 sc->halt_output = cs4281_halt_output; 277 278 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 279 sc->dma_align = 0x10; 280 sc->hw_blocksize = sc->dma_size / 2; 281 282 /* AC 97 attachment */ 283 sc->host_if.arg = sc; 284 sc->host_if.attach = cs428x_attach_codec; 285 sc->host_if.read = cs428x_read_codec; 286 sc->host_if.write = cs428x_write_codec; 287 sc->host_if.reset = cs4281_reset_codec; 288 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 289 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 290 mutex_destroy(&sc->sc_lock); 291 mutex_destroy(&sc->sc_intr_lock); 292 return; 293 } 294 audio_attach_mi(&cs4281_hw_if, sc, sc->sc_dev); 295 296 #if NMIDI > 0 && 0 297 midi_attach_mi(&cs4281_midi_hw_if, sc, sc->sc_dev); 298 #endif 299 300 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 301 aprint_error_dev(self, "couldn't establish power handler\n"); 302 } 303 304 static int 305 cs4281_intr(void *p) 306 { 307 struct cs428x_softc *sc; 308 uint32_t intr, hdsr0, hdsr1; 309 char *empty_dma; 310 int handled; 311 312 sc = p; 313 handled = 0; 314 hdsr0 = 0; 315 hdsr1 = 0; 316 317 mutex_spin_enter(&sc->sc_intr_lock); 318 319 /* grab interrupt register */ 320 intr = BA0READ4(sc, CS4281_HISR); 321 322 DPRINTF(("cs4281_intr:")); 323 /* not for me */ 324 if ((intr & HISR_INTENA) == 0) { 325 /* clear the interrupt register */ 326 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 327 mutex_spin_exit(&sc->sc_intr_lock); 328 return 0; 329 } 330 331 if (intr & HISR_DMA0) 332 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 333 if (intr & HISR_DMA1) 334 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 335 /* clear the interrupt register */ 336 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 337 338 #ifdef CS4280_DEBUG 339 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 340 intr, hdsr0, hdsr1)); 341 #else 342 __USE(hdsr0); 343 __USE(hdsr1); 344 #endif 345 346 /* Playback Interrupt */ 347 if (intr & HISR_DMA0) { 348 handled = 1; 349 if (sc->sc_prun) { 350 DPRINTF((" PB DMA 0x%x(%d)", 351 (int)BA0READ4(sc, CS4281_DCA0), 352 (int)BA0READ4(sc, CS4281_DCC0))); 353 if ((sc->sc_pi%sc->sc_pcount) == 0) 354 sc->sc_pintr(sc->sc_parg); 355 /* copy buffer */ 356 ++sc->sc_pi; 357 empty_dma = sc->sc_pdma->addr; 358 if (sc->sc_pi&1) 359 empty_dma += sc->hw_blocksize; 360 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 361 sc->sc_pn += sc->hw_blocksize; 362 if (sc->sc_pn >= sc->sc_pe) 363 sc->sc_pn = sc->sc_ps; 364 } else { 365 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 366 } 367 } 368 if (intr & HISR_DMA1) { 369 handled = 1; 370 if (sc->sc_rrun) { 371 /* copy from DMA */ 372 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 373 (int)BA0READ4(sc, CS4281_DCC1))); 374 ++sc->sc_ri; 375 empty_dma = sc->sc_rdma->addr; 376 if ((sc->sc_ri & 1) == 0) 377 empty_dma += sc->hw_blocksize; 378 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 379 sc->sc_rn += sc->hw_blocksize; 380 if (sc->sc_rn >= sc->sc_re) 381 sc->sc_rn = sc->sc_rs; 382 if ((sc->sc_ri % sc->sc_rcount) == 0) 383 sc->sc_rintr(sc->sc_rarg); 384 } else { 385 aprint_error_dev(sc->sc_dev, 386 "unexpected record intr\n"); 387 } 388 } 389 DPRINTF(("\n")); 390 391 mutex_spin_exit(&sc->sc_intr_lock); 392 393 return handled; 394 } 395 396 static int 397 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 398 { 399 400 switch (fp->index) { 401 case 0: 402 strcpy(fp->name, AudioEulinear); 403 fp->encoding = AUDIO_ENCODING_ULINEAR; 404 fp->precision = 8; 405 fp->flags = 0; 406 break; 407 case 1: 408 strcpy(fp->name, AudioEmulaw); 409 fp->encoding = AUDIO_ENCODING_ULAW; 410 fp->precision = 8; 411 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 412 break; 413 case 2: 414 strcpy(fp->name, AudioEalaw); 415 fp->encoding = AUDIO_ENCODING_ALAW; 416 fp->precision = 8; 417 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 418 break; 419 case 3: 420 strcpy(fp->name, AudioEslinear); 421 fp->encoding = AUDIO_ENCODING_SLINEAR; 422 fp->precision = 8; 423 fp->flags = 0; 424 break; 425 case 4: 426 strcpy(fp->name, AudioEslinear_le); 427 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 428 fp->precision = 16; 429 fp->flags = 0; 430 break; 431 case 5: 432 strcpy(fp->name, AudioEulinear_le); 433 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 434 fp->precision = 16; 435 fp->flags = 0; 436 break; 437 case 6: 438 strcpy(fp->name, AudioEslinear_be); 439 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 440 fp->precision = 16; 441 fp->flags = 0; 442 break; 443 case 7: 444 strcpy(fp->name, AudioEulinear_be); 445 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 446 fp->precision = 16; 447 fp->flags = 0; 448 break; 449 default: 450 return EINVAL; 451 } 452 return 0; 453 } 454 455 static int 456 cs4281_set_params(void *addr, int setmode, int usemode, 457 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 458 stream_filter_list_t *rfil) 459 { 460 audio_params_t hw; 461 struct cs428x_softc *sc; 462 audio_params_t *p; 463 stream_filter_list_t *fil; 464 int mode; 465 466 sc = addr; 467 for (mode = AUMODE_RECORD; mode != -1; 468 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 469 if ((setmode & mode) == 0) 470 continue; 471 472 p = mode == AUMODE_PLAY ? play : rec; 473 474 if (p == play) { 475 DPRINTFN(5, 476 ("play: sample=%u precision=%u channels=%u\n", 477 p->sample_rate, p->precision, p->channels)); 478 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 479 (p->precision != 8 && p->precision != 16) || 480 (p->channels != 1 && p->channels != 2)) { 481 return EINVAL; 482 } 483 } else { 484 DPRINTFN(5, 485 ("rec: sample=%u precision=%u channels=%u\n", 486 p->sample_rate, p->precision, p->channels)); 487 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 488 (p->precision != 8 && p->precision != 16) || 489 (p->channels != 1 && p->channels != 2)) { 490 return EINVAL; 491 } 492 } 493 hw = *p; 494 fil = mode == AUMODE_PLAY ? pfil : rfil; 495 496 switch (p->encoding) { 497 case AUDIO_ENCODING_SLINEAR_BE: 498 break; 499 case AUDIO_ENCODING_SLINEAR_LE: 500 break; 501 case AUDIO_ENCODING_ULINEAR_BE: 502 break; 503 case AUDIO_ENCODING_ULINEAR_LE: 504 break; 505 case AUDIO_ENCODING_ULAW: 506 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 507 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 508 : linear8_to_mulaw, &hw); 509 break; 510 case AUDIO_ENCODING_ALAW: 511 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 512 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 513 : linear8_to_alaw, &hw); 514 break; 515 default: 516 return EINVAL; 517 } 518 } 519 520 /* set sample rate */ 521 cs4281_set_dac_rate(sc, play->sample_rate); 522 cs4281_set_adc_rate(sc, rec->sample_rate); 523 return 0; 524 } 525 526 static int 527 cs4281_halt_output(void *addr) 528 { 529 struct cs428x_softc *sc; 530 531 sc = addr; 532 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 533 sc->sc_prun = 0; 534 return 0; 535 } 536 537 static int 538 cs4281_halt_input(void *addr) 539 { 540 struct cs428x_softc *sc; 541 542 sc = addr; 543 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 544 sc->sc_rrun = 0; 545 return 0; 546 } 547 548 static int 549 cs4281_getdev(void *addr, struct audio_device *retp) 550 { 551 552 *retp = cs4281_device; 553 return 0; 554 } 555 556 static int 557 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 558 void (*intr)(void *), void *arg, 559 const audio_params_t *param) 560 { 561 struct cs428x_softc *sc; 562 uint32_t fmt; 563 struct cs428x_dma *p; 564 int dma_count; 565 566 sc = addr; 567 fmt = 0; 568 #ifdef DIAGNOSTIC 569 if (sc->sc_prun) 570 printf("cs4281_trigger_output: already running\n"); 571 #endif 572 sc->sc_prun = 1; 573 574 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 575 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 576 sc->sc_pintr = intr; 577 sc->sc_parg = arg; 578 579 /* stop playback DMA */ 580 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 581 582 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 583 param->precision, param->channels, param->encoding)); 584 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 585 continue; 586 if (p == NULL) { 587 printf("cs4281_trigger_output: bad addr %p\n", start); 588 return EINVAL; 589 } 590 591 sc->sc_pcount = blksize / sc->hw_blocksize; 592 sc->sc_ps = (char *)start; 593 sc->sc_pe = (char *)end; 594 sc->sc_pdma = p; 595 sc->sc_pbuf = KERNADDR(p); 596 sc->sc_pi = 0; 597 sc->sc_pn = sc->sc_ps; 598 if (blksize >= sc->dma_size) { 599 sc->sc_pn = sc->sc_ps + sc->dma_size; 600 memcpy(sc->sc_pbuf, start, sc->dma_size); 601 ++sc->sc_pi; 602 } else { 603 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 604 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 605 } 606 607 dma_count = sc->dma_size; 608 if (param->precision != 8) 609 dma_count /= 2; /* 16 bit */ 610 if (param->channels > 1) 611 dma_count /= 2; /* Stereo */ 612 613 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 614 (int)DMAADDR(p), dma_count)); 615 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 616 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 617 618 /* set playback format */ 619 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 620 if (param->precision == 8) 621 fmt |= DMRn_SIZE8; 622 if (param->channels == 1) 623 fmt |= DMRn_MONO; 624 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 625 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 626 fmt |= DMRn_BEND; 627 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 628 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 629 fmt |= DMRn_USIGN; 630 BA0WRITE4(sc, CS4281_DMR0, fmt); 631 632 /* set sample rate */ 633 sc->sc_prate = param->sample_rate; 634 cs4281_set_dac_rate(sc, param->sample_rate); 635 636 /* start DMA */ 637 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 638 /* Enable interrupts */ 639 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 640 641 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 642 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 643 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 644 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 645 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 646 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 647 BA0READ4(sc, CS4281_DACSR))); 648 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 649 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 650 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 651 652 return 0; 653 } 654 655 static int 656 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 657 void (*intr)(void *), void *arg, 658 const audio_params_t *param) 659 { 660 struct cs428x_softc *sc; 661 struct cs428x_dma *p; 662 uint32_t fmt; 663 int dma_count; 664 665 sc = addr; 666 fmt = 0; 667 #ifdef DIAGNOSTIC 668 if (sc->sc_rrun) 669 printf("cs4281_trigger_input: already running\n"); 670 #endif 671 sc->sc_rrun = 1; 672 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 673 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 674 sc->sc_rintr = intr; 675 sc->sc_rarg = arg; 676 677 /* stop recording DMA */ 678 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 679 680 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 681 continue; 682 if (!p) { 683 printf("cs4281_trigger_input: bad addr %p\n", start); 684 return EINVAL; 685 } 686 687 sc->sc_rcount = blksize / sc->hw_blocksize; 688 sc->sc_rs = (char *)start; 689 sc->sc_re = (char *)end; 690 sc->sc_rdma = p; 691 sc->sc_rbuf = KERNADDR(p); 692 sc->sc_ri = 0; 693 sc->sc_rn = sc->sc_rs; 694 695 dma_count = sc->dma_size; 696 if (param->precision != 8) 697 dma_count /= 2; 698 if (param->channels > 1) 699 dma_count /= 2; 700 701 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 702 (int)DMAADDR(p), dma_count)); 703 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 704 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 705 706 /* set recording format */ 707 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 708 if (param->precision == 8) 709 fmt |= DMRn_SIZE8; 710 if (param->channels == 1) 711 fmt |= DMRn_MONO; 712 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 713 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 714 fmt |= DMRn_BEND; 715 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 716 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 717 fmt |= DMRn_USIGN; 718 BA0WRITE4(sc, CS4281_DMR1, fmt); 719 720 /* set sample rate */ 721 sc->sc_rrate = param->sample_rate; 722 cs4281_set_adc_rate(sc, param->sample_rate); 723 724 /* Start DMA */ 725 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 726 /* Enable interrupts */ 727 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 728 729 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 730 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 731 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 732 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 733 734 return 0; 735 } 736 737 static bool 738 cs4281_suspend(device_t dv, const pmf_qual_t *qual) 739 { 740 struct cs428x_softc *sc = device_private(dv); 741 742 mutex_enter(&sc->sc_lock); 743 mutex_spin_exit(&sc->sc_intr_lock); 744 745 /* save current playback status */ 746 if (sc->sc_prun) { 747 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 748 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 749 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 750 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 751 } 752 753 /* save current capture status */ 754 if (sc->sc_rrun) { 755 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 756 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 757 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 758 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 759 } 760 /* Stop DMA */ 761 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 762 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 763 764 mutex_spin_exit(&sc->sc_intr_lock); 765 mutex_exit(&sc->sc_lock); 766 767 return true; 768 } 769 770 static bool 771 cs4281_resume(device_t dv, const pmf_qual_t *qual) 772 { 773 struct cs428x_softc *sc = device_private(dv); 774 775 mutex_enter(&sc->sc_lock); 776 mutex_spin_enter(&sc->sc_intr_lock); 777 778 cs4281_init(sc, 0); 779 cs4281_reset_codec(sc); 780 781 /* restore ac97 registers */ 782 mutex_spin_exit(&sc->sc_intr_lock); 783 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 784 mutex_spin_enter(&sc->sc_intr_lock); 785 786 /* restore DMA related status */ 787 if (sc->sc_prun) { 788 cs4281_set_dac_rate(sc, sc->sc_prate); 789 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 790 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 791 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 792 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 793 } 794 if (sc->sc_rrun) { 795 cs4281_set_adc_rate(sc, sc->sc_rrate); 796 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 797 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 798 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 799 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 800 } 801 /* enable intterupts */ 802 if (sc->sc_prun || sc->sc_rrun) 803 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 804 805 mutex_spin_exit(&sc->sc_intr_lock); 806 mutex_exit(&sc->sc_lock); 807 808 return true; 809 } 810 811 /* control AC97 codec */ 812 static int 813 cs4281_reset_codec(void *addr) 814 { 815 struct cs428x_softc *sc; 816 uint16_t data; 817 uint32_t dat32; 818 int n; 819 820 sc = addr; 821 822 DPRINTFN(3, ("cs4281_reset_codec\n")); 823 824 /* Reset codec */ 825 BA0WRITE4(sc, CS428X_ACCTL, 0); 826 delay(50); /* delay 50us */ 827 828 BA0WRITE4(sc, CS4281_SPMC, 0); 829 delay(100); /* delay 100us */ 830 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 831 #if defined(ENABLE_SECONDARY_CODEC) 832 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 833 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 834 #endif 835 delay(50000); /* XXX: delay 50ms */ 836 837 /* Enable ASYNC generation */ 838 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 839 840 /* Wait for codec ready. Linux driver waits 50ms here */ 841 n = 0; 842 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 843 delay(100); 844 if (++n > 1000) { 845 printf("reset_codec: AC97 codec ready timeout\n"); 846 return ETIMEDOUT; 847 } 848 } 849 #if defined(ENABLE_SECONDARY_CODEC) 850 /* secondary codec ready*/ 851 n = 0; 852 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 853 delay(100); 854 if (++n > 1000) 855 return 0; 856 } 857 #endif 858 /* Set the serial timing configuration */ 859 /* XXX: undocumented but the Linux driver do this */ 860 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 861 862 /* Wait for codec ready signal */ 863 n = 0; 864 do { 865 delay(1000); 866 if (++n > 1000) { 867 aprint_error_dev(sc->sc_dev, 868 "timeout waiting for codec ready\n"); 869 return ETIMEDOUT; 870 } 871 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 872 } while (dat32 == 0); 873 874 /* Enable Valid Frame output on ASDOUT */ 875 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 876 877 /* Wait until codec calibration is finished. Codec register 26h */ 878 n = 0; 879 do { 880 delay(1); 881 if (++n > 1000) { 882 aprint_error_dev(sc->sc_dev, 883 "timeout waiting for codec calibration\n"); 884 return ETIMEDOUT; 885 } 886 cs428x_read_codec(sc, AC97_REG_POWER, &data); 887 } while ((data & 0x0f) != 0x0f); 888 889 /* Set the serial timing configuration again */ 890 /* XXX: undocumented but the Linux driver do this */ 891 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 892 893 /* Wait until we've sampled input slots 3 & 4 as valid */ 894 n = 0; 895 do { 896 delay(1000); 897 if (++n > 1000) { 898 aprint_error_dev(sc->sc_dev, "timeout waiting for " 899 "sampled input slots as valid\n"); 900 return ETIMEDOUT; 901 } 902 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 903 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 904 905 /* Start digital data transfer of audio data to the codec */ 906 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 907 return 0; 908 } 909 910 911 /* Internal functions */ 912 913 /* convert sample rate to register value */ 914 static uint8_t 915 cs4281_sr2regval(int rate) 916 { 917 uint8_t retval; 918 919 /* We don't have to change here. but anyway ... */ 920 if (rate > 48000) 921 rate = 48000; 922 if (rate < 6023) 923 rate = 6023; 924 925 switch (rate) { 926 case 8000: 927 retval = 5; 928 break; 929 case 11025: 930 retval = 4; 931 break; 932 case 16000: 933 retval = 3; 934 break; 935 case 22050: 936 retval = 2; 937 break; 938 case 44100: 939 retval = 1; 940 break; 941 case 48000: 942 retval = 0; 943 break; 944 default: 945 retval = 1536000/rate; /* == 24576000/(rate*16) */ 946 } 947 return retval; 948 } 949 950 static void 951 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 952 { 953 954 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 955 } 956 957 static void 958 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 959 { 960 961 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 962 } 963 964 static int 965 cs4281_init(struct cs428x_softc *sc, int init) 966 { 967 int n; 968 uint16_t data; 969 uint32_t dat32; 970 971 /* set "Configuration Write Protect" register to 972 * 0x4281 to allow to write */ 973 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 974 975 /* 976 * Unset "Full Power-Down bit of Extended PCI Power Management 977 * Control" register to release the reset state. 978 */ 979 dat32 = BA0READ4(sc, CS4281_EPPMC); 980 if (dat32 & EPPMC_FPDN) { 981 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 982 } 983 984 /* Start PLL out in known state */ 985 BA0WRITE4(sc, CS4281_CLKCR1, 0); 986 /* Start serial ports out in known state */ 987 BA0WRITE4(sc, CS4281_SERMC, 0); 988 989 /* Reset codec */ 990 BA0WRITE4(sc, CS428X_ACCTL, 0); 991 delay(50); /* delay 50us */ 992 993 BA0WRITE4(sc, CS4281_SPMC, 0); 994 delay(100); /* delay 100us */ 995 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 996 #if defined(ENABLE_SECONDARY_CODEC) 997 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 998 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 999 #endif 1000 delay(50000); /* XXX: delay 50ms */ 1001 1002 /* Turn on Sound System clocks based on ABITCLK */ 1003 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 1004 delay(50000); /* XXX: delay 50ms */ 1005 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1006 1007 /* Set enables for sections that are needed in the SSPM registers */ 1008 BA0WRITE4(sc, CS4281_SSPM, 1009 SSPM_MIXEN | /* Mixer */ 1010 SSPM_CSRCEN | /* Capture SRC */ 1011 SSPM_PSRCEN | /* Playback SRC */ 1012 SSPM_JSEN | /* Joystick */ 1013 SSPM_ACLEN | /* AC LINK */ 1014 SSPM_FMEN /* FM */ 1015 ); 1016 1017 /* Wait for clock stabilization */ 1018 n = 0; 1019 #if 1 1020 /* what document says */ 1021 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1022 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1023 delay(100); 1024 if (++n > 1000) { 1025 aprint_error_dev(sc->sc_dev, 1026 "timeout waiting for clock stabilization\n"); 1027 return -1; 1028 } 1029 } 1030 #else 1031 /* Cirrus driver for Linux does */ 1032 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1033 delay(1000); 1034 if (++n > 1000) { 1035 aprint_error_dev(sc->sc_dev, 1036 "timeout waiting for clock stabilization\n"); 1037 return -1; 1038 } 1039 } 1040 #endif 1041 1042 /* Enable ASYNC generation */ 1043 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1044 1045 /* Wait for codec ready. Linux driver waits 50ms here */ 1046 n = 0; 1047 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1048 delay(100); 1049 if (++n > 1000) { 1050 aprint_error_dev(sc->sc_dev, 1051 "timeout waiting for codec ready\n"); 1052 return -1; 1053 } 1054 } 1055 1056 #if defined(ENABLE_SECONDARY_CODEC) 1057 /* secondary codec ready*/ 1058 n = 0; 1059 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1060 delay(100); 1061 if (++n > 1000) { 1062 aprint_error_dev(sc->sc_dev, 1063 "timeout waiting for secondary codec ready\n"); 1064 return -1; 1065 } 1066 } 1067 #endif 1068 1069 /* Set the serial timing configuration */ 1070 /* XXX: undocumented but the Linux driver do this */ 1071 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1072 1073 /* Wait for codec ready signal */ 1074 n = 0; 1075 do { 1076 delay(1000); 1077 if (++n > 1000) { 1078 aprint_error_dev(sc->sc_dev, 1079 "timeout waiting for codec ready\n"); 1080 return -1; 1081 } 1082 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1083 } while (dat32 == 0); 1084 1085 /* Enable Valid Frame output on ASDOUT */ 1086 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1087 1088 /* Wait until codec calibration is finished. codec register 26h */ 1089 n = 0; 1090 do { 1091 delay(1); 1092 if (++n > 1000) { 1093 aprint_error_dev(sc->sc_dev, 1094 "timeout waiting for codec calibration\n"); 1095 return -1; 1096 } 1097 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1098 } while ((data & 0x0f) != 0x0f); 1099 1100 /* Set the serial timing configuration again */ 1101 /* XXX: undocumented but the Linux driver do this */ 1102 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1103 1104 /* Wait until we've sampled input slots 3 & 4 as valid */ 1105 n = 0; 1106 do { 1107 delay(1000); 1108 if (++n > 1000) { 1109 aprint_error_dev(sc->sc_dev, "timeout waiting for " 1110 "sampled input slots as valid\n"); 1111 return -1; 1112 } 1113 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1114 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1115 1116 /* Start digital data transfer of audio data to the codec */ 1117 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1118 1119 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1120 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1121 1122 /* Power on the DAC */ 1123 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1124 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1125 1126 /* Wait until we sample a DAC ready state. 1127 * Not documented, but Linux driver does. 1128 */ 1129 for (n = 0; n < 32; ++n) { 1130 delay(1000); 1131 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1132 if (data & 0x02) 1133 break; 1134 } 1135 1136 /* Power on the ADC */ 1137 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1138 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1139 1140 /* Wait until we sample ADC ready state. 1141 * Not documented, but Linux driver does. 1142 */ 1143 for (n = 0; n < 32; ++n) { 1144 delay(1000); 1145 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1146 if (data & 0x01) 1147 break; 1148 } 1149 1150 #if 0 1151 /* Initialize AC-Link features */ 1152 /* variable sample-rate support */ 1153 mem = BA0READ4(sc, CS4281_SERMC); 1154 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1155 BA0WRITE4(sc, CS4281_SERMC, mem); 1156 /* XXX: more... */ 1157 1158 /* Initialize SSCR register features */ 1159 /* XXX: hardware volume setting */ 1160 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1161 #endif 1162 1163 /* disable Sound Blaster Pro emulation */ 1164 /* XXX: 1165 * Cannot set since the documents does not describe which bit is 1166 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1167 * we can ignore it.*/ 1168 #if 0 1169 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1170 #endif 1171 1172 /* map AC97 PCM playback to DMA Channel 0 */ 1173 /* Reset FEN bit to setup first */ 1174 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1175 /* 1176 *| RS[4:0]/| | 1177 *| LS[4:0] | AC97 | Slot Function 1178 *|---------+--------+-------------------- 1179 *| 0 | 3 | Left PCM Playback 1180 *| 1 | 4 | Right PCM Playback 1181 *| 2 | 5 | Phone Line 1 DAC 1182 *| 3 | 6 | Center PCM Playback 1183 *.... 1184 * quoted from Table 29(p109) 1185 */ 1186 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1187 0x00 << 16 | /* LS[4:0] = 0 see above */ 1188 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1189 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1190 BA0WRITE4(sc, CS4281_FCR0, dat32); 1191 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1192 1193 /* map AC97 PCM record to DMA Channel 1 */ 1194 /* Reset FEN bit to setup first */ 1195 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1196 /* 1197 *| RS[4:0]/| 1198 *| LS[4:0] | AC97 | Slot Function 1199 *|---------+------+------------------- 1200 *| 10 | 3 | Left PCM Record 1201 *| 11 | 4 | Right PCM Record 1202 *| 12 | 5 | Phone Line 1 ADC 1203 *| 13 | 6 | Mic ADC 1204 *.... 1205 * quoted from Table 30(p109) 1206 */ 1207 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1208 0x0a << 16 | /* LS[4:0] = 10 See above */ 1209 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1210 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1211 1212 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1213 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1214 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1215 1216 #if 0 1217 /* Disable DMA Channel 2, 3 */ 1218 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1219 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1220 #endif 1221 1222 /* Set the SRC Slot Assignment accordingly */ 1223 /*| PLSS[4:0]/ 1224 *| PRSS[4:0] | AC97 | Slot Function 1225 *|-----------+------+---------------- 1226 *| 0 | 3 | Left PCM Playback 1227 *| 1 | 4 | Right PCM Playback 1228 *| 2 | 5 | phone line 1 DAC 1229 *| 3 | 6 | Center PCM Playback 1230 *| 4 | 7 | Left Surround PCM Playback 1231 *| 5 | 8 | Right Surround PCM Playback 1232 *...... 1233 * 1234 *| CLSS[4:0]/ 1235 *| CRSS[4:0] | AC97 | Codec |Slot Function 1236 *|-----------+------+-------+----------------- 1237 *| 10 | 3 |Primary| Left PCM Record 1238 *| 11 | 4 |Primary| Right PCM Record 1239 *| 12 | 5 |Primary| Phone Line 1 ADC 1240 *| 13 | 6 |Primary| Mic ADC 1241 *|..... 1242 *| 20 | 3 | Sec. | Left PCM Record 1243 *| 21 | 4 | Sec. | Right PCM Record 1244 *| 22 | 5 | Sec. | Phone Line 1 ADC 1245 *| 23 | 6 | Sec. | Mic ADC 1246 */ 1247 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1248 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1249 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1250 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1251 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1252 1253 /* Set interrupt to occurred at Half and Full terminal 1254 * count interrupt enable for DMA channel 0 and 1. 1255 * To keep DMA stop, set MSK. 1256 */ 1257 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1258 BA0WRITE4(sc, CS4281_DCR0, dat32); 1259 BA0WRITE4(sc, CS4281_DCR1, dat32); 1260 1261 /* Set Auto-Initialize Contorl enable */ 1262 BA0WRITE4(sc, CS4281_DMR0, 1263 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1264 BA0WRITE4(sc, CS4281_DMR1, 1265 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1266 1267 /* Clear DMA Mask in HIMR */ 1268 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1269 BA0WRITE4(sc, CS4281_HIMR, 1270 BA0READ4(sc, CS4281_HIMR) & dat32); 1271 1272 /* set current status */ 1273 if (init != 0) { 1274 sc->sc_prun = 0; 1275 sc->sc_rrun = 0; 1276 } 1277 1278 /* setup playback volume */ 1279 BA0WRITE4(sc, CS4281_PPRVC, 7); 1280 BA0WRITE4(sc, CS4281_PPLVC, 7); 1281 1282 return 0; 1283 } 1284
Indexes created Tue Sep 30 20:09:53 GMT 2025