cs4281.c revision 1.55
1 /* $NetBSD: cs4281.c,v 1.55 2019/05/08 13:40:18 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.55 2019/05/08 13:40:18 isaki Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio/audio_if.h> 63 #include <dev/midi_if.h> 64 65 #include <dev/ic/ac97reg.h> 66 #include <dev/ic/ac97var.h> 67 68 #include <dev/pci/cs428x.h> 69 70 #include <sys/bus.h> 71 72 #if defined(ENABLE_SECONDARY_CODEC) 73 #define MAX_CHANNELS (4) 74 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 75 #else 76 #define MAX_CHANNELS (2) 77 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 78 #endif 79 80 /* IF functions for audio driver */ 81 static int cs4281_match(device_t, cfdata_t, void *); 82 static void cs4281_attach(device_t, device_t, void *); 83 static int cs4281_intr(void *); 84 static int cs4281_query_format(void *, audio_format_query_t *); 85 static int cs4281_set_format(void *, int, 86 const audio_params_t *, const audio_params_t *, 87 audio_filter_reg_t *, audio_filter_reg_t *); 88 static int cs4281_halt_output(void *); 89 static int cs4281_halt_input(void *); 90 static int cs4281_getdev(void *, struct audio_device *); 91 static int cs4281_trigger_output(void *, void *, void *, int, 92 void (*)(void *), void *, 93 const audio_params_t *); 94 static int cs4281_trigger_input(void *, void *, void *, int, 95 void (*)(void *), void *, 96 const audio_params_t *); 97 98 static int cs4281_reset_codec(void *); 99 100 /* Internal functions */ 101 static uint8_t cs4281_sr2regval(int); 102 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 103 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 104 static int cs4281_init(struct cs428x_softc *, int); 105 106 /* Power Management */ 107 static bool cs4281_suspend(device_t, const pmf_qual_t *); 108 static bool cs4281_resume(device_t, const pmf_qual_t *); 109 110 static const struct audio_hw_if cs4281_hw_if = { 111 .query_format = cs4281_query_format, 112 .set_format = cs4281_set_format, 113 .round_blocksize = cs428x_round_blocksize, 114 .halt_output = cs4281_halt_output, 115 .halt_input = cs4281_halt_input, 116 .getdev = cs4281_getdev, 117 .set_port = cs428x_mixer_set_port, 118 .get_port = cs428x_mixer_get_port, 119 .query_devinfo = cs428x_query_devinfo, 120 .allocm = cs428x_malloc, 121 .freem = cs428x_free, 122 .round_buffersize = cs428x_round_buffersize, 123 .get_props = cs428x_get_props, 124 .trigger_output = cs4281_trigger_output, 125 .trigger_input = cs4281_trigger_input, 126 .get_locks = cs428x_get_locks, 127 }; 128 129 #if NMIDI > 0 && 0 130 /* Midi Interface */ 131 static void cs4281_midi_close(void*); 132 static void cs4281_midi_getinfo(void *, struct midi_info *); 133 static int cs4281_midi_open(void *, int, void (*)(void *, int), 134 void (*)(void *), void *); 135 static int cs4281_midi_output(void *, int); 136 137 static const struct midi_hw_if cs4281_midi_hw_if = { 138 cs4281_midi_open, 139 cs4281_midi_close, 140 cs4281_midi_output, 141 cs4281_midi_getinfo, 142 0, 143 cs428x_get_locks, 144 }; 145 #endif 146 147 CFATTACH_DECL_NEW(clct, sizeof(struct cs428x_softc), 148 cs4281_match, cs4281_attach, NULL, NULL); 149 150 static struct audio_device cs4281_device = { 151 "CS4281", 152 "", 153 "cs4281" 154 }; 155 156 static const struct audio_format cs4281_formats[] = { 157 { 158 .mode = AUMODE_PLAY | AUMODE_RECORD, 159 .encoding = AUDIO_ENCODING_SLINEAR_NE, 160 .validbits = 16, 161 .precision = 16, 162 .channels = 2, 163 .channel_mask = AUFMT_STEREO, 164 .frequency_type = 6, 165 .frequency = { 8000, 11025, 16000, 22050, 44100, 48000 }, 166 }, 167 }; 168 #define CS4281_NFORMATS __arraycount(cs4281_formats) 169 170 static int 171 cs4281_match(device_t parent, cfdata_t match, void *aux) 172 { 173 struct pci_attach_args *pa; 174 175 pa = (struct pci_attach_args *)aux; 176 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 177 return 0; 178 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 179 return 1; 180 return 0; 181 } 182 183 static void 184 cs4281_attach(device_t parent, device_t self, void *aux) 185 { 186 struct cs428x_softc *sc; 187 struct pci_attach_args *pa; 188 pci_chipset_tag_t pc; 189 char const *intrstr; 190 pcireg_t reg; 191 int error; 192 char intrbuf[PCI_INTRSTR_LEN]; 193 194 sc = device_private(self); 195 sc->sc_dev = self; 196 pa = (struct pci_attach_args *)aux; 197 pc = pa->pa_pc; 198 199 pci_aprint_devinfo(pa, "Audio controller"); 200 201 sc->sc_pc = pa->pa_pc; 202 sc->sc_pt = pa->pa_tag; 203 204 /* Map I/O register */ 205 if (pci_mapreg_map(pa, PCI_BA0, 206 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 207 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 208 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 209 return; 210 } 211 if (pci_mapreg_map(pa, PCI_BA1, 212 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 213 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 214 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 215 return; 216 } 217 218 sc->sc_dmatag = pa->pa_dmat; 219 220 /* power up chip */ 221 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 222 pci_activate_null)) && error != EOPNOTSUPP) { 223 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 224 return; 225 } 226 227 /* Enable the device (set bus master flag) */ 228 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 229 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 230 reg | PCI_COMMAND_MASTER_ENABLE); 231 232 #if 0 233 /* LATENCY_TIMER setting */ 234 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 235 if (PCI_LATTIMER(temp1) < 32) { 236 temp1 &= 0xffff00ff; 237 temp1 |= 0x00002000; 238 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 239 } 240 #endif 241 242 /* Map and establish the interrupt. */ 243 if (pci_intr_map(pa, &sc->intrh)) { 244 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 245 return; 246 } 247 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 248 249 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 250 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 251 252 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->intrh, IPL_AUDIO, 253 cs4281_intr, sc, device_xname(self)); 254 if (sc->sc_ih == NULL) { 255 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 256 if (intrstr != NULL) 257 aprint_error(" at %s", intrstr); 258 aprint_error("\n"); 259 mutex_destroy(&sc->sc_lock); 260 mutex_destroy(&sc->sc_intr_lock); 261 return; 262 } 263 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 264 265 /* 266 * Sound System start-up 267 */ 268 if (cs4281_init(sc, 1) != 0) { 269 mutex_destroy(&sc->sc_lock); 270 mutex_destroy(&sc->sc_intr_lock); 271 return; 272 } 273 274 sc->type = TYPE_CS4281; 275 sc->halt_input = cs4281_halt_input; 276 sc->halt_output = cs4281_halt_output; 277 278 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 279 sc->dma_align = 0x10; 280 sc->hw_blocksize = sc->dma_size / 2; 281 282 /* AC 97 attachment */ 283 sc->host_if.arg = sc; 284 sc->host_if.attach = cs428x_attach_codec; 285 sc->host_if.read = cs428x_read_codec; 286 sc->host_if.write = cs428x_write_codec; 287 sc->host_if.reset = cs4281_reset_codec; 288 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 289 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 290 mutex_destroy(&sc->sc_lock); 291 mutex_destroy(&sc->sc_intr_lock); 292 return; 293 } 294 audio_attach_mi(&cs4281_hw_if, sc, sc->sc_dev); 295 296 #if NMIDI > 0 && 0 297 midi_attach_mi(&cs4281_midi_hw_if, sc, sc->sc_dev); 298 #endif 299 300 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 301 aprint_error_dev(self, "couldn't establish power handler\n"); 302 } 303 304 static int 305 cs4281_intr(void *p) 306 { 307 struct cs428x_softc *sc; 308 uint32_t intr, hdsr0, hdsr1; 309 char *empty_dma; 310 int handled; 311 312 sc = p; 313 handled = 0; 314 hdsr0 = 0; 315 hdsr1 = 0; 316 317 mutex_spin_enter(&sc->sc_intr_lock); 318 319 /* grab interrupt register */ 320 intr = BA0READ4(sc, CS4281_HISR); 321 322 DPRINTF(("cs4281_intr:")); 323 /* not for me */ 324 if ((intr & HISR_INTENA) == 0) { 325 /* clear the interrupt register */ 326 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 327 mutex_spin_exit(&sc->sc_intr_lock); 328 return 0; 329 } 330 331 if (intr & HISR_DMA0) 332 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 333 if (intr & HISR_DMA1) 334 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 335 /* clear the interrupt register */ 336 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 337 338 #ifdef CS4280_DEBUG 339 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 340 intr, hdsr0, hdsr1)); 341 #else 342 __USE(hdsr0); 343 __USE(hdsr1); 344 #endif 345 346 /* Playback Interrupt */ 347 if (intr & HISR_DMA0) { 348 handled = 1; 349 if (sc->sc_prun) { 350 DPRINTF((" PB DMA 0x%x(%d)", 351 (int)BA0READ4(sc, CS4281_DCA0), 352 (int)BA0READ4(sc, CS4281_DCC0))); 353 if ((sc->sc_pi%sc->sc_pcount) == 0) 354 sc->sc_pintr(sc->sc_parg); 355 /* copy buffer */ 356 ++sc->sc_pi; 357 empty_dma = sc->sc_pdma->addr; 358 if (sc->sc_pi&1) 359 empty_dma += sc->hw_blocksize; 360 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 361 sc->sc_pn += sc->hw_blocksize; 362 if (sc->sc_pn >= sc->sc_pe) 363 sc->sc_pn = sc->sc_ps; 364 } else { 365 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 366 } 367 } 368 if (intr & HISR_DMA1) { 369 handled = 1; 370 if (sc->sc_rrun) { 371 /* copy from DMA */ 372 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 373 (int)BA0READ4(sc, CS4281_DCC1))); 374 ++sc->sc_ri; 375 empty_dma = sc->sc_rdma->addr; 376 if ((sc->sc_ri & 1) == 0) 377 empty_dma += sc->hw_blocksize; 378 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 379 sc->sc_rn += sc->hw_blocksize; 380 if (sc->sc_rn >= sc->sc_re) 381 sc->sc_rn = sc->sc_rs; 382 if ((sc->sc_ri % sc->sc_rcount) == 0) 383 sc->sc_rintr(sc->sc_rarg); 384 } else { 385 aprint_error_dev(sc->sc_dev, 386 "unexpected record intr\n"); 387 } 388 } 389 DPRINTF(("\n")); 390 391 mutex_spin_exit(&sc->sc_intr_lock); 392 393 return handled; 394 } 395 396 static int 397 cs4281_query_format(void *addr, audio_format_query_t *afp) 398 { 399 400 return audio_query_format(cs4281_formats, CS4281_NFORMATS, afp); 401 } 402 403 static int 404 cs4281_set_format(void *addr, int setmode, 405 const audio_params_t *play, const audio_params_t *rec, 406 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 407 { 408 struct cs428x_softc *sc; 409 410 sc = addr; 411 /* set sample rate */ 412 cs4281_set_dac_rate(sc, play->sample_rate); 413 cs4281_set_adc_rate(sc, rec->sample_rate); 414 return 0; 415 } 416 417 static int 418 cs4281_halt_output(void *addr) 419 { 420 struct cs428x_softc *sc; 421 422 sc = addr; 423 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 424 sc->sc_prun = 0; 425 return 0; 426 } 427 428 static int 429 cs4281_halt_input(void *addr) 430 { 431 struct cs428x_softc *sc; 432 433 sc = addr; 434 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 435 sc->sc_rrun = 0; 436 return 0; 437 } 438 439 static int 440 cs4281_getdev(void *addr, struct audio_device *retp) 441 { 442 443 *retp = cs4281_device; 444 return 0; 445 } 446 447 static int 448 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 449 void (*intr)(void *), void *arg, 450 const audio_params_t *param) 451 { 452 struct cs428x_softc *sc; 453 uint32_t fmt; 454 struct cs428x_dma *p; 455 int dma_count; 456 457 sc = addr; 458 fmt = 0; 459 #ifdef DIAGNOSTIC 460 if (sc->sc_prun) 461 printf("cs4281_trigger_output: already running\n"); 462 #endif 463 sc->sc_prun = 1; 464 465 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 466 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 467 sc->sc_pintr = intr; 468 sc->sc_parg = arg; 469 470 /* stop playback DMA */ 471 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 472 473 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 474 param->precision, param->channels, param->encoding)); 475 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 476 continue; 477 if (p == NULL) { 478 printf("cs4281_trigger_output: bad addr %p\n", start); 479 return EINVAL; 480 } 481 482 sc->sc_pcount = blksize / sc->hw_blocksize; 483 sc->sc_ps = (char *)start; 484 sc->sc_pe = (char *)end; 485 sc->sc_pdma = p; 486 sc->sc_pbuf = KERNADDR(p); 487 sc->sc_pi = 0; 488 sc->sc_pn = sc->sc_ps; 489 if (blksize >= sc->dma_size) { 490 sc->sc_pn = sc->sc_ps + sc->dma_size; 491 memcpy(sc->sc_pbuf, start, sc->dma_size); 492 ++sc->sc_pi; 493 } else { 494 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 495 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 496 } 497 498 dma_count = sc->dma_size; 499 if (param->precision != 8) 500 dma_count /= 2; /* 16 bit */ 501 if (param->channels > 1) 502 dma_count /= 2; /* Stereo */ 503 504 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 505 (int)DMAADDR(p), dma_count)); 506 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 507 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 508 509 /* set playback format */ 510 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 511 if (param->encoding == AUDIO_ENCODING_SLINEAR_BE) 512 fmt |= DMRn_BEND; 513 BA0WRITE4(sc, CS4281_DMR0, fmt); 514 515 /* set sample rate */ 516 sc->sc_prate = param->sample_rate; 517 cs4281_set_dac_rate(sc, param->sample_rate); 518 519 /* start DMA */ 520 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 521 /* Enable interrupts */ 522 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 523 524 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 525 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 526 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 527 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 528 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 529 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 530 BA0READ4(sc, CS4281_DACSR))); 531 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 532 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 533 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 534 535 return 0; 536 } 537 538 static int 539 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 540 void (*intr)(void *), void *arg, 541 const audio_params_t *param) 542 { 543 struct cs428x_softc *sc; 544 struct cs428x_dma *p; 545 uint32_t fmt; 546 int dma_count; 547 548 sc = addr; 549 fmt = 0; 550 #ifdef DIAGNOSTIC 551 if (sc->sc_rrun) 552 printf("cs4281_trigger_input: already running\n"); 553 #endif 554 sc->sc_rrun = 1; 555 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 556 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 557 sc->sc_rintr = intr; 558 sc->sc_rarg = arg; 559 560 /* stop recording DMA */ 561 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 562 563 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 564 continue; 565 if (!p) { 566 printf("cs4281_trigger_input: bad addr %p\n", start); 567 return EINVAL; 568 } 569 570 sc->sc_rcount = blksize / sc->hw_blocksize; 571 sc->sc_rs = (char *)start; 572 sc->sc_re = (char *)end; 573 sc->sc_rdma = p; 574 sc->sc_rbuf = KERNADDR(p); 575 sc->sc_ri = 0; 576 sc->sc_rn = sc->sc_rs; 577 578 dma_count = sc->dma_size; 579 if (param->precision != 8) 580 dma_count /= 2; 581 if (param->channels > 1) 582 dma_count /= 2; 583 584 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 585 (int)DMAADDR(p), dma_count)); 586 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 587 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 588 589 /* set recording format */ 590 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 591 if (param->encoding == AUDIO_ENCODING_SLINEAR_BE) 592 fmt |= DMRn_BEND; 593 BA0WRITE4(sc, CS4281_DMR1, fmt); 594 595 /* set sample rate */ 596 sc->sc_rrate = param->sample_rate; 597 cs4281_set_adc_rate(sc, param->sample_rate); 598 599 /* Start DMA */ 600 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 601 /* Enable interrupts */ 602 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 603 604 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 605 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 606 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 607 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 608 609 return 0; 610 } 611 612 static bool 613 cs4281_suspend(device_t dv, const pmf_qual_t *qual) 614 { 615 struct cs428x_softc *sc = device_private(dv); 616 617 mutex_enter(&sc->sc_lock); 618 mutex_spin_exit(&sc->sc_intr_lock); 619 620 /* save current playback status */ 621 if (sc->sc_prun) { 622 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 623 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 624 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 625 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 626 } 627 628 /* save current capture status */ 629 if (sc->sc_rrun) { 630 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 631 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 632 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 633 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 634 } 635 /* Stop DMA */ 636 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 637 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 638 639 mutex_spin_exit(&sc->sc_intr_lock); 640 mutex_exit(&sc->sc_lock); 641 642 return true; 643 } 644 645 static bool 646 cs4281_resume(device_t dv, const pmf_qual_t *qual) 647 { 648 struct cs428x_softc *sc = device_private(dv); 649 650 mutex_enter(&sc->sc_lock); 651 mutex_spin_enter(&sc->sc_intr_lock); 652 653 cs4281_init(sc, 0); 654 cs4281_reset_codec(sc); 655 656 /* restore ac97 registers */ 657 mutex_spin_exit(&sc->sc_intr_lock); 658 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 659 mutex_spin_enter(&sc->sc_intr_lock); 660 661 /* restore DMA related status */ 662 if (sc->sc_prun) { 663 cs4281_set_dac_rate(sc, sc->sc_prate); 664 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 665 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 666 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 667 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 668 } 669 if (sc->sc_rrun) { 670 cs4281_set_adc_rate(sc, sc->sc_rrate); 671 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 672 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 673 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 674 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 675 } 676 /* enable intterupts */ 677 if (sc->sc_prun || sc->sc_rrun) 678 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 679 680 mutex_spin_exit(&sc->sc_intr_lock); 681 mutex_exit(&sc->sc_lock); 682 683 return true; 684 } 685 686 /* control AC97 codec */ 687 static int 688 cs4281_reset_codec(void *addr) 689 { 690 struct cs428x_softc *sc; 691 uint16_t data; 692 uint32_t dat32; 693 int n; 694 695 sc = addr; 696 697 DPRINTFN(3, ("cs4281_reset_codec\n")); 698 699 /* Reset codec */ 700 BA0WRITE4(sc, CS428X_ACCTL, 0); 701 delay(50); /* delay 50us */ 702 703 BA0WRITE4(sc, CS4281_SPMC, 0); 704 delay(100); /* delay 100us */ 705 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 706 #if defined(ENABLE_SECONDARY_CODEC) 707 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 708 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 709 #endif 710 delay(50000); /* XXX: delay 50ms */ 711 712 /* Enable ASYNC generation */ 713 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 714 715 /* Wait for codec ready. Linux driver waits 50ms here */ 716 n = 0; 717 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 718 delay(100); 719 if (++n > 1000) { 720 printf("reset_codec: AC97 codec ready timeout\n"); 721 return ETIMEDOUT; 722 } 723 } 724 #if defined(ENABLE_SECONDARY_CODEC) 725 /* secondary codec ready*/ 726 n = 0; 727 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 728 delay(100); 729 if (++n > 1000) 730 return 0; 731 } 732 #endif 733 /* Set the serial timing configuration */ 734 /* XXX: undocumented but the Linux driver do this */ 735 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 736 737 /* Wait for codec ready signal */ 738 n = 0; 739 do { 740 delay(1000); 741 if (++n > 1000) { 742 aprint_error_dev(sc->sc_dev, 743 "timeout waiting for codec ready\n"); 744 return ETIMEDOUT; 745 } 746 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 747 } while (dat32 == 0); 748 749 /* Enable Valid Frame output on ASDOUT */ 750 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 751 752 /* Wait until codec calibration is finished. Codec register 26h */ 753 n = 0; 754 do { 755 delay(1); 756 if (++n > 1000) { 757 aprint_error_dev(sc->sc_dev, 758 "timeout waiting for codec calibration\n"); 759 return ETIMEDOUT; 760 } 761 cs428x_read_codec(sc, AC97_REG_POWER, &data); 762 } while ((data & 0x0f) != 0x0f); 763 764 /* Set the serial timing configuration again */ 765 /* XXX: undocumented but the Linux driver do this */ 766 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 767 768 /* Wait until we've sampled input slots 3 & 4 as valid */ 769 n = 0; 770 do { 771 delay(1000); 772 if (++n > 1000) { 773 aprint_error_dev(sc->sc_dev, "timeout waiting for " 774 "sampled input slots as valid\n"); 775 return ETIMEDOUT; 776 } 777 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 778 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 779 780 /* Start digital data transfer of audio data to the codec */ 781 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 782 return 0; 783 } 784 785 786 /* Internal functions */ 787 788 /* convert sample rate to register value */ 789 static uint8_t 790 cs4281_sr2regval(int rate) 791 { 792 uint8_t retval; 793 794 /* We don't have to change here. but anyway ... */ 795 if (rate > 48000) 796 rate = 48000; 797 if (rate < 6023) 798 rate = 6023; 799 800 switch (rate) { 801 case 8000: 802 retval = 5; 803 break; 804 case 11025: 805 retval = 4; 806 break; 807 case 16000: 808 retval = 3; 809 break; 810 case 22050: 811 retval = 2; 812 break; 813 case 44100: 814 retval = 1; 815 break; 816 case 48000: 817 retval = 0; 818 break; 819 default: 820 retval = 1536000/rate; /* == 24576000/(rate*16) */ 821 } 822 return retval; 823 } 824 825 static void 826 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 827 { 828 829 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 830 } 831 832 static void 833 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 834 { 835 836 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 837 } 838 839 static int 840 cs4281_init(struct cs428x_softc *sc, int init) 841 { 842 int n; 843 uint16_t data; 844 uint32_t dat32; 845 846 /* set "Configuration Write Protect" register to 847 * 0x4281 to allow to write */ 848 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 849 850 /* 851 * Unset "Full Power-Down bit of Extended PCI Power Management 852 * Control" register to release the reset state. 853 */ 854 dat32 = BA0READ4(sc, CS4281_EPPMC); 855 if (dat32 & EPPMC_FPDN) { 856 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 857 } 858 859 /* Start PLL out in known state */ 860 BA0WRITE4(sc, CS4281_CLKCR1, 0); 861 /* Start serial ports out in known state */ 862 BA0WRITE4(sc, CS4281_SERMC, 0); 863 864 /* Reset codec */ 865 BA0WRITE4(sc, CS428X_ACCTL, 0); 866 delay(50); /* delay 50us */ 867 868 BA0WRITE4(sc, CS4281_SPMC, 0); 869 delay(100); /* delay 100us */ 870 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 871 #if defined(ENABLE_SECONDARY_CODEC) 872 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 873 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 874 #endif 875 delay(50000); /* XXX: delay 50ms */ 876 877 /* Turn on Sound System clocks based on ABITCLK */ 878 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 879 delay(50000); /* XXX: delay 50ms */ 880 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 881 882 /* Set enables for sections that are needed in the SSPM registers */ 883 BA0WRITE4(sc, CS4281_SSPM, 884 SSPM_MIXEN | /* Mixer */ 885 SSPM_CSRCEN | /* Capture SRC */ 886 SSPM_PSRCEN | /* Playback SRC */ 887 SSPM_JSEN | /* Joystick */ 888 SSPM_ACLEN | /* AC LINK */ 889 SSPM_FMEN /* FM */ 890 ); 891 892 /* Wait for clock stabilization */ 893 n = 0; 894 #if 1 895 /* what document says */ 896 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 897 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 898 delay(100); 899 if (++n > 1000) { 900 aprint_error_dev(sc->sc_dev, 901 "timeout waiting for clock stabilization\n"); 902 return -1; 903 } 904 } 905 #else 906 /* Cirrus driver for Linux does */ 907 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 908 delay(1000); 909 if (++n > 1000) { 910 aprint_error_dev(sc->sc_dev, 911 "timeout waiting for clock stabilization\n"); 912 return -1; 913 } 914 } 915 #endif 916 917 /* Enable ASYNC generation */ 918 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 919 920 /* Wait for codec ready. Linux driver waits 50ms here */ 921 n = 0; 922 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 923 delay(100); 924 if (++n > 1000) { 925 aprint_error_dev(sc->sc_dev, 926 "timeout waiting for codec ready\n"); 927 return -1; 928 } 929 } 930 931 #if defined(ENABLE_SECONDARY_CODEC) 932 /* secondary codec ready*/ 933 n = 0; 934 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 935 delay(100); 936 if (++n > 1000) { 937 aprint_error_dev(sc->sc_dev, 938 "timeout waiting for secondary codec ready\n"); 939 return -1; 940 } 941 } 942 #endif 943 944 /* Set the serial timing configuration */ 945 /* XXX: undocumented but the Linux driver do this */ 946 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 947 948 /* Wait for codec ready signal */ 949 n = 0; 950 do { 951 delay(1000); 952 if (++n > 1000) { 953 aprint_error_dev(sc->sc_dev, 954 "timeout waiting for codec ready\n"); 955 return -1; 956 } 957 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 958 } while (dat32 == 0); 959 960 /* Enable Valid Frame output on ASDOUT */ 961 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 962 963 /* Wait until codec calibration is finished. codec register 26h */ 964 n = 0; 965 do { 966 delay(1); 967 if (++n > 1000) { 968 aprint_error_dev(sc->sc_dev, 969 "timeout waiting for codec calibration\n"); 970 return -1; 971 } 972 cs428x_read_codec(sc, AC97_REG_POWER, &data); 973 } while ((data & 0x0f) != 0x0f); 974 975 /* Set the serial timing configuration again */ 976 /* XXX: undocumented but the Linux driver do this */ 977 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 978 979 /* Wait until we've sampled input slots 3 & 4 as valid */ 980 n = 0; 981 do { 982 delay(1000); 983 if (++n > 1000) { 984 aprint_error_dev(sc->sc_dev, "timeout waiting for " 985 "sampled input slots as valid\n"); 986 return -1; 987 } 988 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 989 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 990 991 /* Start digital data transfer of audio data to the codec */ 992 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 993 994 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 995 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 996 997 /* Power on the DAC */ 998 cs428x_read_codec(sc, AC97_REG_POWER, &data); 999 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1000 1001 /* Wait until we sample a DAC ready state. 1002 * Not documented, but Linux driver does. 1003 */ 1004 for (n = 0; n < 32; ++n) { 1005 delay(1000); 1006 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1007 if (data & 0x02) 1008 break; 1009 } 1010 1011 /* Power on the ADC */ 1012 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1013 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1014 1015 /* Wait until we sample ADC ready state. 1016 * Not documented, but Linux driver does. 1017 */ 1018 for (n = 0; n < 32; ++n) { 1019 delay(1000); 1020 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1021 if (data & 0x01) 1022 break; 1023 } 1024 1025 #if 0 1026 /* Initialize AC-Link features */ 1027 /* variable sample-rate support */ 1028 mem = BA0READ4(sc, CS4281_SERMC); 1029 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1030 BA0WRITE4(sc, CS4281_SERMC, mem); 1031 /* XXX: more... */ 1032 1033 /* Initialize SSCR register features */ 1034 /* XXX: hardware volume setting */ 1035 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1036 #endif 1037 1038 /* disable Sound Blaster Pro emulation */ 1039 /* XXX: 1040 * Cannot set since the documents does not describe which bit is 1041 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1042 * we can ignore it.*/ 1043 #if 0 1044 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1045 #endif 1046 1047 /* map AC97 PCM playback to DMA Channel 0 */ 1048 /* Reset FEN bit to setup first */ 1049 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1050 /* 1051 *| RS[4:0]/| | 1052 *| LS[4:0] | AC97 | Slot Function 1053 *|---------+--------+-------------------- 1054 *| 0 | 3 | Left PCM Playback 1055 *| 1 | 4 | Right PCM Playback 1056 *| 2 | 5 | Phone Line 1 DAC 1057 *| 3 | 6 | Center PCM Playback 1058 *.... 1059 * quoted from Table 29(p109) 1060 */ 1061 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1062 0x00 << 16 | /* LS[4:0] = 0 see above */ 1063 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1064 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1065 BA0WRITE4(sc, CS4281_FCR0, dat32); 1066 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1067 1068 /* map AC97 PCM record to DMA Channel 1 */ 1069 /* Reset FEN bit to setup first */ 1070 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1071 /* 1072 *| RS[4:0]/| 1073 *| LS[4:0] | AC97 | Slot Function 1074 *|---------+------+------------------- 1075 *| 10 | 3 | Left PCM Record 1076 *| 11 | 4 | Right PCM Record 1077 *| 12 | 5 | Phone Line 1 ADC 1078 *| 13 | 6 | Mic ADC 1079 *.... 1080 * quoted from Table 30(p109) 1081 */ 1082 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1083 0x0a << 16 | /* LS[4:0] = 10 See above */ 1084 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1085 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1086 1087 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1088 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1089 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1090 1091 #if 0 1092 /* Disable DMA Channel 2, 3 */ 1093 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1094 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1095 #endif 1096 1097 /* Set the SRC Slot Assignment accordingly */ 1098 /*| PLSS[4:0]/ 1099 *| PRSS[4:0] | AC97 | Slot Function 1100 *|-----------+------+---------------- 1101 *| 0 | 3 | Left PCM Playback 1102 *| 1 | 4 | Right PCM Playback 1103 *| 2 | 5 | phone line 1 DAC 1104 *| 3 | 6 | Center PCM Playback 1105 *| 4 | 7 | Left Surround PCM Playback 1106 *| 5 | 8 | Right Surround PCM Playback 1107 *...... 1108 * 1109 *| CLSS[4:0]/ 1110 *| CRSS[4:0] | AC97 | Codec |Slot Function 1111 *|-----------+------+-------+----------------- 1112 *| 10 | 3 |Primary| Left PCM Record 1113 *| 11 | 4 |Primary| Right PCM Record 1114 *| 12 | 5 |Primary| Phone Line 1 ADC 1115 *| 13 | 6 |Primary| Mic ADC 1116 *|..... 1117 *| 20 | 3 | Sec. | Left PCM Record 1118 *| 21 | 4 | Sec. | Right PCM Record 1119 *| 22 | 5 | Sec. | Phone Line 1 ADC 1120 *| 23 | 6 | Sec. | Mic ADC 1121 */ 1122 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1123 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1124 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1125 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1126 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1127 1128 /* Set interrupt to occurred at Half and Full terminal 1129 * count interrupt enable for DMA channel 0 and 1. 1130 * To keep DMA stop, set MSK. 1131 */ 1132 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1133 BA0WRITE4(sc, CS4281_DCR0, dat32); 1134 BA0WRITE4(sc, CS4281_DCR1, dat32); 1135 1136 /* Set Auto-Initialize Contorl enable */ 1137 BA0WRITE4(sc, CS4281_DMR0, 1138 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1139 BA0WRITE4(sc, CS4281_DMR1, 1140 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1141 1142 /* Clear DMA Mask in HIMR */ 1143 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1144 BA0WRITE4(sc, CS4281_HIMR, 1145 BA0READ4(sc, CS4281_HIMR) & dat32); 1146 1147 /* set current status */ 1148 if (init != 0) { 1149 sc->sc_prun = 0; 1150 sc->sc_rrun = 0; 1151 } 1152 1153 /* setup playback volume */ 1154 BA0WRITE4(sc, CS4281_PPRVC, 7); 1155 BA0WRITE4(sc, CS4281_PPLVC, 7); 1156 1157 return 0; 1158 } 1159
Indexes created Wed Oct 01 07:09:59 GMT 2025