cs4281.c revision 1.56.2.1
1 /* $NetBSD: cs4281.c,v 1.56.2.1 2021/04/03 22:28:46 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.56.2.1 2021/04/03 22:28:46 thorpej Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio/audio_if.h> 63 #include <dev/midi_if.h> 64 65 #include <dev/ic/ac97reg.h> 66 #include <dev/ic/ac97var.h> 67 68 #include <dev/pci/cs428x.h> 69 70 #include <sys/bus.h> 71 72 #if defined(ENABLE_SECONDARY_CODEC) 73 #define MAX_CHANNELS (4) 74 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 75 #else 76 #define MAX_CHANNELS (2) 77 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 78 #endif 79 80 /* IF functions for audio driver */ 81 static int cs4281_match(device_t, cfdata_t, void *); 82 static void cs4281_attach(device_t, device_t, void *); 83 static int cs4281_intr(void *); 84 static int cs4281_query_format(void *, audio_format_query_t *); 85 static int cs4281_set_format(void *, int, 86 const audio_params_t *, const audio_params_t *, 87 audio_filter_reg_t *, audio_filter_reg_t *); 88 static int cs4281_halt_output(void *); 89 static int cs4281_halt_input(void *); 90 static int cs4281_getdev(void *, struct audio_device *); 91 static int cs4281_trigger_output(void *, void *, void *, int, 92 void (*)(void *), void *, 93 const audio_params_t *); 94 static int cs4281_trigger_input(void *, void *, void *, int, 95 void (*)(void *), void *, 96 const audio_params_t *); 97 98 static int cs4281_reset_codec(void *); 99 100 /* Internal functions */ 101 static uint8_t cs4281_sr2regval(int); 102 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 103 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 104 static int cs4281_init(struct cs428x_softc *, int); 105 106 /* Power Management */ 107 static bool cs4281_suspend(device_t, const pmf_qual_t *); 108 static bool cs4281_resume(device_t, const pmf_qual_t *); 109 110 static const struct audio_hw_if cs4281_hw_if = { 111 .query_format = cs4281_query_format, 112 .set_format = cs4281_set_format, 113 .round_blocksize = cs428x_round_blocksize, 114 .halt_output = cs4281_halt_output, 115 .halt_input = cs4281_halt_input, 116 .getdev = cs4281_getdev, 117 .set_port = cs428x_mixer_set_port, 118 .get_port = cs428x_mixer_get_port, 119 .query_devinfo = cs428x_query_devinfo, 120 .allocm = cs428x_malloc, 121 .freem = cs428x_free, 122 .round_buffersize = cs428x_round_buffersize, 123 .get_props = cs428x_get_props, 124 .trigger_output = cs4281_trigger_output, 125 .trigger_input = cs4281_trigger_input, 126 .get_locks = cs428x_get_locks, 127 }; 128 129 #if NMIDI > 0 && 0 130 /* Midi Interface */ 131 static void cs4281_midi_close(void*); 132 static void cs4281_midi_getinfo(void *, struct midi_info *); 133 static int cs4281_midi_open(void *, int, void (*)(void *, int), 134 void (*)(void *), void *); 135 static int cs4281_midi_output(void *, int); 136 137 static const struct midi_hw_if cs4281_midi_hw_if = { 138 cs4281_midi_open, 139 cs4281_midi_close, 140 cs4281_midi_output, 141 cs4281_midi_getinfo, 142 0, 143 cs428x_get_locks, 144 }; 145 #endif 146 147 CFATTACH_DECL_NEW(clct, sizeof(struct cs428x_softc), 148 cs4281_match, cs4281_attach, NULL, NULL); 149 150 static struct audio_device cs4281_device = { 151 "CS4281", 152 "", 153 "cs4281" 154 }; 155 156 static const struct audio_format cs4281_formats[] = { 157 { 158 .mode = AUMODE_PLAY | AUMODE_RECORD, 159 .encoding = AUDIO_ENCODING_SLINEAR_NE, 160 .validbits = 16, 161 .precision = 16, 162 .channels = 2, 163 .channel_mask = AUFMT_STEREO, 164 .frequency_type = 6, 165 .frequency = { 8000, 11025, 16000, 22050, 44100, 48000 }, 166 }, 167 }; 168 #define CS4281_NFORMATS __arraycount(cs4281_formats) 169 170 static int 171 cs4281_match(device_t parent, cfdata_t match, void *aux) 172 { 173 struct pci_attach_args *pa; 174 175 pa = (struct pci_attach_args *)aux; 176 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 177 return 0; 178 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 179 return 1; 180 return 0; 181 } 182 183 static void 184 cs4281_attach(device_t parent, device_t self, void *aux) 185 { 186 struct cs428x_softc *sc; 187 struct pci_attach_args *pa; 188 pci_chipset_tag_t pc; 189 char const *intrstr; 190 pcireg_t reg; 191 int error; 192 char intrbuf[PCI_INTRSTR_LEN]; 193 194 sc = device_private(self); 195 sc->sc_dev = self; 196 pa = (struct pci_attach_args *)aux; 197 pc = pa->pa_pc; 198 199 pci_aprint_devinfo(pa, "Audio controller"); 200 201 sc->sc_pc = pa->pa_pc; 202 sc->sc_pt = pa->pa_tag; 203 204 /* Map I/O register */ 205 if (pci_mapreg_map(pa, PCI_BA0, 206 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 207 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 208 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 209 return; 210 } 211 if (pci_mapreg_map(pa, PCI_BA1, 212 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 213 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 214 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 215 return; 216 } 217 218 sc->sc_dmatag = pa->pa_dmat; 219 220 /* power up chip */ 221 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 222 pci_activate_null)) && error != EOPNOTSUPP) { 223 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 224 return; 225 } 226 227 /* Enable the device (set bus master flag) */ 228 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 229 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 230 reg | PCI_COMMAND_MASTER_ENABLE); 231 232 #if 0 233 /* LATENCY_TIMER setting */ 234 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 235 if (PCI_LATTIMER(temp1) < 32) { 236 temp1 &= 0xffff00ff; 237 temp1 |= 0x00002000; 238 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 239 } 240 #endif 241 242 /* Map and establish the interrupt. */ 243 if (pci_intr_map(pa, &sc->intrh)) { 244 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 245 return; 246 } 247 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 248 249 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 250 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 251 252 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->intrh, IPL_AUDIO, 253 cs4281_intr, sc, device_xname(self)); 254 if (sc->sc_ih == NULL) { 255 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 256 if (intrstr != NULL) 257 aprint_error(" at %s", intrstr); 258 aprint_error("\n"); 259 mutex_destroy(&sc->sc_lock); 260 mutex_destroy(&sc->sc_intr_lock); 261 return; 262 } 263 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 264 265 /* 266 * Sound System start-up 267 */ 268 if (cs4281_init(sc, 1) != 0) { 269 mutex_destroy(&sc->sc_lock); 270 mutex_destroy(&sc->sc_intr_lock); 271 return; 272 } 273 274 sc->type = TYPE_CS4281; 275 276 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 277 sc->dma_align = 0x10; 278 sc->hw_blocksize = sc->dma_size / 2; 279 280 /* AC 97 attachment */ 281 sc->host_if.arg = sc; 282 sc->host_if.attach = cs428x_attach_codec; 283 sc->host_if.read = cs428x_read_codec; 284 sc->host_if.write = cs428x_write_codec; 285 sc->host_if.reset = cs4281_reset_codec; 286 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 287 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 288 mutex_destroy(&sc->sc_lock); 289 mutex_destroy(&sc->sc_intr_lock); 290 return; 291 } 292 audio_attach_mi(&cs4281_hw_if, sc, sc->sc_dev); 293 294 #if NMIDI > 0 && 0 295 midi_attach_mi(&cs4281_midi_hw_if, sc, sc->sc_dev); 296 #endif 297 298 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 299 aprint_error_dev(self, "couldn't establish power handler\n"); 300 } 301 302 static int 303 cs4281_intr(void *p) 304 { 305 struct cs428x_softc *sc; 306 uint32_t intr, hdsr0, hdsr1; 307 char *empty_dma; 308 int handled; 309 310 sc = p; 311 handled = 0; 312 hdsr0 = 0; 313 hdsr1 = 0; 314 315 mutex_spin_enter(&sc->sc_intr_lock); 316 317 /* grab interrupt register */ 318 intr = BA0READ4(sc, CS4281_HISR); 319 320 DPRINTF(("cs4281_intr:")); 321 /* not for me */ 322 if ((intr & HISR_INTENA) == 0) { 323 /* clear the interrupt register */ 324 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 325 mutex_spin_exit(&sc->sc_intr_lock); 326 return 0; 327 } 328 329 if (intr & HISR_DMA0) 330 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 331 if (intr & HISR_DMA1) 332 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 333 /* clear the interrupt register */ 334 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 335 336 #ifdef CS4280_DEBUG 337 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 338 intr, hdsr0, hdsr1)); 339 #else 340 __USE(hdsr0); 341 __USE(hdsr1); 342 #endif 343 344 /* Playback Interrupt */ 345 if (intr & HISR_DMA0) { 346 handled = 1; 347 if (sc->sc_prun) { 348 DPRINTF((" PB DMA 0x%x(%d)", 349 (int)BA0READ4(sc, CS4281_DCA0), 350 (int)BA0READ4(sc, CS4281_DCC0))); 351 if ((sc->sc_pi%sc->sc_pcount) == 0) 352 sc->sc_pintr(sc->sc_parg); 353 /* copy buffer */ 354 ++sc->sc_pi; 355 empty_dma = sc->sc_pdma->addr; 356 if (sc->sc_pi&1) 357 empty_dma += sc->hw_blocksize; 358 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 359 sc->sc_pn += sc->hw_blocksize; 360 if (sc->sc_pn >= sc->sc_pe) 361 sc->sc_pn = sc->sc_ps; 362 } else { 363 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 364 } 365 } 366 if (intr & HISR_DMA1) { 367 handled = 1; 368 if (sc->sc_rrun) { 369 /* copy from DMA */ 370 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 371 (int)BA0READ4(sc, CS4281_DCC1))); 372 ++sc->sc_ri; 373 empty_dma = sc->sc_rdma->addr; 374 if ((sc->sc_ri & 1) == 0) 375 empty_dma += sc->hw_blocksize; 376 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 377 sc->sc_rn += sc->hw_blocksize; 378 if (sc->sc_rn >= sc->sc_re) 379 sc->sc_rn = sc->sc_rs; 380 if ((sc->sc_ri % sc->sc_rcount) == 0) 381 sc->sc_rintr(sc->sc_rarg); 382 } else { 383 aprint_error_dev(sc->sc_dev, 384 "unexpected record intr\n"); 385 } 386 } 387 DPRINTF(("\n")); 388 389 mutex_spin_exit(&sc->sc_intr_lock); 390 391 return handled; 392 } 393 394 static int 395 cs4281_query_format(void *addr, audio_format_query_t *afp) 396 { 397 398 return audio_query_format(cs4281_formats, CS4281_NFORMATS, afp); 399 } 400 401 static int 402 cs4281_set_format(void *addr, int setmode, 403 const audio_params_t *play, const audio_params_t *rec, 404 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 405 { 406 struct cs428x_softc *sc; 407 408 sc = addr; 409 /* set sample rate */ 410 cs4281_set_dac_rate(sc, play->sample_rate); 411 cs4281_set_adc_rate(sc, rec->sample_rate); 412 return 0; 413 } 414 415 static int 416 cs4281_halt_output(void *addr) 417 { 418 struct cs428x_softc *sc; 419 420 sc = addr; 421 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 422 sc->sc_prun = 0; 423 return 0; 424 } 425 426 static int 427 cs4281_halt_input(void *addr) 428 { 429 struct cs428x_softc *sc; 430 431 sc = addr; 432 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 433 sc->sc_rrun = 0; 434 return 0; 435 } 436 437 static int 438 cs4281_getdev(void *addr, struct audio_device *retp) 439 { 440 441 *retp = cs4281_device; 442 return 0; 443 } 444 445 static int 446 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 447 void (*intr)(void *), void *arg, 448 const audio_params_t *param) 449 { 450 struct cs428x_softc *sc; 451 uint32_t fmt; 452 struct cs428x_dma *p; 453 int dma_count; 454 455 sc = addr; 456 fmt = 0; 457 #ifdef DIAGNOSTIC 458 if (sc->sc_prun) 459 printf("cs4281_trigger_output: already running\n"); 460 #endif 461 sc->sc_prun = 1; 462 463 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 464 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 465 sc->sc_pintr = intr; 466 sc->sc_parg = arg; 467 468 /* stop playback DMA */ 469 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 470 471 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 472 param->precision, param->channels, param->encoding)); 473 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 474 continue; 475 if (p == NULL) { 476 printf("cs4281_trigger_output: bad addr %p\n", start); 477 return EINVAL; 478 } 479 480 sc->sc_pcount = blksize / sc->hw_blocksize; 481 sc->sc_ps = (char *)start; 482 sc->sc_pe = (char *)end; 483 sc->sc_pdma = p; 484 sc->sc_pbuf = KERNADDR(p); 485 sc->sc_pi = 0; 486 sc->sc_pn = sc->sc_ps; 487 if (blksize >= sc->dma_size) { 488 sc->sc_pn = sc->sc_ps + sc->dma_size; 489 memcpy(sc->sc_pbuf, start, sc->dma_size); 490 ++sc->sc_pi; 491 } else { 492 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 493 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 494 } 495 496 dma_count = sc->dma_size; 497 if (param->precision != 8) 498 dma_count /= 2; /* 16 bit */ 499 if (param->channels > 1) 500 dma_count /= 2; /* Stereo */ 501 502 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 503 (int)DMAADDR(p), dma_count)); 504 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 505 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 506 507 /* set playback format */ 508 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 509 if (param->encoding == AUDIO_ENCODING_SLINEAR_BE) 510 fmt |= DMRn_BEND; 511 BA0WRITE4(sc, CS4281_DMR0, fmt); 512 513 /* set sample rate */ 514 sc->sc_prate = param->sample_rate; 515 cs4281_set_dac_rate(sc, param->sample_rate); 516 517 /* start DMA */ 518 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 519 /* Enable interrupts */ 520 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 521 522 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 523 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 524 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 525 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 526 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 527 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 528 BA0READ4(sc, CS4281_DACSR))); 529 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 530 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 531 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 532 533 return 0; 534 } 535 536 static int 537 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 538 void (*intr)(void *), void *arg, 539 const audio_params_t *param) 540 { 541 struct cs428x_softc *sc; 542 struct cs428x_dma *p; 543 uint32_t fmt; 544 int dma_count; 545 546 sc = addr; 547 fmt = 0; 548 #ifdef DIAGNOSTIC 549 if (sc->sc_rrun) 550 printf("cs4281_trigger_input: already running\n"); 551 #endif 552 sc->sc_rrun = 1; 553 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 554 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 555 sc->sc_rintr = intr; 556 sc->sc_rarg = arg; 557 558 /* stop recording DMA */ 559 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 560 561 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 562 continue; 563 if (!p) { 564 printf("cs4281_trigger_input: bad addr %p\n", start); 565 return EINVAL; 566 } 567 568 sc->sc_rcount = blksize / sc->hw_blocksize; 569 sc->sc_rs = (char *)start; 570 sc->sc_re = (char *)end; 571 sc->sc_rdma = p; 572 sc->sc_rbuf = KERNADDR(p); 573 sc->sc_ri = 0; 574 sc->sc_rn = sc->sc_rs; 575 576 dma_count = sc->dma_size; 577 if (param->precision != 8) 578 dma_count /= 2; 579 if (param->channels > 1) 580 dma_count /= 2; 581 582 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 583 (int)DMAADDR(p), dma_count)); 584 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 585 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 586 587 /* set recording format */ 588 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 589 if (param->encoding == AUDIO_ENCODING_SLINEAR_BE) 590 fmt |= DMRn_BEND; 591 BA0WRITE4(sc, CS4281_DMR1, fmt); 592 593 /* set sample rate */ 594 sc->sc_rrate = param->sample_rate; 595 cs4281_set_adc_rate(sc, param->sample_rate); 596 597 /* Start DMA */ 598 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 599 /* Enable interrupts */ 600 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 601 602 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 603 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 604 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 605 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 606 607 return 0; 608 } 609 610 static bool 611 cs4281_suspend(device_t dv, const pmf_qual_t *qual) 612 { 613 struct cs428x_softc *sc = device_private(dv); 614 615 mutex_enter(&sc->sc_lock); 616 mutex_spin_exit(&sc->sc_intr_lock); 617 618 /* save current playback status */ 619 if (sc->sc_prun) { 620 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 621 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 622 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 623 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 624 } 625 626 /* save current capture status */ 627 if (sc->sc_rrun) { 628 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 629 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 630 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 631 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 632 } 633 /* Stop DMA */ 634 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 635 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 636 637 mutex_spin_exit(&sc->sc_intr_lock); 638 mutex_exit(&sc->sc_lock); 639 640 return true; 641 } 642 643 static bool 644 cs4281_resume(device_t dv, const pmf_qual_t *qual) 645 { 646 struct cs428x_softc *sc = device_private(dv); 647 648 mutex_enter(&sc->sc_lock); 649 mutex_spin_enter(&sc->sc_intr_lock); 650 651 cs4281_init(sc, 0); 652 cs4281_reset_codec(sc); 653 654 /* restore ac97 registers */ 655 mutex_spin_exit(&sc->sc_intr_lock); 656 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 657 mutex_spin_enter(&sc->sc_intr_lock); 658 659 /* restore DMA related status */ 660 if (sc->sc_prun) { 661 cs4281_set_dac_rate(sc, sc->sc_prate); 662 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 663 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 664 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 665 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 666 } 667 if (sc->sc_rrun) { 668 cs4281_set_adc_rate(sc, sc->sc_rrate); 669 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 670 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 671 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 672 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 673 } 674 /* enable intterupts */ 675 if (sc->sc_prun || sc->sc_rrun) 676 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 677 678 mutex_spin_exit(&sc->sc_intr_lock); 679 mutex_exit(&sc->sc_lock); 680 681 return true; 682 } 683 684 /* control AC97 codec */ 685 static int 686 cs4281_reset_codec(void *addr) 687 { 688 struct cs428x_softc *sc; 689 uint16_t data; 690 uint32_t dat32; 691 int n; 692 693 sc = addr; 694 695 DPRINTFN(3, ("cs4281_reset_codec\n")); 696 697 /* Reset codec */ 698 BA0WRITE4(sc, CS428X_ACCTL, 0); 699 delay(50); /* delay 50us */ 700 701 BA0WRITE4(sc, CS4281_SPMC, 0); 702 delay(100); /* delay 100us */ 703 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 704 #if defined(ENABLE_SECONDARY_CODEC) 705 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 706 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 707 #endif 708 delay(50000); /* XXX: delay 50ms */ 709 710 /* Enable ASYNC generation */ 711 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 712 713 /* Wait for codec ready. Linux driver waits 50ms here */ 714 n = 0; 715 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 716 delay(100); 717 if (++n > 1000) { 718 printf("reset_codec: AC97 codec ready timeout\n"); 719 return ETIMEDOUT; 720 } 721 } 722 #if defined(ENABLE_SECONDARY_CODEC) 723 /* secondary codec ready*/ 724 n = 0; 725 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 726 delay(100); 727 if (++n > 1000) 728 return 0; 729 } 730 #endif 731 /* Set the serial timing configuration */ 732 /* XXX: undocumented but the Linux driver do this */ 733 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 734 735 /* Wait for codec ready signal */ 736 n = 0; 737 do { 738 delay(1000); 739 if (++n > 1000) { 740 aprint_error_dev(sc->sc_dev, 741 "timeout waiting for codec ready\n"); 742 return ETIMEDOUT; 743 } 744 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 745 } while (dat32 == 0); 746 747 /* Enable Valid Frame output on ASDOUT */ 748 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 749 750 /* Wait until codec calibration is finished. Codec register 26h */ 751 n = 0; 752 do { 753 delay(1); 754 if (++n > 1000) { 755 aprint_error_dev(sc->sc_dev, 756 "timeout waiting for codec calibration\n"); 757 return ETIMEDOUT; 758 } 759 cs428x_read_codec(sc, AC97_REG_POWER, &data); 760 } while ((data & 0x0f) != 0x0f); 761 762 /* Set the serial timing configuration again */ 763 /* XXX: undocumented but the Linux driver do this */ 764 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 765 766 /* Wait until we've sampled input slots 3 & 4 as valid */ 767 n = 0; 768 do { 769 delay(1000); 770 if (++n > 1000) { 771 aprint_error_dev(sc->sc_dev, "timeout waiting for " 772 "sampled input slots as valid\n"); 773 return ETIMEDOUT; 774 } 775 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 776 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 777 778 /* Start digital data transfer of audio data to the codec */ 779 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 780 return 0; 781 } 782 783 784 /* Internal functions */ 785 786 /* convert sample rate to register value */ 787 static uint8_t 788 cs4281_sr2regval(int rate) 789 { 790 uint8_t retval; 791 792 /* We don't have to change here. but anyway ... */ 793 if (rate > 48000) 794 rate = 48000; 795 if (rate < 6023) 796 rate = 6023; 797 798 switch (rate) { 799 case 8000: 800 retval = 5; 801 break; 802 case 11025: 803 retval = 4; 804 break; 805 case 16000: 806 retval = 3; 807 break; 808 case 22050: 809 retval = 2; 810 break; 811 case 44100: 812 retval = 1; 813 break; 814 case 48000: 815 retval = 0; 816 break; 817 default: 818 retval = 1536000/rate; /* == 24576000/(rate*16) */ 819 } 820 return retval; 821 } 822 823 static void 824 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 825 { 826 827 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 828 } 829 830 static void 831 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 832 { 833 834 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 835 } 836 837 static int 838 cs4281_init(struct cs428x_softc *sc, int init) 839 { 840 int n; 841 uint16_t data; 842 uint32_t dat32; 843 844 /* set "Configuration Write Protect" register to 845 * 0x4281 to allow to write */ 846 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 847 848 /* 849 * Unset "Full Power-Down bit of Extended PCI Power Management 850 * Control" register to release the reset state. 851 */ 852 dat32 = BA0READ4(sc, CS4281_EPPMC); 853 if (dat32 & EPPMC_FPDN) { 854 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 855 } 856 857 /* Start PLL out in known state */ 858 BA0WRITE4(sc, CS4281_CLKCR1, 0); 859 /* Start serial ports out in known state */ 860 BA0WRITE4(sc, CS4281_SERMC, 0); 861 862 /* Reset codec */ 863 BA0WRITE4(sc, CS428X_ACCTL, 0); 864 delay(50); /* delay 50us */ 865 866 BA0WRITE4(sc, CS4281_SPMC, 0); 867 delay(100); /* delay 100us */ 868 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 869 #if defined(ENABLE_SECONDARY_CODEC) 870 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 871 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 872 #endif 873 delay(50000); /* XXX: delay 50ms */ 874 875 /* Turn on Sound System clocks based on ABITCLK */ 876 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 877 delay(50000); /* XXX: delay 50ms */ 878 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 879 880 /* Set enables for sections that are needed in the SSPM registers */ 881 BA0WRITE4(sc, CS4281_SSPM, 882 SSPM_MIXEN | /* Mixer */ 883 SSPM_CSRCEN | /* Capture SRC */ 884 SSPM_PSRCEN | /* Playback SRC */ 885 SSPM_JSEN | /* Joystick */ 886 SSPM_ACLEN | /* AC LINK */ 887 SSPM_FMEN /* FM */ 888 ); 889 890 /* Wait for clock stabilization */ 891 n = 0; 892 #if 1 893 /* what document says */ 894 while ((BA0READ4(sc, CS4281_CLKCR1) & (CLKCR1_DLLRDY | CLKCR1_CLKON)) 895 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 896 delay(100); 897 if (++n > 1000) { 898 aprint_error_dev(sc->sc_dev, 899 "timeout waiting for clock stabilization\n"); 900 return -1; 901 } 902 } 903 #else 904 /* Cirrus driver for Linux does */ 905 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 906 delay(1000); 907 if (++n > 1000) { 908 aprint_error_dev(sc->sc_dev, 909 "timeout waiting for clock stabilization\n"); 910 return -1; 911 } 912 } 913 #endif 914 915 /* Enable ASYNC generation */ 916 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 917 918 /* Wait for codec ready. Linux driver waits 50ms here */ 919 n = 0; 920 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 921 delay(100); 922 if (++n > 1000) { 923 aprint_error_dev(sc->sc_dev, 924 "timeout waiting for codec ready\n"); 925 return -1; 926 } 927 } 928 929 #if defined(ENABLE_SECONDARY_CODEC) 930 /* secondary codec ready*/ 931 n = 0; 932 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 933 delay(100); 934 if (++n > 1000) { 935 aprint_error_dev(sc->sc_dev, 936 "timeout waiting for secondary codec ready\n"); 937 return -1; 938 } 939 } 940 #endif 941 942 /* Set the serial timing configuration */ 943 /* XXX: undocumented but the Linux driver do this */ 944 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 945 946 /* Wait for codec ready signal */ 947 n = 0; 948 do { 949 delay(1000); 950 if (++n > 1000) { 951 aprint_error_dev(sc->sc_dev, 952 "timeout waiting for codec ready\n"); 953 return -1; 954 } 955 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 956 } while (dat32 == 0); 957 958 /* Enable Valid Frame output on ASDOUT */ 959 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 960 961 /* Wait until codec calibration is finished. codec register 26h */ 962 n = 0; 963 do { 964 delay(1); 965 if (++n > 1000) { 966 aprint_error_dev(sc->sc_dev, 967 "timeout waiting for codec calibration\n"); 968 return -1; 969 } 970 cs428x_read_codec(sc, AC97_REG_POWER, &data); 971 } while ((data & 0x0f) != 0x0f); 972 973 /* Set the serial timing configuration again */ 974 /* XXX: undocumented but the Linux driver do this */ 975 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 976 977 /* Wait until we've sampled input slots 3 & 4 as valid */ 978 n = 0; 979 do { 980 delay(1000); 981 if (++n > 1000) { 982 aprint_error_dev(sc->sc_dev, "timeout waiting for " 983 "sampled input slots as valid\n"); 984 return -1; 985 } 986 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 987 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 988 989 /* Start digital data transfer of audio data to the codec */ 990 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 991 992 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 993 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 994 995 /* Power on the DAC */ 996 cs428x_read_codec(sc, AC97_REG_POWER, &data); 997 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 998 999 /* Wait until we sample a DAC ready state. 1000 * Not documented, but Linux driver does. 1001 */ 1002 for (n = 0; n < 32; ++n) { 1003 delay(1000); 1004 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1005 if (data & 0x02) 1006 break; 1007 } 1008 1009 /* Power on the ADC */ 1010 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1011 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1012 1013 /* Wait until we sample ADC ready state. 1014 * Not documented, but Linux driver does. 1015 */ 1016 for (n = 0; n < 32; ++n) { 1017 delay(1000); 1018 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1019 if (data & 0x01) 1020 break; 1021 } 1022 1023 #if 0 1024 /* Initialize AC-Link features */ 1025 /* variable sample-rate support */ 1026 mem = BA0READ4(sc, CS4281_SERMC); 1027 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1028 BA0WRITE4(sc, CS4281_SERMC, mem); 1029 /* XXX: more... */ 1030 1031 /* Initialize SSCR register features */ 1032 /* XXX: hardware volume setting */ 1033 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1034 #endif 1035 1036 /* disable Sound Blaster Pro emulation */ 1037 /* XXX: 1038 * Cannot set since the documents does not describe which bit is 1039 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1040 * we can ignore it.*/ 1041 #if 0 1042 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1043 #endif 1044 1045 /* map AC97 PCM playback to DMA Channel 0 */ 1046 /* Reset FEN bit to setup first */ 1047 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1048 /* 1049 *| RS[4:0]/| | 1050 *| LS[4:0] | AC97 | Slot Function 1051 *|---------+--------+-------------------- 1052 *| 0 | 3 | Left PCM Playback 1053 *| 1 | 4 | Right PCM Playback 1054 *| 2 | 5 | Phone Line 1 DAC 1055 *| 3 | 6 | Center PCM Playback 1056 *.... 1057 * quoted from Table 29(p109) 1058 */ 1059 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1060 0x00 << 16 | /* LS[4:0] = 0 see above */ 1061 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1062 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1063 BA0WRITE4(sc, CS4281_FCR0, dat32); 1064 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1065 1066 /* map AC97 PCM record to DMA Channel 1 */ 1067 /* Reset FEN bit to setup first */ 1068 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1069 /* 1070 *| RS[4:0]/| 1071 *| LS[4:0] | AC97 | Slot Function 1072 *|---------+------+------------------- 1073 *| 10 | 3 | Left PCM Record 1074 *| 11 | 4 | Right PCM Record 1075 *| 12 | 5 | Phone Line 1 ADC 1076 *| 13 | 6 | Mic ADC 1077 *.... 1078 * quoted from Table 30(p109) 1079 */ 1080 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1081 0x0a << 16 | /* LS[4:0] = 10 See above */ 1082 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1083 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1084 1085 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1086 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1087 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1088 1089 #if 0 1090 /* Disable DMA Channel 2, 3 */ 1091 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1092 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1093 #endif 1094 1095 /* Set the SRC Slot Assignment accordingly */ 1096 /*| PLSS[4:0]/ 1097 *| PRSS[4:0] | AC97 | Slot Function 1098 *|-----------+------+---------------- 1099 *| 0 | 3 | Left PCM Playback 1100 *| 1 | 4 | Right PCM Playback 1101 *| 2 | 5 | phone line 1 DAC 1102 *| 3 | 6 | Center PCM Playback 1103 *| 4 | 7 | Left Surround PCM Playback 1104 *| 5 | 8 | Right Surround PCM Playback 1105 *...... 1106 * 1107 *| CLSS[4:0]/ 1108 *| CRSS[4:0] | AC97 | Codec |Slot Function 1109 *|-----------+------+-------+----------------- 1110 *| 10 | 3 |Primary| Left PCM Record 1111 *| 11 | 4 |Primary| Right PCM Record 1112 *| 12 | 5 |Primary| Phone Line 1 ADC 1113 *| 13 | 6 |Primary| Mic ADC 1114 *|..... 1115 *| 20 | 3 | Sec. | Left PCM Record 1116 *| 21 | 4 | Sec. | Right PCM Record 1117 *| 22 | 5 | Sec. | Phone Line 1 ADC 1118 *| 23 | 6 | Sec. | Mic ADC 1119 */ 1120 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1121 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1122 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1123 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1124 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1125 1126 /* Set interrupt to occurred at Half and Full terminal 1127 * count interrupt enable for DMA channel 0 and 1. 1128 * To keep DMA stop, set MSK. 1129 */ 1130 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1131 BA0WRITE4(sc, CS4281_DCR0, dat32); 1132 BA0WRITE4(sc, CS4281_DCR1, dat32); 1133 1134 /* Set Auto-Initialize Contorl enable */ 1135 BA0WRITE4(sc, CS4281_DMR0, 1136 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1137 BA0WRITE4(sc, CS4281_DMR1, 1138 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1139 1140 /* Clear DMA Mask in HIMR */ 1141 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1142 BA0WRITE4(sc, CS4281_HIMR, 1143 BA0READ4(sc, CS4281_HIMR) & dat32); 1144 1145 /* set current status */ 1146 if (init != 0) { 1147 sc->sc_prun = 0; 1148 sc->sc_rrun = 0; 1149 } 1150 1151 /* setup playback volume */ 1152 BA0WRITE4(sc, CS4281_PPRVC, 7); 1153 BA0WRITE4(sc, CS4281_PPLVC, 7); 1154 1155 return 0; 1156 } 1157
Indexes created Thu Oct 02 10:09:58 GMT 2025