cs4281.c revision 1.6
1 /* $NetBSD: cs4281.c,v 1.6 2001/10/03 00:04:52 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/malloc.h> 49 #include <sys/fcntl.h> 50 #include <sys/device.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 54 #include <dev/pci/pcidevs.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/cs4281reg.h> 57 #include <dev/pci/cs428xreg.h> 58 59 #include <sys/audioio.h> 60 #include <dev/audio_if.h> 61 #include <dev/midi_if.h> 62 #include <dev/mulaw.h> 63 #include <dev/auconv.h> 64 65 #include <dev/ic/ac97reg.h> 66 #include <dev/ic/ac97var.h> 67 68 #include <dev/pci/cs428x.h> 69 70 #include <machine/bus.h> 71 72 #if defined(ENABLE_SECONDARY_CODEC) 73 #define MAX_CHANNELS (4) 74 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 75 #else 76 #define MAX_CHANNELS (2) 77 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 78 #endif 79 80 /* IF functions for audio driver */ 81 int cs4281_match(struct device *, struct cfdata *, void *); 82 void cs4281_attach(struct device *, struct device *, void *); 83 int cs4281_intr(void *); 84 int cs4281_query_encoding(void *, struct audio_encoding *); 85 int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 86 int cs4281_halt_output(void *); 87 int cs4281_halt_input(void *); 88 int cs4281_getdev(void *, struct audio_device *); 89 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 90 void *, struct audio_params *); 91 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 92 void *, struct audio_params *); 93 94 void cs4281_reset_codec(void *); 95 96 /* Internal functions */ 97 u_int8_t cs4281_sr2regval(int); 98 void cs4281_set_dac_rate(struct cs428x_softc *, int); 99 void cs4281_set_adc_rate(struct cs428x_softc *, int); 100 int cs4281_init(struct cs428x_softc *, int); 101 102 /* Power Management */ 103 void cs4281_power(int, void *); 104 105 struct audio_hw_if cs4281_hw_if = { 106 cs428x_open, 107 cs428x_close, 108 NULL, 109 cs4281_query_encoding, 110 cs4281_set_params, 111 cs428x_round_blocksize, 112 NULL, 113 NULL, 114 NULL, 115 NULL, 116 NULL, 117 cs4281_halt_output, 118 cs4281_halt_input, 119 NULL, 120 cs4281_getdev, 121 NULL, 122 cs428x_mixer_set_port, 123 cs428x_mixer_get_port, 124 cs428x_query_devinfo, 125 cs428x_malloc, 126 cs428x_free, 127 cs428x_round_buffersize, 128 cs428x_mappage, 129 cs428x_get_props, 130 cs4281_trigger_output, 131 cs4281_trigger_input, 132 NULL, 133 }; 134 135 #if NMIDI > 0 && 0 136 /* Midi Interface */ 137 void cs4281_midi_close(void*); 138 void cs4281_midi_getinfo(void *, struct midi_info *); 139 int cs4281_midi_open(void *, int, void (*)(void *, int), 140 void (*)(void *), void *); 141 int cs4281_midi_output(void *, int); 142 143 struct midi_hw_if cs4281_midi_hw_if = { 144 cs4281_midi_open, 145 cs4281_midi_close, 146 cs4281_midi_output, 147 cs4281_midi_getinfo, 148 0, 149 }; 150 #endif 151 152 struct cfattach clct_ca = { 153 sizeof(struct cs428x_softc), cs4281_match, cs4281_attach 154 }; 155 156 struct audio_device cs4281_device = { 157 "CS4281", 158 "", 159 "cs4281" 160 }; 161 162 163 int 164 cs4281_match(parent, match, aux) 165 struct device *parent; 166 struct cfdata *match; 167 void *aux; 168 { 169 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 170 171 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 172 return 0; 173 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 174 return 1; 175 return 0; 176 } 177 178 void 179 cs4281_attach(parent, self, aux) 180 struct device *parent; 181 struct device *self; 182 void *aux; 183 { 184 struct cs428x_softc *sc = (struct cs428x_softc *)self; 185 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 186 pci_chipset_tag_t pc = pa->pa_pc; 187 char const *intrstr; 188 pci_intr_handle_t ih; 189 pcireg_t reg; 190 char devinfo[256]; 191 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 192 193 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 194 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 195 196 /* Map I/O register */ 197 if (pci_mapreg_map(pa, PCI_BA0, 198 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 199 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 200 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 201 return; 202 } 203 if (pci_mapreg_map(pa, PCI_BA1, 204 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 205 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 206 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 207 return; 208 } 209 210 sc->sc_dmatag = pa->pa_dmat; 211 212 /* 213 * Set Power State D0. 214 * Without do this, 0xffffffff is read from all registers after 215 * using Windows. 216 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 217 */ 218 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 219 &pci_pwrmgmt_cap_reg, 0)) { 220 221 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 222 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 223 pci_pwrmgmt_csr_reg); 224 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 225 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 226 (reg & ~PCI_PMCSR_STATE_MASK) | 227 PCI_PMCSR_STATE_D0); 228 } 229 } 230 231 /* Enable the device (set bus master flag) */ 232 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 233 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 234 reg | PCI_COMMAND_MASTER_ENABLE); 235 236 #if 0 237 /* LATENCY_TIMER setting */ 238 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 239 if ( PCI_LATTIMER(temp1) < 32 ) { 240 temp1 &= 0xffff00ff; 241 temp1 |= 0x00002000; 242 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 243 } 244 #endif 245 246 /* Map and establish the interrupt. */ 247 if (pci_intr_map(pa, &ih)) { 248 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 249 return; 250 } 251 intrstr = pci_intr_string(pc, ih); 252 253 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 254 if (sc->sc_ih == NULL) { 255 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 256 if (intrstr != NULL) 257 printf(" at %s", intrstr); 258 printf("\n"); 259 return; 260 } 261 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 262 263 /* 264 * Sound System start-up 265 */ 266 if (cs4281_init(sc,1) != 0) 267 return; 268 269 sc->type = TYPE_CS4281; 270 sc->halt_input = cs4281_halt_input; 271 sc->halt_output = cs4281_halt_output; 272 273 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 274 sc->dma_align = 0x10; 275 sc->hw_blocksize = sc->dma_size / 2; 276 277 /* AC 97 attachment */ 278 sc->host_if.arg = sc; 279 sc->host_if.attach = cs428x_attach_codec; 280 sc->host_if.read = cs428x_read_codec; 281 sc->host_if.write = cs428x_write_codec; 282 sc->host_if.reset = cs4281_reset_codec; 283 if (ac97_attach(&sc->host_if) != 0) { 284 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 285 return; 286 } 287 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 288 289 #if NMIDI > 0 && 0 290 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 291 #endif 292 293 sc->sc_suspend = PWR_RESUME; 294 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 295 } 296 297 int 298 cs4281_intr(p) 299 void *p; 300 { 301 struct cs428x_softc *sc = p; 302 u_int32_t intr, hdsr0, hdsr1; 303 char *empty_dma; 304 int handled = 0; 305 306 hdsr0 = 0; 307 hdsr1 = 0; 308 309 /* grab interrupt register */ 310 intr = BA0READ4(sc, CS4281_HISR); 311 312 DPRINTF(("cs4281_intr:")); 313 /* not for me */ 314 if ((intr & HISR_INTENA) == 0) { 315 /* clear the interrupt register */ 316 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 317 return 0; 318 } 319 320 if (intr & HISR_DMA0) 321 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 322 if (intr & HISR_DMA1) 323 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 324 /* clear the interrupt register */ 325 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 326 327 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 328 intr, hdsr0, hdsr1)); 329 330 /* Playback Interrupt */ 331 if (intr & HISR_DMA0) { 332 handled = 1; 333 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 334 (int)BA0READ4(sc, CS4281_DCC0))); 335 if (sc->sc_pintr) { 336 if ((sc->sc_pi%sc->sc_pcount) == 0) 337 sc->sc_pintr(sc->sc_parg); 338 } else { 339 printf("unexpected play intr\n"); 340 } 341 /* copy buffer */ 342 ++sc->sc_pi; 343 empty_dma = sc->sc_pdma->addr; 344 if (sc->sc_pi&1) 345 empty_dma += sc->hw_blocksize; 346 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 347 sc->sc_pn += sc->hw_blocksize; 348 if (sc->sc_pn >= sc->sc_pe) 349 sc->sc_pn = sc->sc_ps; 350 } 351 if (intr & HISR_DMA1) { 352 handled = 1; 353 /* copy from dma */ 354 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 355 (int)BA0READ4(sc, CS4281_DCC1))); 356 ++sc->sc_ri; 357 empty_dma = sc->sc_rdma->addr; 358 if ((sc->sc_ri & 1) == 0) 359 empty_dma += sc->hw_blocksize; 360 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 361 if (sc->sc_rn >= sc->sc_re) 362 sc->sc_rn = sc->sc_rs; 363 if (sc->sc_rintr) { 364 if ((sc->sc_ri % sc->sc_rcount) == 0) 365 sc->sc_rintr(sc->sc_rarg); 366 } else { 367 printf("unexpected record intr\n"); 368 } 369 } 370 DPRINTF(("\n")); 371 372 return handled; 373 } 374 375 int 376 cs4281_query_encoding(addr, fp) 377 void *addr; 378 struct audio_encoding *fp; 379 { 380 switch (fp->index) { 381 case 0: 382 strcpy(fp->name, AudioEulinear); 383 fp->encoding = AUDIO_ENCODING_ULINEAR; 384 fp->precision = 8; 385 fp->flags = 0; 386 break; 387 case 1: 388 strcpy(fp->name, AudioEmulaw); 389 fp->encoding = AUDIO_ENCODING_ULAW; 390 fp->precision = 8; 391 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 392 break; 393 case 2: 394 strcpy(fp->name, AudioEalaw); 395 fp->encoding = AUDIO_ENCODING_ALAW; 396 fp->precision = 8; 397 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 398 break; 399 case 3: 400 strcpy(fp->name, AudioEslinear); 401 fp->encoding = AUDIO_ENCODING_SLINEAR; 402 fp->precision = 8; 403 fp->flags = 0; 404 break; 405 case 4: 406 strcpy(fp->name, AudioEslinear_le); 407 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 408 fp->precision = 16; 409 fp->flags = 0; 410 break; 411 case 5: 412 strcpy(fp->name, AudioEulinear_le); 413 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 414 fp->precision = 16; 415 fp->flags = 0; 416 break; 417 case 6: 418 strcpy(fp->name, AudioEslinear_be); 419 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 420 fp->precision = 16; 421 fp->flags = 0; 422 break; 423 case 7: 424 strcpy(fp->name, AudioEulinear_be); 425 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 426 fp->precision = 16; 427 fp->flags = 0; 428 break; 429 default: 430 return EINVAL; 431 } 432 return 0; 433 } 434 435 int 436 cs4281_set_params(addr, setmode, usemode, play, rec) 437 void *addr; 438 int setmode, usemode; 439 struct audio_params *play, *rec; 440 { 441 struct cs428x_softc *sc = addr; 442 struct audio_params *p; 443 int mode; 444 445 for (mode = AUMODE_RECORD; mode != -1; 446 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 447 if ((setmode & mode) == 0) 448 continue; 449 450 p = mode == AUMODE_PLAY ? play : rec; 451 452 if (p == play) { 453 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 454 p->sample_rate, p->precision, p->channels)); 455 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 456 (p->precision != 8 && p->precision != 16) || 457 (p->channels != 1 && p->channels != 2)) { 458 return (EINVAL); 459 } 460 } else { 461 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 462 p->sample_rate, p->precision, p->channels)); 463 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 464 (p->precision != 8 && p->precision != 16) || 465 (p->channels != 1 && p->channels != 2)) { 466 return (EINVAL); 467 } 468 } 469 p->factor = 1; 470 p->sw_code = 0; 471 472 switch (p->encoding) { 473 case AUDIO_ENCODING_SLINEAR_BE: 474 break; 475 case AUDIO_ENCODING_SLINEAR_LE: 476 break; 477 case AUDIO_ENCODING_ULINEAR_BE: 478 break; 479 case AUDIO_ENCODING_ULINEAR_LE: 480 break; 481 case AUDIO_ENCODING_ULAW: 482 if (mode == AUMODE_PLAY) { 483 p->sw_code = mulaw_to_slinear8; 484 } else { 485 p->sw_code = slinear8_to_mulaw; 486 } 487 break; 488 case AUDIO_ENCODING_ALAW: 489 if (mode == AUMODE_PLAY) { 490 p->sw_code = alaw_to_slinear8; 491 } else { 492 p->sw_code = slinear8_to_alaw; 493 } 494 break; 495 default: 496 return (EINVAL); 497 } 498 } 499 500 /* set sample rate */ 501 cs4281_set_dac_rate(sc, play->sample_rate); 502 cs4281_set_adc_rate(sc, rec->sample_rate); 503 return 0; 504 } 505 506 int 507 cs4281_halt_output(addr) 508 void *addr; 509 { 510 struct cs428x_softc *sc = addr; 511 512 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 513 sc->sc_prun = 0; 514 return 0; 515 } 516 517 int 518 cs4281_halt_input(addr) 519 void *addr; 520 { 521 struct cs428x_softc *sc = addr; 522 523 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 524 sc->sc_rrun = 0; 525 return 0; 526 } 527 528 int 529 cs4281_getdev(addr, retp) 530 void *addr; 531 struct audio_device *retp; 532 { 533 *retp = cs4281_device; 534 return 0; 535 } 536 537 int 538 cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 539 void *addr; 540 void *start, *end; 541 int blksize; 542 void (*intr) __P((void *)); 543 void *arg; 544 struct audio_params *param; 545 { 546 struct cs428x_softc *sc = addr; 547 u_int32_t fmt=0; 548 struct cs428x_dma *p; 549 int dma_count; 550 551 #ifdef DIAGNOSTIC 552 if (sc->sc_prun) 553 printf("cs4281_trigger_output: already running\n"); 554 #endif 555 sc->sc_prun = 1; 556 557 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 558 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 559 sc->sc_pintr = intr; 560 sc->sc_parg = arg; 561 562 /* stop playback DMA */ 563 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 564 565 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 566 param->precision, param->factor, param->channels, 567 param->encoding)); 568 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 569 ; 570 if (p == NULL) { 571 printf("cs4281_trigger_output: bad addr %p\n", start); 572 return (EINVAL); 573 } 574 575 sc->sc_pcount = blksize / sc->hw_blocksize; 576 sc->sc_ps = (char *)start; 577 sc->sc_pe = (char *)end; 578 sc->sc_pdma = p; 579 sc->sc_pbuf = KERNADDR(p); 580 sc->sc_pi = 0; 581 sc->sc_pn = sc->sc_ps; 582 if (blksize >= sc->dma_size) { 583 sc->sc_pn = sc->sc_ps + sc->dma_size; 584 memcpy(sc->sc_pbuf, start, sc->dma_size); 585 ++sc->sc_pi; 586 } else { 587 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 588 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 589 } 590 591 dma_count = sc->dma_size; 592 if (param->precision * param->factor != 8) 593 dma_count /= 2; /* 16 bit */ 594 if (param->channels > 1) 595 dma_count /= 2; /* Stereo */ 596 597 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 598 (int)DMAADDR(p), dma_count)); 599 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 600 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 601 602 /* set playback format */ 603 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 604 if (param->precision * param->factor == 8) 605 fmt |= DMRn_SIZE8; 606 if (param->channels == 1) 607 fmt |= DMRn_MONO; 608 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 609 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 610 fmt |= DMRn_BEND; 611 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 612 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 613 fmt |= DMRn_USIGN; 614 BA0WRITE4(sc, CS4281_DMR0, fmt); 615 616 /* set sample rate */ 617 sc->sc_prate = param->sample_rate; 618 cs4281_set_dac_rate(sc, param->sample_rate); 619 620 /* start DMA */ 621 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 622 /* Enable interrupts */ 623 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 624 625 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 626 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 627 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 628 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 629 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 630 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 631 BA0READ4(sc, CS4281_DACSR))); 632 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 633 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 634 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 635 636 return 0; 637 } 638 639 int 640 cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 641 void *addr; 642 void *start, *end; 643 int blksize; 644 void (*intr) __P((void *)); 645 void *arg; 646 struct audio_params *param; 647 { 648 struct cs428x_softc *sc = addr; 649 struct cs428x_dma *p; 650 u_int32_t fmt=0; 651 int dma_count; 652 653 printf("cs4281_trigger_input: not implemented yet\n"); 654 #ifdef DIAGNOSTIC 655 if (sc->sc_rrun) 656 printf("cs4281_trigger_input: already running\n"); 657 #endif 658 sc->sc_rrun = 1; 659 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 660 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 661 sc->sc_rintr = intr; 662 sc->sc_rarg = arg; 663 664 /* stop recording DMA */ 665 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 666 667 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 668 ; 669 if (!p) { 670 printf("cs4281_trigger_input: bad addr %p\n", start); 671 return (EINVAL); 672 } 673 674 sc->sc_rcount = blksize / sc->hw_blocksize; 675 sc->sc_rs = (char *)start; 676 sc->sc_re = (char *)end; 677 sc->sc_rdma = p; 678 sc->sc_rbuf = KERNADDR(p); 679 sc->sc_ri = 0; 680 sc->sc_rn = sc->sc_rs; 681 682 dma_count = sc->dma_size; 683 if (param->precision * param->factor == 8) 684 dma_count /= 2; 685 if (param->channels > 1) 686 dma_count /= 2; 687 688 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 689 (int)DMAADDR(p), dma_count)); 690 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 691 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 692 693 /* set recording format */ 694 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 695 if (param->precision * param->factor == 8) 696 fmt |= DMRn_SIZE8; 697 if (param->channels == 1) 698 fmt |= DMRn_MONO; 699 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 700 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 701 fmt |= DMRn_BEND; 702 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 703 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 704 fmt |= DMRn_USIGN; 705 BA0WRITE4(sc, CS4281_DMR1, fmt); 706 707 /* set sample rate */ 708 sc->sc_rrate = param->sample_rate; 709 cs4281_set_adc_rate(sc, param->sample_rate); 710 711 /* Start DMA */ 712 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 713 /* Enable interrupts */ 714 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 715 716 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 717 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 718 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 719 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 720 721 return 0; 722 } 723 724 /* Power Hook */ 725 void 726 cs4281_power(why, v) 727 int why; 728 void *v; 729 { 730 struct cs428x_softc *sc = (struct cs428x_softc *)v; 731 static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 732 static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 733 734 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 735 switch (why) { 736 case PWR_SUSPEND: 737 case PWR_STANDBY: 738 sc->sc_suspend = why; 739 740 /* save current playback status */ 741 if (sc->sc_prun) { 742 dcr0 = BA0READ4(sc, CS4281_DCR0); 743 dmr0 = BA0READ4(sc, CS4281_DMR0); 744 dbc0 = BA0READ4(sc, CS4281_DBC0); 745 dba0 = BA0READ4(sc, CS4281_DBA0); 746 } 747 748 /* save current capture status */ 749 if (sc->sc_rrun) { 750 dcr1 = BA0READ4(sc, CS4281_DCR1); 751 dmr1 = BA0READ4(sc, CS4281_DMR1); 752 dbc1 = BA0READ4(sc, CS4281_DBC1); 753 dba1 = BA0READ4(sc, CS4281_DBA1); 754 } 755 /* Stop DMA */ 756 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 757 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 758 break; 759 case PWR_RESUME: 760 if (sc->sc_suspend == PWR_RESUME) { 761 printf("cs4281_power: odd, resume without suspend.\n"); 762 sc->sc_suspend = why; 763 return; 764 } 765 sc->sc_suspend = why; 766 cs4281_init(sc,0); 767 cs4281_reset_codec(sc); 768 769 /* restore ac97 registers */ 770 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 771 772 /* restore DMA related status */ 773 if (sc->sc_prun) { 774 cs4281_set_dac_rate(sc, sc->sc_prate); 775 BA0WRITE4(sc, CS4281_DBA0, dba0); 776 BA0WRITE4(sc, CS4281_DBC0, dbc0); 777 BA0WRITE4(sc, CS4281_DMR0, dmr0); 778 BA0WRITE4(sc, CS4281_DCR0, dcr0); 779 } 780 if (sc->sc_rrun) { 781 cs4281_set_adc_rate(sc, sc->sc_rrate); 782 BA0WRITE4(sc, CS4281_DBA1, dba1); 783 BA0WRITE4(sc, CS4281_DBC1, dbc1); 784 BA0WRITE4(sc, CS4281_DMR1, dmr1); 785 BA0WRITE4(sc, CS4281_DCR1, dcr1); 786 } 787 /* enable intterupts */ 788 if (sc->sc_prun || sc->sc_rrun) 789 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 790 break; 791 case PWR_SOFTSUSPEND: 792 case PWR_SOFTSTANDBY: 793 case PWR_SOFTRESUME: 794 break; 795 } 796 } 797 798 /* control AC97 codec */ 799 void 800 cs4281_reset_codec(void *addr) 801 { 802 struct cs428x_softc *sc; 803 u_int16_t data; 804 u_int32_t dat32; 805 int n; 806 807 sc = addr; 808 809 DPRINTFN(3,("cs4281_reset_codec\n")); 810 811 /* Reset codec */ 812 BA0WRITE4(sc, CS428X_ACCTL, 0); 813 delay(50); /* delay 50us */ 814 815 BA0WRITE4(sc, CS4281_SPMC, 0); 816 delay(100); /* delay 100us */ 817 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 818 #if defined(ENABLE_SECONDARY_CODEC) 819 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 820 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 821 #endif 822 delay(50000); /* XXX: delay 50ms */ 823 824 /* Enable ASYNC generation */ 825 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 826 827 /* Wait for Codec ready. Linux driver wait 50ms here */ 828 n = 0; 829 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 830 delay(100); 831 if (++n > 1000) { 832 printf("reset_codec: AC97 codec ready timeout\n"); 833 return; 834 } 835 } 836 #if defined(ENABLE_SECONDARY_CODEC) 837 /* secondary codec ready*/ 838 n = 0; 839 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 840 delay(100); 841 if (++n > 1000) 842 return; 843 } 844 #endif 845 /* Set the serial timing configuration */ 846 /* XXX: undocumented but the Linux driver do this */ 847 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 848 849 /* Wait for Codec ready signal */ 850 n = 0; 851 do { 852 delay(1000); 853 if (++n > 1000) { 854 printf("%s: Timeout waiting for Codec ready\n", 855 sc->sc_dev.dv_xname); 856 return; 857 } 858 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 859 } while (dat32 == 0); 860 861 /* Enable Valid Frame output on ASDOUT */ 862 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 863 864 /* Wait until Codec Calibration is finished. Codec register 26h */ 865 n = 0; 866 do { 867 delay(1); 868 if (++n > 1000) { 869 printf("%s: Timeout waiting for Codec calibration\n", 870 sc->sc_dev.dv_xname); 871 return ; 872 } 873 cs428x_read_codec(sc, AC97_REG_POWER, &data); 874 } while ((data & 0x0f) != 0x0f); 875 876 /* Set the serial timing configuration again */ 877 /* XXX: undocumented but the Linux driver do this */ 878 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 879 880 /* Wait until we've sampled input slots 3 & 4 as valid */ 881 n = 0; 882 do { 883 delay(1000); 884 if (++n > 1000) { 885 printf("%s: Timeout waiting for sampled input slots as valid\n", 886 sc->sc_dev.dv_xname); 887 return; 888 } 889 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 890 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 891 892 /* Start digital data transfer of audio data to the codec */ 893 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 894 } 895 896 897 /* Internal functions */ 898 899 /* convert sample rate to register value */ 900 u_int8_t 901 cs4281_sr2regval(rate) 902 int rate; 903 { 904 u_int8_t retval; 905 906 /* We don't have to change here. but anyway ... */ 907 if (rate > 48000) 908 rate = 48000; 909 if (rate < 6023) 910 rate = 6023; 911 912 switch (rate) { 913 case 8000: 914 retval = 5; 915 break; 916 case 11025: 917 retval = 4; 918 break; 919 case 16000: 920 retval = 3; 921 break; 922 case 22050: 923 retval = 2; 924 break; 925 case 44100: 926 retval = 1; 927 break; 928 case 48000: 929 retval = 0; 930 break; 931 default: 932 retval = 1536000/rate; /* == 24576000/(rate*16) */ 933 } 934 return retval; 935 } 936 937 void 938 cs4281_set_adc_rate(sc, rate) 939 struct cs428x_softc *sc; 940 int rate; 941 { 942 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 943 } 944 945 void 946 cs4281_set_dac_rate(sc, rate) 947 struct cs428x_softc *sc; 948 int rate; 949 { 950 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 951 } 952 953 int 954 cs4281_init(sc, init) 955 struct cs428x_softc *sc; 956 int init; 957 { 958 int n; 959 u_int16_t data; 960 u_int32_t dat32; 961 962 /* set "Configuration Write Protect" register to 963 * 0x4281 to allow to write */ 964 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 965 966 /* 967 * Unset "Full Power-Down bit of Extended PCI Power Management 968 * Control" register to release the reset state. 969 */ 970 dat32 = BA0READ4(sc, CS4281_EPPMC); 971 if (dat32 & EPPMC_FPDN) { 972 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 973 } 974 975 /* Start PLL out in known state */ 976 BA0WRITE4(sc, CS4281_CLKCR1, 0); 977 /* Start serial ports out in known state */ 978 BA0WRITE4(sc, CS4281_SERMC, 0); 979 980 /* Reset codec */ 981 BA0WRITE4(sc, CS428X_ACCTL, 0); 982 delay(50); /* delay 50us */ 983 984 BA0WRITE4(sc, CS4281_SPMC, 0); 985 delay(100); /* delay 100us */ 986 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 987 #if defined(ENABLE_SECONDARY_CODEC) 988 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 989 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 990 #endif 991 delay(50000); /* XXX: delay 50ms */ 992 993 /* Turn on Sound System clocks based on ABITCLK */ 994 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 995 delay(50000); /* XXX: delay 50ms */ 996 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 997 998 /* Set enables for sections that are needed in the SSPM registers */ 999 BA0WRITE4(sc, CS4281_SSPM, 1000 SSPM_MIXEN | /* Mixer */ 1001 SSPM_CSRCEN | /* Capture SRC */ 1002 SSPM_PSRCEN | /* Playback SRC */ 1003 SSPM_JSEN | /* Joystick */ 1004 SSPM_ACLEN | /* AC LINK */ 1005 SSPM_FMEN /* FM */ 1006 ); 1007 1008 /* Wait for clock stabilization */ 1009 n = 0; 1010 #if 1 1011 /* what document says */ 1012 while ( ( BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1013 != (CLKCR1_DLLRDY | CLKCR1_CLKON )) { 1014 delay(100); 1015 if ( ++n > 1000 ) 1016 return -1; 1017 } 1018 #else 1019 /* Cirrus driver for Linux does */ 1020 while ( !(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1021 delay(1000); 1022 if ( ++n > 1000 ) 1023 return -1; 1024 } 1025 #endif 1026 1027 /* Enable ASYNC generation */ 1028 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1029 1030 /* Wait for Codec ready. Linux driver wait 50ms here */ 1031 n = 0; 1032 while((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1033 delay(100); 1034 if (++n > 1000) 1035 return -1; 1036 } 1037 1038 #if defined(ENABLE_SECONDARY_CODEC) 1039 /* secondary codec ready*/ 1040 n = 0; 1041 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1042 delay(100); 1043 if (++n > 1000) 1044 return -1; 1045 } 1046 #endif 1047 1048 /* Set the serial timing configuration */ 1049 /* XXX: undocumented but the Linux driver do this */ 1050 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1051 1052 /* Wait for Codec ready signal */ 1053 n = 0; 1054 do { 1055 delay(1000); 1056 if (++n > 1000) { 1057 printf("%s: Timeout waiting for Codec ready\n", 1058 sc->sc_dev.dv_xname); 1059 return -1; 1060 } 1061 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1062 } while (dat32 == 0); 1063 1064 /* Enable Valid Frame output on ASDOUT */ 1065 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1066 1067 /* Wait until Codec Calibration is finished. Codec register 26h */ 1068 n = 0; 1069 do { 1070 delay(1); 1071 if (++n > 1000) { 1072 printf("%s: Timeout waiting for Codec calibration\n", 1073 sc->sc_dev.dv_xname); 1074 return -1; 1075 } 1076 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1077 } while ((data & 0x0f) != 0x0f); 1078 1079 /* Set the serial timing configuration again */ 1080 /* XXX: undocumented but the Linux driver do this */ 1081 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1082 1083 /* Wait until we've sampled input slots 3 & 4 as valid */ 1084 n = 0; 1085 do { 1086 delay(1000); 1087 if (++n > 1000) { 1088 printf("%s: Timeout waiting for sampled input slots as valid\n", 1089 sc->sc_dev.dv_xname); 1090 return -1; 1091 } 1092 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1093 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1094 1095 /* Start digital data transfer of audio data to the codec */ 1096 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1097 1098 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1099 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1100 1101 /* Power on the DAC */ 1102 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1103 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1104 1105 /* Wait until we sample a DAC ready state. 1106 * Not documented, but Linux driver does. 1107 */ 1108 for (n = 0; n < 32; ++n) { 1109 delay(1000); 1110 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1111 if (data & 0x02) 1112 break; 1113 } 1114 1115 /* Power on the ADC */ 1116 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1117 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1118 1119 /* Wait until we sample ADC ready state. 1120 * Not documented, but Linux driver does. 1121 */ 1122 for (n = 0; n < 32; ++n) { 1123 delay(1000); 1124 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1125 if (data & 0x01) 1126 break; 1127 } 1128 1129 #if 0 1130 /* Initialize AC-Link features */ 1131 /* variable sample-rate support */ 1132 mem = BA0READ4(sc, CS4281_SERMC); 1133 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1134 BA0WRITE4(sc, CS4281_SERMC, mem); 1135 /* XXX: more... */ 1136 1137 /* Initialize SSCR register features */ 1138 /* XXX: hardware volume setting */ 1139 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1140 #endif 1141 1142 /* disable Sound Blaster Pro emulation */ 1143 /* XXX: 1144 * Cannot set since the documents does not describe which bit is 1145 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1146 * we can ignore it.*/ 1147 #if 0 1148 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1149 #endif 1150 1151 /* map AC97 PCM playback to DMA Channel 0 */ 1152 /* Reset FEN bit to setup first */ 1153 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc,CS4281_FCR0) & ~FCRn_FEN)); 1154 /* 1155 *| RS[4:0]/| | 1156 *| LS[4:0] | AC97 | Slot Function 1157 *|---------+--------+-------------------- 1158 *| 0 | 3 | Left PCM Playback 1159 *| 1 | 4 | Right PCM Playback 1160 *| 2 | 5 | Phone Line 1 DAC 1161 *| 3 | 6 | Center PCM Playback 1162 *.... 1163 * quoted from Table 29(p109) 1164 */ 1165 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1166 0x00 << 16 | /* LS[4:0] = 0 see above */ 1167 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1168 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1169 BA0WRITE4(sc, CS4281_FCR0, dat32); 1170 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1171 1172 /* map AC97 PCM record to DMA Channel 1 */ 1173 /* Reset FEN bit to setup first */ 1174 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc,CS4281_FCR1) & ~FCRn_FEN)); 1175 /* 1176 *| RS[4:0]/| 1177 *| LS[4:0] | AC97 | Slot Function 1178 *|---------+------+------------------- 1179 *| 10 | 3 | Left PCM Record 1180 *| 11 | 4 | Right PCM Record 1181 *| 12 | 5 | Phone Line 1 ADC 1182 *| 13 | 6 | Mic ADC 1183 *.... 1184 * quoted from Table 30(p109) 1185 */ 1186 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1187 0x0a << 16 | /* LS[4:0] = 10 See above */ 1188 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1189 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1190 1191 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1192 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1193 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1194 1195 #if 0 1196 /* Disable DMA Channel 2, 3 */ 1197 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc,CS4281_FCR2) & ~FCRn_FEN)); 1198 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc,CS4281_FCR3) & ~FCRn_FEN)); 1199 #endif 1200 1201 /* Set the SRC Slot Assignment accordingly */ 1202 /*| PLSS[4:0]/ 1203 *| PRSS[4:0] | AC97 | Slot Function 1204 *|-----------+------+---------------- 1205 *| 0 | 3 | Left PCM Playback 1206 *| 1 | 4 | Right PCM Playback 1207 *| 2 | 5 | phone line 1 DAC 1208 *| 3 | 6 | Center PCM Playback 1209 *| 4 | 7 | Left Surround PCM Playback 1210 *| 5 | 8 | Right Surround PCM Playback 1211 *...... 1212 * 1213 *| CLSS[4:0]/ 1214 *| CRSS[4:0] | AC97 | Codec |Slot Function 1215 *|-----------+------+-------+----------------- 1216 *| 10 | 3 |Primary| Left PCM Record 1217 *| 11 | 4 |Primary| Right PCM Record 1218 *| 12 | 5 |Primary| Phone Line 1 ADC 1219 *| 13 | 6 |Primary| Mic ADC 1220 *|..... 1221 *| 20 | 3 | Sec. | Left PCM Record 1222 *| 21 | 4 | Sec. | Right PCM Record 1223 *| 22 | 5 | Sec. | Phone Line 1 ADC 1224 *| 23 | 6 | Sec. | Mic ADC 1225 */ 1226 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1227 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1228 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1229 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1230 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1231 1232 /* Set interrupt to occurred at Half and Full terminal 1233 * count interrupt enable for DMA channel 0 and 1. 1234 * To keep DMA stop, set MSK. 1235 */ 1236 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1237 BA0WRITE4(sc, CS4281_DCR0, dat32); 1238 BA0WRITE4(sc, CS4281_DCR1, dat32); 1239 1240 /* Set Auto-Initialize Contorl enable */ 1241 BA0WRITE4(sc, CS4281_DMR0, 1242 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1243 BA0WRITE4(sc, CS4281_DMR1, 1244 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1245 1246 /* Clear DMA Mask in HIMR */ 1247 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1248 BA0WRITE4(sc, CS4281_HIMR, 1249 BA0READ4(sc, CS4281_HIMR) & dat32); 1250 1251 /* set current status */ 1252 if (init != 0) { 1253 sc->sc_prun = 0; 1254 sc->sc_rrun = 0; 1255 } 1256 1257 /* setup playback volume */ 1258 BA0WRITE4(sc, CS4281_PPRVC, 7); 1259 BA0WRITE4(sc, CS4281_PPLVC, 7); 1260 1261 return 0; 1262 } 1263
Indexes created Tue Sep 30 20:09:53 GMT 2025