cxdtv.c revision 1.17
1 /* $NetBSD: cxdtv.c,v 1.17 2019/12/22 23:23:32 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.17 2019/12/22 23:23:32 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/proc.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_bitbang.h> 46 47 #include <dev/i2c/tvpllvar.h> 48 #include <dev/i2c/tvpll_tuners.h> 49 50 #include <dev/i2c/nxt2kvar.h> 51 #include <dev/i2c/lg3303var.h> 52 53 #include <dev/dtv/dtvif.h> 54 55 #include <dev/pci/cxdtvreg.h> 56 #include <dev/pci/cxdtvvar.h> 57 #include <dev/pci/cxdtv_boards.h> 58 59 #define CXDTV_MMBASE 0x10 60 61 #define CXDTV_SRAM_CH_MPEG 0 62 #define CXDTV_TS_PKTSIZE (188 * 8) 63 64 static int cxdtv_match(device_t, cfdata_t, void *); 65 static void cxdtv_attach(device_t, device_t, void *); 66 static int cxdtv_detach(device_t, int); 67 static int cxdtv_rescan(device_t, const char *, const int *); 68 static void cxdtv_childdet(device_t, device_t); 69 static int cxdtv_intr(void *); 70 71 static bool cxdtv_resume(device_t, const pmf_qual_t *); 72 73 static int cxdtv_iic_send_start(void *, int); 74 static int cxdtv_iic_send_stop(void *, int); 75 static int cxdtv_iic_initiate_xfer(void *, i2c_addr_t, int); 76 static int cxdtv_iic_read_byte(void *, uint8_t *, int); 77 static int cxdtv_iic_write_byte(void *, uint8_t, int); 78 79 static void cxdtv_i2cbb_set_bits(void *, uint32_t); 80 static void cxdtv_i2cbb_set_dir(void *, uint32_t); 81 static uint32_t cxdtv_i2cbb_read_bits(void *); 82 83 static int cxdtv_sram_ch_setup(struct cxdtv_softc *, 84 struct cxdtv_sram_ch *, uint32_t); 85 static int cxdtv_allocmem(struct cxdtv_softc *, size_t, size_t, 86 struct cxdtv_dma *); 87 static int cxdtv_freemem(struct cxdtv_softc *, struct cxdtv_dma *); 88 static int cxdtv_risc_buffer(struct cxdtv_softc *, uint32_t, uint32_t); 89 static int cxdtv_risc_field(struct cxdtv_softc *, uint32_t *, uint32_t); 90 91 static int cxdtv_mpeg_attach(struct cxdtv_softc *); 92 static int cxdtv_mpeg_detach(struct cxdtv_softc *, int flags); 93 static int cxdtv_mpeg_intr(struct cxdtv_softc *); 94 static int cxdtv_mpeg_reset(struct cxdtv_softc *); 95 96 static int cxdtv_mpeg_trigger(struct cxdtv_softc *, void *); 97 static int cxdtv_mpeg_halt(struct cxdtv_softc *); 98 static void * cxdtv_mpeg_malloc(struct cxdtv_softc *, size_t); 99 static void cxdtv_mpeg_free(struct cxdtv_softc *, void *); 100 101 static void cxdtv_card_init_hd5500(struct cxdtv_softc *); 102 static void cxdtv_card_init_hdtvwonder(struct cxdtv_softc *); 103 104 /* MPEG TS Port */ 105 static void cxdtv_dtv_get_devinfo(void *, struct dvb_frontend_info *); 106 static int cxdtv_dtv_open(void *, int); 107 static void cxdtv_dtv_close(void *); 108 static int cxdtv_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 109 static fe_status_t cxdtv_dtv_get_status(void *); 110 static uint16_t cxdtv_dtv_get_signal_strength(void *); 111 static uint16_t cxdtv_dtv_get_snr(void *); 112 static int cxdtv_dtv_start_transfer(void *, 113 void (*)(void *, const struct dtv_payload *), void *); 114 static int cxdtv_dtv_stop_transfer(void *); 115 116 static const struct dtv_hw_if cxdtv_dtv_if = { 117 .get_devinfo = cxdtv_dtv_get_devinfo, 118 .open = cxdtv_dtv_open, 119 .close = cxdtv_dtv_close, 120 .set_tuner = cxdtv_dtv_set_tuner, 121 .get_status = cxdtv_dtv_get_status, 122 .get_signal_strength = cxdtv_dtv_get_signal_strength, 123 .get_snr = cxdtv_dtv_get_snr, 124 .start_transfer = cxdtv_dtv_start_transfer, 125 .stop_transfer = cxdtv_dtv_stop_transfer, 126 }; 127 128 const struct i2c_bitbang_ops cxdtv_i2cbb_ops = { 129 cxdtv_i2cbb_set_bits, 130 cxdtv_i2cbb_set_dir, 131 cxdtv_i2cbb_read_bits, 132 { CXDTV_I2C_C_DATACONTROL_SDA, CXDTV_I2C_C_DATACONTROL_SCL, 0, 0 } 133 }; 134 135 /* Maybe make this dynamically allocated. */ 136 static struct cxdtv_sram_ch cxdtv_sram_chs[] = { 137 [CXDTV_SRAM_CH_MPEG] = { 138 .csc_cmds = 0x180200, /* CMDS for ch. 28 */ 139 .csc_iq = 0x180340, /* after last CMDS */ 140 .csc_iqsz = 0x40, /* 16 dwords */ 141 .csc_cdt = 0x180380, /* after iq */ 142 .csc_cdtsz = 0x40, /* cluster discriptor space */ 143 .csc_fifo = 0x180400, /* after cdt */ 144 .csc_fifosz = 0x001C00, /* let's just align this up */ 145 .csc_risc = 0x182000, /* after fifo */ 146 .csc_riscsz = 0x6000, /* room for dma programs */ 147 .csc_ptr1 = CXDTV_DMA28_PTR1, 148 .csc_ptr2 = CXDTV_DMA28_PTR2, 149 .csc_cnt1 = CXDTV_DMA28_CNT1, 150 .csc_cnt2 = CXDTV_DMA28_CNT2, 151 }, 152 }; 153 154 CFATTACH_DECL2_NEW(cxdtv, sizeof(struct cxdtv_softc), 155 cxdtv_match, cxdtv_attach, cxdtv_detach, NULL, 156 cxdtv_rescan, cxdtv_childdet); 157 158 static int 159 cxdtv_match(device_t parent, cfdata_t match, void *aux) 160 { 161 const struct pci_attach_args *pa; 162 pcireg_t reg; 163 164 pa = aux; 165 166 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 167 return 0; 168 169 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX2388XMPEG) 170 return 0; 171 172 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 173 if (cxdtv_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)) == NULL) 174 return 0; 175 176 return 1; 177 } 178 179 static void 180 cxdtv_attach(device_t parent, device_t self, void *aux) 181 { 182 struct cxdtv_softc *sc; 183 const struct pci_attach_args *pa = aux; 184 pci_intr_handle_t ih; 185 pcireg_t reg; 186 const char *intrstr; 187 struct i2cbus_attach_args iba; 188 char intrbuf[PCI_INTRSTR_LEN]; 189 190 sc = device_private(self); 191 192 sc->sc_dev = self; 193 sc->sc_pc = pa->pa_pc; 194 195 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 196 197 sc->sc_vendor = PCI_VENDOR(reg); 198 sc->sc_product = PCI_PRODUCT(reg); 199 200 sc->sc_board = cxdtv_board_lookup(sc->sc_vendor, sc->sc_product); 201 KASSERT(sc->sc_board != NULL); 202 203 pci_aprint_devinfo(pa, NULL); 204 205 if (pci_mapreg_map(pa, CXDTV_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 206 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 207 aprint_error_dev(self, "couldn't map memory space\n"); 208 return; 209 } 210 211 sc->sc_dmat = pa->pa_dmat; 212 213 if (pci_intr_map(pa, &ih)) { 214 aprint_error_dev(self, "couldn't map interrupt\n"); 215 return; 216 } 217 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 218 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_VM, cxdtv_intr, 219 sc, device_xname(self)); 220 if (sc->sc_ih == NULL) { 221 aprint_error_dev(self, "couldn't establish interrupt"); 222 if (intrstr != NULL) 223 aprint_error(" at %s", intrstr); 224 aprint_error("\n"); 225 return; 226 } 227 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 228 229 /* set master */ 230 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 231 reg |= PCI_COMMAND_MASTER_ENABLE; 232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 233 234 iic_tag_init(&sc->sc_i2c); 235 sc->sc_i2c.ic_cookie = sc; 236 sc->sc_i2c.ic_send_start = cxdtv_iic_send_start; 237 sc->sc_i2c.ic_send_stop = cxdtv_iic_send_stop; 238 sc->sc_i2c.ic_initiate_xfer = cxdtv_iic_initiate_xfer; 239 sc->sc_i2c.ic_read_byte = cxdtv_iic_read_byte; 240 sc->sc_i2c.ic_write_byte = cxdtv_iic_write_byte; 241 242 #if notyet 243 /* enable i2c compatible software mode */ 244 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, 245 CXDTV_I2C_C_DATACONTROL); 246 val = CXDTV_I2C_C_DATACONTROL_SCL | CXDTV_I2C_C_DATACONTROL_SDA; 247 bus_space_write_4(sc->sc_memt, sc->sc_memh, 248 CXDTV_I2C_C_DATACONTROL, val); 249 #endif 250 251 cxdtv_mpeg_attach(sc); 252 253 /* attach other devices to iic(4) */ 254 memset(&iba, 0, sizeof(iba)); 255 iba.iba_tag = &sc->sc_i2c; 256 config_found_ia(self, "i2cbus", &iba, iicbus_print); 257 258 if (!pmf_device_register(self, NULL, cxdtv_resume)) 259 aprint_error_dev(self, "couldn't establish power handler\n"); 260 261 return; 262 } 263 264 static int 265 cxdtv_detach(device_t self, int flags) 266 { 267 struct cxdtv_softc *sc = device_private(self); 268 int error; 269 270 error = cxdtv_mpeg_detach(sc, flags); 271 if (error) 272 return error; 273 274 if (sc->sc_ih) 275 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 276 277 if (sc->sc_mems) 278 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 279 280 iic_tag_fini(&sc->sc_i2c); 281 282 return 0; 283 } 284 285 static int 286 cxdtv_rescan(device_t self, const char *ifattr, const int *locs) 287 { 288 struct cxdtv_softc *sc = device_private(self); 289 struct dtv_attach_args daa; 290 291 daa.hw = &cxdtv_dtv_if; 292 daa.priv = sc; 293 294 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 295 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", 296 &daa, dtv_print); 297 298 return 0; 299 } 300 301 static void 302 cxdtv_childdet(device_t self, device_t child) 303 { 304 struct cxdtv_softc *sc = device_private(self); 305 306 if (child == sc->sc_dtvdev) 307 sc->sc_dtvdev = NULL; 308 } 309 310 static bool 311 cxdtv_resume(device_t dv, const pmf_qual_t *qual) 312 { 313 /* XXX revisit */ 314 315 aprint_debug_dev(dv, "%s\n", __func__); 316 317 return true; 318 } 319 320 static int 321 cxdtv_intr(void *intarg) 322 { 323 struct cxdtv_softc *sc = intarg; 324 uint32_t val; 325 326 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MSTAT); 327 if (val == 0) { 328 return 0; /* not ours */ 329 } 330 331 if (val & CXT_PI_TS_INT) { 332 cxdtv_mpeg_intr(sc); 333 } 334 335 if (val & ~CXT_PI_TS_INT) { 336 device_printf(sc->sc_dev, "%s, %08x\n", __func__, val); 337 } 338 339 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, val); 340 341 return 1; 342 } 343 344 /* I2C interface */ 345 346 static void 347 cxdtv_i2cbb_set_bits(void *cookie, uint32_t bits) 348 { 349 struct cxdtv_softc *sc = cookie; 350 351 bus_space_write_4(sc->sc_memt, sc->sc_memh, 352 CXDTV_I2C_C_DATACONTROL, bits); 353 (void)bus_space_read_4(sc->sc_memt, sc->sc_memh, 354 CXDTV_I2C_C_DATACONTROL); 355 356 return; 357 } 358 359 static void 360 cxdtv_i2cbb_set_dir(void *cookie, uint32_t bits) 361 { 362 return; 363 } 364 365 static uint32_t 366 cxdtv_i2cbb_read_bits(void *cookie) 367 { 368 struct cxdtv_softc *sc = cookie; 369 uint32_t value; 370 371 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 372 CXDTV_I2C_C_DATACONTROL); 373 374 return value; 375 } 376 377 static int 378 cxdtv_iic_send_start(void *cookie, int flags) 379 { 380 return i2c_bitbang_send_start(cookie, flags, &cxdtv_i2cbb_ops); 381 } 382 383 static int 384 cxdtv_iic_send_stop(void *cookie, int flags) 385 { 386 return i2c_bitbang_send_stop(cookie, flags, &cxdtv_i2cbb_ops); 387 } 388 389 static int 390 cxdtv_iic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 391 { 392 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &cxdtv_i2cbb_ops); 393 } 394 395 static int 396 cxdtv_iic_read_byte(void *cookie, uint8_t *data, int flags) 397 { 398 return i2c_bitbang_read_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 399 } 400 401 static int 402 cxdtv_iic_write_byte(void *cookie, uint8_t data, int flags) 403 { 404 return i2c_bitbang_write_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 405 } 406 407 int 408 cxdtv_mpeg_attach(struct cxdtv_softc *sc) 409 { 410 struct cxdtv_sram_ch *ch; 411 412 CX_DPRINTF(("cxdtv_mpeg_attach\n")); 413 414 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 415 416 sc->sc_riscbufsz = ch->csc_riscsz; 417 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 418 419 aprint_debug_dev(sc->sc_dev, "attaching frontend...\n"); 420 421 switch(sc->sc_vendor) { 422 case PCI_VENDOR_ATI: 423 cxdtv_card_init_hdtvwonder(sc); 424 break; 425 case PCI_VENDOR_PCHDTV: 426 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 427 cxdtv_card_init_hd5500(sc); 428 } 429 break; 430 } 431 432 KASSERT(sc->sc_tuner == NULL); 433 KASSERT(sc->sc_demod == NULL); 434 435 switch(sc->sc_board->cb_demod) { 436 case CXDTV_DEMOD_NXT2004: 437 sc->sc_demod = nxt2k_open(sc->sc_dev, &sc->sc_i2c, 0x0a, 0); 438 break; 439 case CXDTV_DEMOD_LG3303: 440 sc->sc_demod = lg3303_open(sc->sc_dev, &sc->sc_i2c, 0x59, 441 LG3303_CFG_SERIAL_INPUT); 442 break; 443 default: 444 break; 445 } 446 447 switch(sc->sc_board->cb_tuner) { 448 case CXDTV_TUNER_PLL: 449 if (sc->sc_vendor == PCI_VENDOR_ATI) 450 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tuv1236d_pll); 451 if (sc->sc_vendor == PCI_VENDOR_PCHDTV) 452 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tdvs_h06xf_pll); 453 break; 454 default: 455 break; 456 } 457 458 KASSERT(sc->sc_tuner != NULL); 459 KASSERT(sc->sc_demod != NULL); 460 461 cxdtv_rescan(sc->sc_dev, NULL, NULL); 462 463 return (sc->sc_dtvdev != NULL); 464 } 465 466 int 467 cxdtv_mpeg_detach(struct cxdtv_softc *sc, int flags) 468 { 469 int error = 0; 470 471 if (sc->sc_dtvdev) { 472 error = config_detach(sc->sc_dtvdev, flags); 473 if (error) 474 return error; 475 } 476 477 if (sc->sc_demod) { 478 switch (sc->sc_board->cb_demod) { 479 case CXDTV_DEMOD_NXT2004: 480 nxt2k_close(sc->sc_demod); 481 break; 482 case CXDTV_DEMOD_LG3303: 483 lg3303_close(sc->sc_demod); 484 break; 485 default: 486 break; 487 } 488 sc->sc_demod = NULL; 489 } 490 if (sc->sc_tuner) { 491 switch (sc->sc_board->cb_tuner) { 492 case CXDTV_TUNER_PLL: 493 tvpll_close(sc->sc_tuner); 494 break; 495 default: 496 break; 497 } 498 sc->sc_tuner = NULL; 499 } 500 501 if (sc->sc_riscbuf) { 502 kmem_free(sc->sc_riscbuf, sc->sc_riscbufsz); 503 sc->sc_riscbuf = NULL; 504 sc->sc_riscbufsz = 0; 505 } 506 507 return error; 508 } 509 510 static void 511 cxdtv_dtv_get_devinfo(void *priv, struct dvb_frontend_info *info) 512 { 513 memset(info, 0, sizeof(*info)); 514 strlcpy(info->name, "CX23880", sizeof(info->name)); 515 info->type = FE_ATSC; 516 info->frequency_min = 54000000; 517 info->frequency_max = 858000000; 518 info->frequency_stepsize = 62500; 519 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 520 } 521 522 static int 523 cxdtv_dtv_open(void *priv, int flags) 524 { 525 struct cxdtv_softc *sc = priv; 526 527 KASSERT(sc->sc_tsbuf == NULL); 528 529 cxdtv_mpeg_reset(sc); 530 531 /* allocate two alternating DMA areas for MPEG TS packets */ 532 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 533 534 if (sc->sc_tsbuf == NULL) 535 return ENOMEM; 536 537 return 0; 538 } 539 540 static void 541 cxdtv_dtv_close(void *priv) 542 { 543 struct cxdtv_softc *sc = priv; 544 545 cxdtv_dtv_stop_transfer(sc); 546 547 if (sc->sc_tsbuf != NULL) { 548 cxdtv_mpeg_free(sc, sc->sc_tsbuf); 549 sc->sc_tsbuf = NULL; 550 } 551 } 552 553 static int 554 cxdtv_dtv_set_tuner(void *priv, const struct dvb_frontend_parameters *params) 555 { 556 struct cxdtv_softc *sc = priv; 557 int error = -1; 558 559 switch(sc->sc_board->cb_tuner) { 560 case CXDTV_TUNER_PLL: 561 error = tvpll_tune_dtv(sc->sc_tuner, params); 562 } 563 if (error) 564 goto bad; 565 566 switch(sc->sc_board->cb_demod) { 567 case CXDTV_DEMOD_NXT2004: 568 error = nxt2k_set_modulation(sc->sc_demod, params->u.vsb.modulation); 569 break; 570 case CXDTV_DEMOD_LG3303: 571 error = lg3303_set_modulation(sc->sc_demod, params->u.vsb.modulation); 572 break; 573 default: 574 break; 575 } 576 577 bad: 578 return error; 579 } 580 581 static fe_status_t 582 cxdtv_dtv_get_status(void *priv) 583 { 584 struct cxdtv_softc *sc = priv; 585 586 switch(sc->sc_board->cb_demod) { 587 case CXDTV_DEMOD_NXT2004: 588 return nxt2k_get_dtv_status(sc->sc_demod); 589 case CXDTV_DEMOD_LG3303: 590 return lg3303_get_dtv_status(sc->sc_demod); 591 default: 592 return 0; 593 } 594 } 595 596 static uint16_t 597 cxdtv_dtv_get_signal_strength(void *priv) 598 { 599 struct cxdtv_softc *sc = priv; 600 601 switch(sc->sc_board->cb_demod) { 602 case CXDTV_DEMOD_NXT2004: 603 return 0; /* TODO */ 604 case CXDTV_DEMOD_LG3303: 605 return lg3303_get_signal_strength(sc->sc_demod); 606 } 607 608 return 0; 609 } 610 611 static uint16_t 612 cxdtv_dtv_get_snr(void *priv) 613 { 614 struct cxdtv_softc *sc = priv; 615 616 switch(sc->sc_board->cb_demod) { 617 case CXDTV_DEMOD_NXT2004: 618 return 0; /* TODO */ 619 case CXDTV_DEMOD_LG3303: 620 return lg3303_get_snr(sc->sc_demod); 621 } 622 623 return 0; 624 } 625 626 static int 627 cxdtv_dtv_start_transfer(void *priv, 628 void (*cb)(void *, const struct dtv_payload *), void *arg) 629 { 630 struct cxdtv_softc *sc = priv; 631 632 sc->sc_dtvsubmitcb = cb; 633 sc->sc_dtvsubmitarg = arg; 634 635 /* allocate two alternating DMA areas for MPEG TS packets */ 636 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 637 638 cxdtv_mpeg_trigger(sc, sc->sc_tsbuf); 639 640 return 0; 641 } 642 643 static int 644 cxdtv_dtv_stop_transfer(void *priv) 645 { 646 struct cxdtv_softc *sc = priv; 647 648 cxdtv_mpeg_halt(sc); 649 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 650 651 sc->sc_dtvsubmitcb = NULL; 652 sc->sc_dtvsubmitarg = NULL; 653 654 return 0; 655 } 656 657 int 658 cxdtv_mpeg_reset(struct cxdtv_softc *sc) 659 { 660 uint32_t v; 661 662 CX_DPRINTF(("cxdtv_mpeg_reset\n")); 663 664 v = (uint32_t)-1; 665 666 /* shutdown */ 667 /* hold RISC in reset */ 668 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 0); 669 /* disable FIFO and RISC */ 670 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 0); 671 /* mask off all interrupts */ 672 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 673 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 0); 674 675 /* clear interrupts */ 676 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, v); 677 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, v); 678 679 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 680 681 /* XXX magic */ 682 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_STHRSH, 0x0707); 683 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_DTHRSH, 0x0707); 684 685 /* reset external components*/ 686 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 0); 687 kpause("cxdtvrst", false, MAX(1, mstohz(1)), NULL); 688 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 1); 689 690 /* let error interrupts happen */ 691 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 692 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 693 v | 0x00fc00); /* XXX magic */ 694 695 return 0; 696 } 697 698 static int 699 cxdtv_risc_buffer(struct cxdtv_softc *sc, uint32_t bpl, uint32_t lines) 700 { 701 uint32_t *rm; 702 uint32_t size; 703 704 CX_DPRINTF(("cxdtv_risc_buffer: bpl=0x%x\n", bpl)); 705 706 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 707 size += 2; 708 709 device_printf(sc->sc_dev, "%s: est. inst. %d\n", __func__, size); 710 711 size *= 8; 712 device_printf(sc->sc_dev, "%s: est. qword %d\n", __func__, size); 713 714 if (sc->sc_riscbuf == NULL) { 715 device_printf(sc->sc_dev, "not enough memory for RISC\n"); 716 return ENOMEM; 717 } 718 719 rm = (uint32_t *)sc->sc_riscbuf; 720 cxdtv_risc_field(sc, rm, bpl); 721 722 return 0; 723 } 724 725 static int 726 cxdtv_risc_field(struct cxdtv_softc *sc, uint32_t *rm, uint32_t bpl) 727 { 728 struct cxdtv_dma *p; 729 730 CX_DPRINTF(("cxdtv_risc_field: bpl=0x%x\n", bpl)); 731 732 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 733 continue; 734 if (p == NULL) { 735 device_printf(sc->sc_dev, "cxdtv_risc_field: bad addr %p\n", 736 sc->sc_tsbuf); 737 return ENOENT; 738 } 739 740 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 741 742 rm = sc->sc_riscbuf; 743 744 /* htole32 will be done when program is copied to chip SRAM */ 745 746 /* XXX */ 747 *(rm++) = (CX_RISC_SYNC|0); 748 749 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 750 *(rm++) = (DMAADDR(p) + 0 * bpl); 751 752 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 753 *(rm++) = (DMAADDR(p) + 1 * bpl); 754 755 *(rm++) = (CX_RISC_JUMP|1); 756 *(rm++) = (cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG].csc_risc + 4); 757 758 return 0; 759 } 760 761 static int 762 cxdtv_sram_ch_setup(struct cxdtv_softc *sc, struct cxdtv_sram_ch *csc, 763 uint32_t bpl) 764 { 765 unsigned int i, lines; 766 uint32_t cdt; 767 768 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 769 770 /* XXX why round? */ 771 bpl = (bpl + 7) & ~7; 772 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 773 cdt = csc->csc_cdt; 774 lines = csc->csc_fifosz / bpl; 775 device_printf(sc->sc_dev, "%s %d lines\n", __func__, lines); 776 777 /* fill in CDT */ 778 for (i = 0; i < lines; i++) { 779 CX_DPRINTF(("CDT ent %08x, %08x\n", cdt + (16 * i), 780 csc->csc_fifo + (bpl * i))); 781 bus_space_write_4(sc->sc_memt, sc->sc_memh, 782 cdt + (16 * i), 783 csc->csc_fifo + (bpl * i)); 784 } 785 786 /* copy DMA program */ 787 788 /* converts program to little endian as it goes into SRAM */ 789 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 790 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 791 792 /* fill in CMDS */ 793 bus_space_write_4(sc->sc_memt, sc->sc_memh, 794 csc->csc_cmds + CX_CMDS_O_IRPC, csc->csc_risc); 795 796 bus_space_write_4(sc->sc_memt, sc->sc_memh, 797 csc->csc_cmds + CX_CMDS_O_CDTB, csc->csc_cdt); 798 bus_space_write_4(sc->sc_memt, sc->sc_memh, 799 csc->csc_cmds + CX_CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 800 801 bus_space_write_4(sc->sc_memt, sc->sc_memh, 802 csc->csc_cmds + CX_CMDS_O_IQB, csc->csc_iq); 803 bus_space_write_4(sc->sc_memt, sc->sc_memh, 804 csc->csc_cmds + CX_CMDS_O_IQS, 805 CX_CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 806 807 /* zero rest of CMDS */ 808 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x14, 0, 0x2c/4); 809 810 bus_space_write_4(sc->sc_memt, sc->sc_memh, 811 csc->csc_cnt1, (bpl >> 3) - 1); 812 813 bus_space_write_4(sc->sc_memt, sc->sc_memh, 814 csc->csc_ptr2, cdt); 815 bus_space_write_4(sc->sc_memt, sc->sc_memh, 816 csc->csc_cnt2, (lines * 16) >> 3); 817 818 return 0; 819 } 820 821 int 822 cxdtv_mpeg_trigger(struct cxdtv_softc *sc, void *buf) 823 { 824 struct cxdtv_dma *p; 825 struct cxdtv_sram_ch *ch; 826 uint32_t v; 827 828 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 829 830 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 831 continue; 832 if (p == NULL) { 833 device_printf(sc->sc_dev, "cxdtv_mpeg_trigger: bad addr %p\n", 834 buf); 835 return ENOENT; 836 } 837 838 CX_DPRINTF(("cxdtv_mpeg_trigger: buf=%p\n", buf)); 839 840 cxdtv_risc_buffer(sc, CXDTV_TS_PKTSIZE, 1); 841 cxdtv_sram_ch_setup(sc, ch, CXDTV_TS_PKTSIZE); 842 843 /* software reset */ 844 845 switch(sc->sc_vendor) { 846 case PCI_VENDOR_ATI: 847 /* both ATI boards with DTV are the same */ 848 bus_space_write_4(sc->sc_memt, sc->sc_memh, 849 CXDTV_TS_GEN_CONTROL, IPB_SW_RST); 850 delay(100); 851 /* parallel MPEG port */ 852 bus_space_write_4(sc->sc_memt, sc->sc_memh, 853 CXDTV_PINMUX_IO, MPEG_PAR_EN); 854 break; 855 case PCI_VENDOR_PCHDTV: 856 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 857 bus_space_write_4(sc->sc_memt, sc->sc_memh, 858 CXDTV_TS_GEN_CONTROL, IPB_SW_RST|IPB_SMODE); 859 delay(100); 860 bus_space_write_4(sc->sc_memt, sc->sc_memh, 861 CXDTV_PINMUX_IO, 0x00); /* serial MPEG port */ 862 /* byte-width start-of-packet */ 863 bus_space_write_4(sc->sc_memt, sc->sc_memh, 864 CXDTV_HW_SOP_CONTROL, 865 0x47 << 16 | 188 << 4 | 1); 866 bus_space_write_4(sc->sc_memt, sc->sc_memh, 867 CXDTV_TS_SOP_STATUS, IPB_SOP_BYTEWIDE); 868 /* serial MPEG port on HD5500 */ 869 bus_space_write_4(sc->sc_memt, sc->sc_memh, 870 CXDTV_TS_GEN_CONTROL, IPB_SMODE); 871 } 872 break; 873 default: 874 break; 875 } 876 877 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_LNGTH, 878 CXDTV_TS_PKTSIZE); 879 880 /* Configure for standard MPEG TS, 1 good packet to sync */ 881 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_HW_SOP_CONTROL, 882 0x47 << 16 | 188 << 4 | 1); 883 884 /* zero counter */ 885 bus_space_write_4(sc->sc_memt, sc->sc_memh, 886 CXDTV_TS_GP_CNT_CNTRL, 0x03); 887 888 /* enable bad packet interrupt */ 889 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_BD_PKT_STATUS, 890 0x1000); 891 892 /* enable overflow counter */ 893 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_FIFO_OVFL_STAT, 894 0x1000); 895 896 /* unmask TS interrupt */ 897 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 898 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 899 v | CXT_PI_TS_INT); 900 901 /* unmask all TS interrupts */ 902 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 903 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 904 v | 0x1f1011); 905 906 /* enable RISC DMA engine */ 907 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2); 908 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 909 v | CXDTV_DEV_CNTRL2_RUN_RISC); 910 911 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 912 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 913 v | CXDTV_TS_RISC_EN | CXDTV_TS_FIFO_EN); 914 915 return 0; 916 } 917 918 int 919 cxdtv_mpeg_halt(struct cxdtv_softc *sc) 920 { 921 uint32_t v; 922 923 CX_DPRINTF(("cxdtv_mpeg_halt\n")); 924 925 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 926 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 927 v & ~(CXDTV_TS_RISC_EN|CXDTV_TS_FIFO_EN)); 928 929 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 930 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 931 v & ~CXT_PI_TS_INT); 932 933 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 934 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 935 v & ~0x1f1011); 936 937 return 0; 938 } 939 940 int 941 cxdtv_mpeg_intr(struct cxdtv_softc *sc) 942 { 943 struct dtv_payload payload; 944 uint32_t s, m; 945 946 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT); 947 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 948 if ((s & m) == 0) 949 return 0; 950 951 if ( (s & ~CXDTV_TS_RISCI) != 0 ) 952 device_printf(sc->sc_dev, "unexpected TS IS %08x\n", s); 953 954 if (sc->sc_dtvsubmitcb == NULL) 955 goto done; 956 957 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 958 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 959 0, CXDTV_TS_PKTSIZE, 960 BUS_DMASYNC_POSTREAD); 961 payload.data = KERNADDR(sc->sc_dma); 962 payload.size = CXDTV_TS_PKTSIZE; 963 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 964 } 965 966 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 967 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 968 CXDTV_TS_PKTSIZE, CXDTV_TS_PKTSIZE, 969 BUS_DMASYNC_POSTREAD); 970 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CXDTV_TS_PKTSIZE; 971 payload.size = CXDTV_TS_PKTSIZE; 972 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 973 } 974 975 done: 976 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, s); 977 978 return 1; 979 } 980 981 static int 982 cxdtv_allocmem(struct cxdtv_softc *sc, size_t size, size_t align, 983 struct cxdtv_dma *p) 984 { 985 int err; 986 987 p->size = size; 988 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 989 p->segs, __arraycount(p->segs), 990 &p->nsegs, BUS_DMA_NOWAIT); 991 if (err) 992 return err; 993 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 994 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 995 if (err) 996 goto free; 997 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 998 BUS_DMA_NOWAIT, &p->map); 999 if (err) 1000 goto unmap; 1001 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 1002 BUS_DMA_NOWAIT); 1003 if (err) 1004 goto destroy; 1005 1006 return 0; 1007 1008 destroy: 1009 bus_dmamap_destroy(sc->sc_dmat, p->map); 1010 unmap: 1011 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1012 free: 1013 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1014 1015 return err; 1016 } 1017 1018 static int 1019 cxdtv_freemem(struct cxdtv_softc *sc, struct cxdtv_dma *p) 1020 { 1021 1022 bus_dmamap_unload(sc->sc_dmat, p->map); 1023 bus_dmamap_destroy(sc->sc_dmat, p->map); 1024 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1025 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1026 1027 return 0; 1028 } 1029 1030 void * 1031 cxdtv_mpeg_malloc(struct cxdtv_softc *sc, size_t size) 1032 { 1033 struct cxdtv_dma *p; 1034 int err; 1035 1036 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1037 err = cxdtv_allocmem(sc, size, 16, p); 1038 if (err) { 1039 kmem_free(p, sizeof(*p)); 1040 device_printf(sc->sc_dev, "not enough memory\n"); 1041 return NULL; 1042 } 1043 1044 p->next = sc->sc_dma; 1045 sc->sc_dma = p; 1046 1047 return KERNADDR(p); 1048 } 1049 1050 static void 1051 cxdtv_mpeg_free(struct cxdtv_softc *sc, void *addr) 1052 { 1053 struct cxdtv_dma *p; 1054 struct cxdtv_dma **pp; 1055 1056 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) { 1057 if (KERNADDR(p) == addr) { 1058 cxdtv_freemem(sc, p); 1059 *pp = p->next; 1060 kmem_free(p, sizeof(*p)); 1061 return; 1062 } 1063 } 1064 1065 device_printf(sc->sc_dev, "%p is already free\n", addr); 1066 1067 return; 1068 } 1069 1070 1071 /* ATI HDTV Wonder */ 1072 static void 1073 cxdtv_card_init_hdtvwonder(struct cxdtv_softc *sc) 1074 { 1075 int i, x; 1076 i2c_addr_t na; 1077 uint8_t nb[5][2] = { 1078 {0x10, 0x12}, {0x13, 0x04}, {0x16, 0x00}, 1079 {0x14, 0x04}, {0x17, 0x00} 1080 }; 1081 1082 /* prepare TUV1236D/TU1236F NIM */ 1083 1084 na = 0x0a; /* Nxt2004 address */ 1085 x = 0; 1086 1087 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 1088 1089 for(i = 0; i < 5; i++) 1090 x |= iic_exec(&sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, na, 1091 nb[i], 2, NULL, 0, I2C_F_POLL); 1092 1093 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 1094 1095 if (x) 1096 aprint_error_dev(sc->sc_dev, "HDTV Wonder tuner init failed"); 1097 } 1098 1099 /* pcHDTV HD5500 */ 1100 #define cxdtv_write_field(_mask, _shift, _value) \ 1101 (((_value) & (_mask)) << (_shift)) 1102 1103 static void 1104 cxdtv_write_gpio(struct cxdtv_softc *sc, uint32_t mask, uint32_t value) 1105 { 1106 uint32_t v = 0; 1107 v |= cxdtv_write_field(0xff, 16, mask); 1108 v |= cxdtv_write_field(0xff, 8, mask); 1109 v |= cxdtv_write_field(0xff, 0, (mask & value)); 1110 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_GP0_IO, v); 1111 } 1112 1113 static void 1114 cxdtv_card_init_hd5500(struct cxdtv_softc *sc) 1115 { 1116 /* hardware (demod) reset */ 1117 cxdtv_write_gpio(sc, 1, 0); 1118 delay(100000); 1119 cxdtv_write_gpio(sc, 1, 1); 1120 delay(200000); 1121 } 1122 1123 MODULE(MODULE_CLASS_DRIVER, cxdtv, "tvpll,nxt2k,lg3303,pci"); 1124 1125 #ifdef _MODULE 1126 #include "ioconf.c" 1127 #endif 1128 1129 static int 1130 cxdtv_modcmd(modcmd_t cmd, void *opaque) 1131 { 1132 switch (cmd) { 1133 case MODULE_CMD_INIT: 1134 #ifdef _MODULE 1135 return config_init_component(cfdriver_ioconf_cxdtv, 1136 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1137 #else 1138 return 0; 1139 #endif 1140 case MODULE_CMD_FINI: 1141 #ifdef _MODULE 1142 return config_fini_component(cfdriver_ioconf_cxdtv, 1143 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1144 #else 1145 return 0; 1146 #endif 1147 default: 1148 return ENOTTY; 1149 } 1150 } 1151
Indexes created Fri Oct 03 02:09:57 GMT 2025