cxdtv.c revision 1.19
1 /* $NetBSD: cxdtv.c,v 1.19 2021/04/24 23:36:57 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.19 2021/04/24 23:36:57 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/proc.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_bitbang.h> 46 47 #include <dev/i2c/tvpllvar.h> 48 #include <dev/i2c/tvpll_tuners.h> 49 50 #include <dev/i2c/nxt2kvar.h> 51 #include <dev/i2c/lg3303var.h> 52 53 #include <dev/dtv/dtvif.h> 54 55 #include <dev/pci/cxdtvreg.h> 56 #include <dev/pci/cxdtvvar.h> 57 #include <dev/pci/cxdtv_boards.h> 58 59 #define CXDTV_MMBASE 0x10 60 61 #define CXDTV_SRAM_CH_MPEG 0 62 #define CXDTV_TS_PKTSIZE (188 * 8) 63 64 static int cxdtv_match(device_t, cfdata_t, void *); 65 static void cxdtv_attach(device_t, device_t, void *); 66 static int cxdtv_detach(device_t, int); 67 static int cxdtv_rescan(device_t, const char *, const int *); 68 static void cxdtv_childdet(device_t, device_t); 69 static int cxdtv_intr(void *); 70 71 static bool cxdtv_resume(device_t, const pmf_qual_t *); 72 73 static int cxdtv_iic_send_start(void *, int); 74 static int cxdtv_iic_send_stop(void *, int); 75 static int cxdtv_iic_initiate_xfer(void *, i2c_addr_t, int); 76 static int cxdtv_iic_read_byte(void *, uint8_t *, int); 77 static int cxdtv_iic_write_byte(void *, uint8_t, int); 78 79 static void cxdtv_i2cbb_set_bits(void *, uint32_t); 80 static void cxdtv_i2cbb_set_dir(void *, uint32_t); 81 static uint32_t cxdtv_i2cbb_read_bits(void *); 82 83 static int cxdtv_sram_ch_setup(struct cxdtv_softc *, 84 struct cxdtv_sram_ch *, uint32_t); 85 static int cxdtv_allocmem(struct cxdtv_softc *, size_t, size_t, 86 struct cxdtv_dma *); 87 static int cxdtv_freemem(struct cxdtv_softc *, struct cxdtv_dma *); 88 static int cxdtv_risc_buffer(struct cxdtv_softc *, uint32_t, uint32_t); 89 static int cxdtv_risc_field(struct cxdtv_softc *, uint32_t *, uint32_t); 90 91 static int cxdtv_mpeg_attach(struct cxdtv_softc *); 92 static int cxdtv_mpeg_detach(struct cxdtv_softc *, int flags); 93 static int cxdtv_mpeg_intr(struct cxdtv_softc *); 94 static int cxdtv_mpeg_reset(struct cxdtv_softc *); 95 96 static int cxdtv_mpeg_trigger(struct cxdtv_softc *, void *); 97 static int cxdtv_mpeg_halt(struct cxdtv_softc *); 98 static void * cxdtv_mpeg_malloc(struct cxdtv_softc *, size_t); 99 static void cxdtv_mpeg_free(struct cxdtv_softc *, void *); 100 101 static void cxdtv_card_init_hd5500(struct cxdtv_softc *); 102 static void cxdtv_card_init_hdtvwonder(struct cxdtv_softc *); 103 104 /* MPEG TS Port */ 105 static void cxdtv_dtv_get_devinfo(void *, struct dvb_frontend_info *); 106 static int cxdtv_dtv_open(void *, int); 107 static void cxdtv_dtv_close(void *); 108 static int cxdtv_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 109 static fe_status_t cxdtv_dtv_get_status(void *); 110 static uint16_t cxdtv_dtv_get_signal_strength(void *); 111 static uint16_t cxdtv_dtv_get_snr(void *); 112 static int cxdtv_dtv_start_transfer(void *, 113 void (*)(void *, const struct dtv_payload *), void *); 114 static int cxdtv_dtv_stop_transfer(void *); 115 116 static const struct dtv_hw_if cxdtv_dtv_if = { 117 .get_devinfo = cxdtv_dtv_get_devinfo, 118 .open = cxdtv_dtv_open, 119 .close = cxdtv_dtv_close, 120 .set_tuner = cxdtv_dtv_set_tuner, 121 .get_status = cxdtv_dtv_get_status, 122 .get_signal_strength = cxdtv_dtv_get_signal_strength, 123 .get_snr = cxdtv_dtv_get_snr, 124 .start_transfer = cxdtv_dtv_start_transfer, 125 .stop_transfer = cxdtv_dtv_stop_transfer, 126 }; 127 128 const struct i2c_bitbang_ops cxdtv_i2cbb_ops = { 129 cxdtv_i2cbb_set_bits, 130 cxdtv_i2cbb_set_dir, 131 cxdtv_i2cbb_read_bits, 132 { CXDTV_I2C_C_DATACONTROL_SDA, CXDTV_I2C_C_DATACONTROL_SCL, 0, 0 } 133 }; 134 135 /* Maybe make this dynamically allocated. */ 136 static struct cxdtv_sram_ch cxdtv_sram_chs[] = { 137 [CXDTV_SRAM_CH_MPEG] = { 138 .csc_cmds = 0x180200, /* CMDS for ch. 28 */ 139 .csc_iq = 0x180340, /* after last CMDS */ 140 .csc_iqsz = 0x40, /* 16 dwords */ 141 .csc_cdt = 0x180380, /* after iq */ 142 .csc_cdtsz = 0x40, /* cluster discriptor space */ 143 .csc_fifo = 0x180400, /* after cdt */ 144 .csc_fifosz = 0x001C00, /* let's just align this up */ 145 .csc_risc = 0x182000, /* after fifo */ 146 .csc_riscsz = 0x6000, /* room for dma programs */ 147 .csc_ptr1 = CXDTV_DMA28_PTR1, 148 .csc_ptr2 = CXDTV_DMA28_PTR2, 149 .csc_cnt1 = CXDTV_DMA28_CNT1, 150 .csc_cnt2 = CXDTV_DMA28_CNT2, 151 }, 152 }; 153 154 CFATTACH_DECL2_NEW(cxdtv, sizeof(struct cxdtv_softc), 155 cxdtv_match, cxdtv_attach, cxdtv_detach, NULL, 156 cxdtv_rescan, cxdtv_childdet); 157 158 static int 159 cxdtv_match(device_t parent, cfdata_t match, void *aux) 160 { 161 const struct pci_attach_args *pa; 162 pcireg_t reg; 163 164 pa = aux; 165 166 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 167 return 0; 168 169 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX2388XMPEG) 170 return 0; 171 172 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 173 if (cxdtv_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)) == NULL) 174 return 0; 175 176 return 1; 177 } 178 179 static void 180 cxdtv_attach(device_t parent, device_t self, void *aux) 181 { 182 struct cxdtv_softc *sc; 183 const struct pci_attach_args *pa = aux; 184 pci_intr_handle_t ih; 185 pcireg_t reg; 186 const char *intrstr; 187 struct i2cbus_attach_args iba; 188 char intrbuf[PCI_INTRSTR_LEN]; 189 190 sc = device_private(self); 191 192 sc->sc_dev = self; 193 sc->sc_pc = pa->pa_pc; 194 195 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 196 197 sc->sc_vendor = PCI_VENDOR(reg); 198 sc->sc_product = PCI_PRODUCT(reg); 199 200 sc->sc_board = cxdtv_board_lookup(sc->sc_vendor, sc->sc_product); 201 KASSERT(sc->sc_board != NULL); 202 203 pci_aprint_devinfo(pa, NULL); 204 205 if (pci_mapreg_map(pa, CXDTV_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 206 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 207 aprint_error_dev(self, "couldn't map memory space\n"); 208 return; 209 } 210 211 sc->sc_dmat = pa->pa_dmat; 212 213 if (pci_intr_map(pa, &ih)) { 214 aprint_error_dev(self, "couldn't map interrupt\n"); 215 return; 216 } 217 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 218 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_VM, cxdtv_intr, 219 sc, device_xname(self)); 220 if (sc->sc_ih == NULL) { 221 aprint_error_dev(self, "couldn't establish interrupt"); 222 if (intrstr != NULL) 223 aprint_error(" at %s", intrstr); 224 aprint_error("\n"); 225 return; 226 } 227 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 228 229 /* set master */ 230 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 231 reg |= PCI_COMMAND_MASTER_ENABLE; 232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 233 234 iic_tag_init(&sc->sc_i2c); 235 sc->sc_i2c.ic_cookie = sc; 236 sc->sc_i2c.ic_send_start = cxdtv_iic_send_start; 237 sc->sc_i2c.ic_send_stop = cxdtv_iic_send_stop; 238 sc->sc_i2c.ic_initiate_xfer = cxdtv_iic_initiate_xfer; 239 sc->sc_i2c.ic_read_byte = cxdtv_iic_read_byte; 240 sc->sc_i2c.ic_write_byte = cxdtv_iic_write_byte; 241 242 #if notyet 243 /* enable i2c compatible software mode */ 244 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, 245 CXDTV_I2C_C_DATACONTROL); 246 val = CXDTV_I2C_C_DATACONTROL_SCL | CXDTV_I2C_C_DATACONTROL_SDA; 247 bus_space_write_4(sc->sc_memt, sc->sc_memh, 248 CXDTV_I2C_C_DATACONTROL, val); 249 #endif 250 251 cxdtv_mpeg_attach(sc); 252 253 /* attach other devices to iic(4) */ 254 memset(&iba, 0, sizeof(iba)); 255 iba.iba_tag = &sc->sc_i2c; 256 config_found(self, &iba, iicbus_print, 257 CFARG_IATTR, "i2cbus", 258 CFARG_EOL); 259 260 if (!pmf_device_register(self, NULL, cxdtv_resume)) 261 aprint_error_dev(self, "couldn't establish power handler\n"); 262 263 return; 264 } 265 266 static int 267 cxdtv_detach(device_t self, int flags) 268 { 269 struct cxdtv_softc *sc = device_private(self); 270 int error; 271 272 error = cxdtv_mpeg_detach(sc, flags); 273 if (error) 274 return error; 275 276 if (sc->sc_ih) 277 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 278 279 if (sc->sc_mems) 280 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 281 282 iic_tag_fini(&sc->sc_i2c); 283 284 return 0; 285 } 286 287 static int 288 cxdtv_rescan(device_t self, const char *ifattr, const int *locs) 289 { 290 struct cxdtv_softc *sc = device_private(self); 291 struct dtv_attach_args daa; 292 293 daa.hw = &cxdtv_dtv_if; 294 daa.priv = sc; 295 296 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 297 sc->sc_dtvdev = config_found(sc->sc_dev, &daa, dtv_print, 298 CFARG_IATTR, "dtvbus", 299 CFARG_EOL); 300 301 return 0; 302 } 303 304 static void 305 cxdtv_childdet(device_t self, device_t child) 306 { 307 struct cxdtv_softc *sc = device_private(self); 308 309 if (child == sc->sc_dtvdev) 310 sc->sc_dtvdev = NULL; 311 } 312 313 static bool 314 cxdtv_resume(device_t dv, const pmf_qual_t *qual) 315 { 316 /* XXX revisit */ 317 318 aprint_debug_dev(dv, "%s\n", __func__); 319 320 return true; 321 } 322 323 static int 324 cxdtv_intr(void *intarg) 325 { 326 struct cxdtv_softc *sc = intarg; 327 uint32_t val; 328 329 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MSTAT); 330 if (val == 0) { 331 return 0; /* not ours */ 332 } 333 334 if (val & CXT_PI_TS_INT) { 335 cxdtv_mpeg_intr(sc); 336 } 337 338 if (val & ~CXT_PI_TS_INT) { 339 device_printf(sc->sc_dev, "%s, %08x\n", __func__, val); 340 } 341 342 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, val); 343 344 return 1; 345 } 346 347 /* I2C interface */ 348 349 static void 350 cxdtv_i2cbb_set_bits(void *cookie, uint32_t bits) 351 { 352 struct cxdtv_softc *sc = cookie; 353 354 bus_space_write_4(sc->sc_memt, sc->sc_memh, 355 CXDTV_I2C_C_DATACONTROL, bits); 356 (void)bus_space_read_4(sc->sc_memt, sc->sc_memh, 357 CXDTV_I2C_C_DATACONTROL); 358 359 return; 360 } 361 362 static void 363 cxdtv_i2cbb_set_dir(void *cookie, uint32_t bits) 364 { 365 return; 366 } 367 368 static uint32_t 369 cxdtv_i2cbb_read_bits(void *cookie) 370 { 371 struct cxdtv_softc *sc = cookie; 372 uint32_t value; 373 374 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 375 CXDTV_I2C_C_DATACONTROL); 376 377 return value; 378 } 379 380 static int 381 cxdtv_iic_send_start(void *cookie, int flags) 382 { 383 return i2c_bitbang_send_start(cookie, flags, &cxdtv_i2cbb_ops); 384 } 385 386 static int 387 cxdtv_iic_send_stop(void *cookie, int flags) 388 { 389 return i2c_bitbang_send_stop(cookie, flags, &cxdtv_i2cbb_ops); 390 } 391 392 static int 393 cxdtv_iic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 394 { 395 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &cxdtv_i2cbb_ops); 396 } 397 398 static int 399 cxdtv_iic_read_byte(void *cookie, uint8_t *data, int flags) 400 { 401 return i2c_bitbang_read_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 402 } 403 404 static int 405 cxdtv_iic_write_byte(void *cookie, uint8_t data, int flags) 406 { 407 return i2c_bitbang_write_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 408 } 409 410 int 411 cxdtv_mpeg_attach(struct cxdtv_softc *sc) 412 { 413 struct cxdtv_sram_ch *ch; 414 415 CX_DPRINTF(("cxdtv_mpeg_attach\n")); 416 417 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 418 419 sc->sc_riscbufsz = ch->csc_riscsz; 420 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 421 422 aprint_debug_dev(sc->sc_dev, "attaching frontend...\n"); 423 424 switch(sc->sc_vendor) { 425 case PCI_VENDOR_ATI: 426 cxdtv_card_init_hdtvwonder(sc); 427 break; 428 case PCI_VENDOR_PCHDTV: 429 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 430 cxdtv_card_init_hd5500(sc); 431 } 432 break; 433 } 434 435 KASSERT(sc->sc_tuner == NULL); 436 KASSERT(sc->sc_demod == NULL); 437 438 switch(sc->sc_board->cb_demod) { 439 case CXDTV_DEMOD_NXT2004: 440 sc->sc_demod = nxt2k_open(sc->sc_dev, &sc->sc_i2c, 0x0a, 0); 441 break; 442 case CXDTV_DEMOD_LG3303: 443 sc->sc_demod = lg3303_open(sc->sc_dev, &sc->sc_i2c, 0x59, 444 LG3303_CFG_SERIAL_INPUT); 445 break; 446 default: 447 break; 448 } 449 450 switch(sc->sc_board->cb_tuner) { 451 case CXDTV_TUNER_PLL: 452 if (sc->sc_vendor == PCI_VENDOR_ATI) 453 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tuv1236d_pll); 454 if (sc->sc_vendor == PCI_VENDOR_PCHDTV) 455 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tdvs_h06xf_pll); 456 break; 457 default: 458 break; 459 } 460 461 KASSERT(sc->sc_tuner != NULL); 462 KASSERT(sc->sc_demod != NULL); 463 464 cxdtv_rescan(sc->sc_dev, NULL, NULL); 465 466 return (sc->sc_dtvdev != NULL); 467 } 468 469 int 470 cxdtv_mpeg_detach(struct cxdtv_softc *sc, int flags) 471 { 472 int error = 0; 473 474 if (sc->sc_dtvdev) { 475 error = config_detach(sc->sc_dtvdev, flags); 476 if (error) 477 return error; 478 } 479 480 if (sc->sc_demod) { 481 switch (sc->sc_board->cb_demod) { 482 case CXDTV_DEMOD_NXT2004: 483 nxt2k_close(sc->sc_demod); 484 break; 485 case CXDTV_DEMOD_LG3303: 486 lg3303_close(sc->sc_demod); 487 break; 488 default: 489 break; 490 } 491 sc->sc_demod = NULL; 492 } 493 if (sc->sc_tuner) { 494 switch (sc->sc_board->cb_tuner) { 495 case CXDTV_TUNER_PLL: 496 tvpll_close(sc->sc_tuner); 497 break; 498 default: 499 break; 500 } 501 sc->sc_tuner = NULL; 502 } 503 504 if (sc->sc_riscbuf) { 505 kmem_free(sc->sc_riscbuf, sc->sc_riscbufsz); 506 sc->sc_riscbuf = NULL; 507 sc->sc_riscbufsz = 0; 508 } 509 510 return error; 511 } 512 513 static void 514 cxdtv_dtv_get_devinfo(void *priv, struct dvb_frontend_info *info) 515 { 516 memset(info, 0, sizeof(*info)); 517 strlcpy(info->name, "CX23880", sizeof(info->name)); 518 info->type = FE_ATSC; 519 info->frequency_min = 54000000; 520 info->frequency_max = 858000000; 521 info->frequency_stepsize = 62500; 522 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 523 } 524 525 static int 526 cxdtv_dtv_open(void *priv, int flags) 527 { 528 struct cxdtv_softc *sc = priv; 529 530 KASSERT(sc->sc_tsbuf == NULL); 531 532 cxdtv_mpeg_reset(sc); 533 534 /* allocate two alternating DMA areas for MPEG TS packets */ 535 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 536 537 if (sc->sc_tsbuf == NULL) 538 return ENOMEM; 539 540 return 0; 541 } 542 543 static void 544 cxdtv_dtv_close(void *priv) 545 { 546 struct cxdtv_softc *sc = priv; 547 548 cxdtv_dtv_stop_transfer(sc); 549 550 if (sc->sc_tsbuf != NULL) { 551 cxdtv_mpeg_free(sc, sc->sc_tsbuf); 552 sc->sc_tsbuf = NULL; 553 } 554 } 555 556 static int 557 cxdtv_dtv_set_tuner(void *priv, const struct dvb_frontend_parameters *params) 558 { 559 struct cxdtv_softc *sc = priv; 560 int error = -1; 561 562 switch(sc->sc_board->cb_tuner) { 563 case CXDTV_TUNER_PLL: 564 error = tvpll_tune_dtv(sc->sc_tuner, params); 565 } 566 if (error) 567 goto bad; 568 569 switch(sc->sc_board->cb_demod) { 570 case CXDTV_DEMOD_NXT2004: 571 error = nxt2k_set_modulation(sc->sc_demod, params->u.vsb.modulation); 572 break; 573 case CXDTV_DEMOD_LG3303: 574 error = lg3303_set_modulation(sc->sc_demod, params->u.vsb.modulation); 575 break; 576 default: 577 break; 578 } 579 580 bad: 581 return error; 582 } 583 584 static fe_status_t 585 cxdtv_dtv_get_status(void *priv) 586 { 587 struct cxdtv_softc *sc = priv; 588 589 switch(sc->sc_board->cb_demod) { 590 case CXDTV_DEMOD_NXT2004: 591 return nxt2k_get_dtv_status(sc->sc_demod); 592 case CXDTV_DEMOD_LG3303: 593 return lg3303_get_dtv_status(sc->sc_demod); 594 default: 595 return 0; 596 } 597 } 598 599 static uint16_t 600 cxdtv_dtv_get_signal_strength(void *priv) 601 { 602 struct cxdtv_softc *sc = priv; 603 604 switch(sc->sc_board->cb_demod) { 605 case CXDTV_DEMOD_NXT2004: 606 return 0; /* TODO */ 607 case CXDTV_DEMOD_LG3303: 608 return lg3303_get_signal_strength(sc->sc_demod); 609 } 610 611 return 0; 612 } 613 614 static uint16_t 615 cxdtv_dtv_get_snr(void *priv) 616 { 617 struct cxdtv_softc *sc = priv; 618 619 switch(sc->sc_board->cb_demod) { 620 case CXDTV_DEMOD_NXT2004: 621 return 0; /* TODO */ 622 case CXDTV_DEMOD_LG3303: 623 return lg3303_get_snr(sc->sc_demod); 624 } 625 626 return 0; 627 } 628 629 static int 630 cxdtv_dtv_start_transfer(void *priv, 631 void (*cb)(void *, const struct dtv_payload *), void *arg) 632 { 633 struct cxdtv_softc *sc = priv; 634 635 sc->sc_dtvsubmitcb = cb; 636 sc->sc_dtvsubmitarg = arg; 637 638 /* allocate two alternating DMA areas for MPEG TS packets */ 639 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 640 641 cxdtv_mpeg_trigger(sc, sc->sc_tsbuf); 642 643 return 0; 644 } 645 646 static int 647 cxdtv_dtv_stop_transfer(void *priv) 648 { 649 struct cxdtv_softc *sc = priv; 650 651 cxdtv_mpeg_halt(sc); 652 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 653 654 sc->sc_dtvsubmitcb = NULL; 655 sc->sc_dtvsubmitarg = NULL; 656 657 return 0; 658 } 659 660 int 661 cxdtv_mpeg_reset(struct cxdtv_softc *sc) 662 { 663 uint32_t v; 664 665 CX_DPRINTF(("cxdtv_mpeg_reset\n")); 666 667 v = (uint32_t)-1; 668 669 /* shutdown */ 670 /* hold RISC in reset */ 671 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 0); 672 /* disable FIFO and RISC */ 673 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 0); 674 /* mask off all interrupts */ 675 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 676 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 0); 677 678 /* clear interrupts */ 679 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, v); 680 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, v); 681 682 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 683 684 /* XXX magic */ 685 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_STHRSH, 0x0707); 686 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_DTHRSH, 0x0707); 687 688 /* reset external components*/ 689 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 0); 690 kpause("cxdtvrst", false, MAX(1, mstohz(1)), NULL); 691 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 1); 692 693 /* let error interrupts happen */ 694 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 695 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 696 v | 0x00fc00); /* XXX magic */ 697 698 return 0; 699 } 700 701 static int 702 cxdtv_risc_buffer(struct cxdtv_softc *sc, uint32_t bpl, uint32_t lines) 703 { 704 uint32_t *rm; 705 uint32_t size; 706 707 CX_DPRINTF(("cxdtv_risc_buffer: bpl=0x%x\n", bpl)); 708 709 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 710 size += 2; 711 712 device_printf(sc->sc_dev, "%s: est. inst. %d\n", __func__, size); 713 714 size *= 8; 715 device_printf(sc->sc_dev, "%s: est. qword %d\n", __func__, size); 716 717 if (sc->sc_riscbuf == NULL) { 718 device_printf(sc->sc_dev, "not enough memory for RISC\n"); 719 return ENOMEM; 720 } 721 722 rm = (uint32_t *)sc->sc_riscbuf; 723 cxdtv_risc_field(sc, rm, bpl); 724 725 return 0; 726 } 727 728 static int 729 cxdtv_risc_field(struct cxdtv_softc *sc, uint32_t *rm, uint32_t bpl) 730 { 731 struct cxdtv_dma *p; 732 733 CX_DPRINTF(("cxdtv_risc_field: bpl=0x%x\n", bpl)); 734 735 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 736 continue; 737 if (p == NULL) { 738 device_printf(sc->sc_dev, "cxdtv_risc_field: bad addr %p\n", 739 sc->sc_tsbuf); 740 return ENOENT; 741 } 742 743 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 744 745 rm = sc->sc_riscbuf; 746 747 /* htole32 will be done when program is copied to chip SRAM */ 748 749 /* XXX */ 750 *(rm++) = (CX_RISC_SYNC|0); 751 752 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 753 *(rm++) = (DMAADDR(p) + 0 * bpl); 754 755 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 756 *(rm++) = (DMAADDR(p) + 1 * bpl); 757 758 *(rm++) = (CX_RISC_JUMP|1); 759 *(rm++) = (cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG].csc_risc + 4); 760 761 return 0; 762 } 763 764 static int 765 cxdtv_sram_ch_setup(struct cxdtv_softc *sc, struct cxdtv_sram_ch *csc, 766 uint32_t bpl) 767 { 768 unsigned int i, lines; 769 uint32_t cdt; 770 771 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 772 773 /* XXX why round? */ 774 bpl = (bpl + 7) & ~7; 775 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 776 cdt = csc->csc_cdt; 777 lines = csc->csc_fifosz / bpl; 778 device_printf(sc->sc_dev, "%s %d lines\n", __func__, lines); 779 780 /* fill in CDT */ 781 for (i = 0; i < lines; i++) { 782 CX_DPRINTF(("CDT ent %08x, %08x\n", cdt + (16 * i), 783 csc->csc_fifo + (bpl * i))); 784 bus_space_write_4(sc->sc_memt, sc->sc_memh, 785 cdt + (16 * i), 786 csc->csc_fifo + (bpl * i)); 787 } 788 789 /* copy DMA program */ 790 791 /* converts program to little endian as it goes into SRAM */ 792 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 793 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 794 795 /* fill in CMDS */ 796 bus_space_write_4(sc->sc_memt, sc->sc_memh, 797 csc->csc_cmds + CX_CMDS_O_IRPC, csc->csc_risc); 798 799 bus_space_write_4(sc->sc_memt, sc->sc_memh, 800 csc->csc_cmds + CX_CMDS_O_CDTB, csc->csc_cdt); 801 bus_space_write_4(sc->sc_memt, sc->sc_memh, 802 csc->csc_cmds + CX_CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 803 804 bus_space_write_4(sc->sc_memt, sc->sc_memh, 805 csc->csc_cmds + CX_CMDS_O_IQB, csc->csc_iq); 806 bus_space_write_4(sc->sc_memt, sc->sc_memh, 807 csc->csc_cmds + CX_CMDS_O_IQS, 808 CX_CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 809 810 /* zero rest of CMDS */ 811 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x14, 0, 0x2c/4); 812 813 bus_space_write_4(sc->sc_memt, sc->sc_memh, 814 csc->csc_cnt1, (bpl >> 3) - 1); 815 816 bus_space_write_4(sc->sc_memt, sc->sc_memh, 817 csc->csc_ptr2, cdt); 818 bus_space_write_4(sc->sc_memt, sc->sc_memh, 819 csc->csc_cnt2, (lines * 16) >> 3); 820 821 return 0; 822 } 823 824 int 825 cxdtv_mpeg_trigger(struct cxdtv_softc *sc, void *buf) 826 { 827 struct cxdtv_dma *p; 828 struct cxdtv_sram_ch *ch; 829 uint32_t v; 830 831 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 832 833 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 834 continue; 835 if (p == NULL) { 836 device_printf(sc->sc_dev, "cxdtv_mpeg_trigger: bad addr %p\n", 837 buf); 838 return ENOENT; 839 } 840 841 CX_DPRINTF(("cxdtv_mpeg_trigger: buf=%p\n", buf)); 842 843 cxdtv_risc_buffer(sc, CXDTV_TS_PKTSIZE, 1); 844 cxdtv_sram_ch_setup(sc, ch, CXDTV_TS_PKTSIZE); 845 846 /* software reset */ 847 848 switch(sc->sc_vendor) { 849 case PCI_VENDOR_ATI: 850 /* both ATI boards with DTV are the same */ 851 bus_space_write_4(sc->sc_memt, sc->sc_memh, 852 CXDTV_TS_GEN_CONTROL, IPB_SW_RST); 853 delay(100); 854 /* parallel MPEG port */ 855 bus_space_write_4(sc->sc_memt, sc->sc_memh, 856 CXDTV_PINMUX_IO, MPEG_PAR_EN); 857 break; 858 case PCI_VENDOR_PCHDTV: 859 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 860 bus_space_write_4(sc->sc_memt, sc->sc_memh, 861 CXDTV_TS_GEN_CONTROL, IPB_SW_RST|IPB_SMODE); 862 delay(100); 863 bus_space_write_4(sc->sc_memt, sc->sc_memh, 864 CXDTV_PINMUX_IO, 0x00); /* serial MPEG port */ 865 /* byte-width start-of-packet */ 866 bus_space_write_4(sc->sc_memt, sc->sc_memh, 867 CXDTV_HW_SOP_CONTROL, 868 0x47 << 16 | 188 << 4 | 1); 869 bus_space_write_4(sc->sc_memt, sc->sc_memh, 870 CXDTV_TS_SOP_STATUS, IPB_SOP_BYTEWIDE); 871 /* serial MPEG port on HD5500 */ 872 bus_space_write_4(sc->sc_memt, sc->sc_memh, 873 CXDTV_TS_GEN_CONTROL, IPB_SMODE); 874 } 875 break; 876 default: 877 break; 878 } 879 880 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_LNGTH, 881 CXDTV_TS_PKTSIZE); 882 883 /* Configure for standard MPEG TS, 1 good packet to sync */ 884 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_HW_SOP_CONTROL, 885 0x47 << 16 | 188 << 4 | 1); 886 887 /* zero counter */ 888 bus_space_write_4(sc->sc_memt, sc->sc_memh, 889 CXDTV_TS_GP_CNT_CNTRL, 0x03); 890 891 /* enable bad packet interrupt */ 892 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_BD_PKT_STATUS, 893 0x1000); 894 895 /* enable overflow counter */ 896 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_FIFO_OVFL_STAT, 897 0x1000); 898 899 /* unmask TS interrupt */ 900 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 901 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 902 v | CXT_PI_TS_INT); 903 904 /* unmask all TS interrupts */ 905 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 906 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 907 v | 0x1f1011); 908 909 /* enable RISC DMA engine */ 910 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2); 911 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 912 v | CXDTV_DEV_CNTRL2_RUN_RISC); 913 914 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 915 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 916 v | CXDTV_TS_RISC_EN | CXDTV_TS_FIFO_EN); 917 918 return 0; 919 } 920 921 int 922 cxdtv_mpeg_halt(struct cxdtv_softc *sc) 923 { 924 uint32_t v; 925 926 CX_DPRINTF(("cxdtv_mpeg_halt\n")); 927 928 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 929 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 930 v & ~(CXDTV_TS_RISC_EN|CXDTV_TS_FIFO_EN)); 931 932 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 933 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 934 v & ~CXT_PI_TS_INT); 935 936 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 937 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 938 v & ~0x1f1011); 939 940 return 0; 941 } 942 943 int 944 cxdtv_mpeg_intr(struct cxdtv_softc *sc) 945 { 946 struct dtv_payload payload; 947 uint32_t s, m; 948 949 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT); 950 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 951 if ((s & m) == 0) 952 return 0; 953 954 if ( (s & ~CXDTV_TS_RISCI) != 0 ) 955 device_printf(sc->sc_dev, "unexpected TS IS %08x\n", s); 956 957 if (sc->sc_dtvsubmitcb == NULL) 958 goto done; 959 960 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 961 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 962 0, CXDTV_TS_PKTSIZE, 963 BUS_DMASYNC_POSTREAD); 964 payload.data = KERNADDR(sc->sc_dma); 965 payload.size = CXDTV_TS_PKTSIZE; 966 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 967 } 968 969 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 970 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 971 CXDTV_TS_PKTSIZE, CXDTV_TS_PKTSIZE, 972 BUS_DMASYNC_POSTREAD); 973 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CXDTV_TS_PKTSIZE; 974 payload.size = CXDTV_TS_PKTSIZE; 975 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 976 } 977 978 done: 979 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, s); 980 981 return 1; 982 } 983 984 static int 985 cxdtv_allocmem(struct cxdtv_softc *sc, size_t size, size_t align, 986 struct cxdtv_dma *p) 987 { 988 int err; 989 990 p->size = size; 991 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 992 p->segs, __arraycount(p->segs), 993 &p->nsegs, BUS_DMA_NOWAIT); 994 if (err) 995 return err; 996 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 997 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 998 if (err) 999 goto free; 1000 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 1001 BUS_DMA_NOWAIT, &p->map); 1002 if (err) 1003 goto unmap; 1004 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 1005 BUS_DMA_NOWAIT); 1006 if (err) 1007 goto destroy; 1008 1009 return 0; 1010 1011 destroy: 1012 bus_dmamap_destroy(sc->sc_dmat, p->map); 1013 unmap: 1014 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1015 free: 1016 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1017 1018 return err; 1019 } 1020 1021 static int 1022 cxdtv_freemem(struct cxdtv_softc *sc, struct cxdtv_dma *p) 1023 { 1024 1025 bus_dmamap_unload(sc->sc_dmat, p->map); 1026 bus_dmamap_destroy(sc->sc_dmat, p->map); 1027 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1028 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1029 1030 return 0; 1031 } 1032 1033 void * 1034 cxdtv_mpeg_malloc(struct cxdtv_softc *sc, size_t size) 1035 { 1036 struct cxdtv_dma *p; 1037 int err; 1038 1039 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1040 err = cxdtv_allocmem(sc, size, 16, p); 1041 if (err) { 1042 kmem_free(p, sizeof(*p)); 1043 device_printf(sc->sc_dev, "not enough memory\n"); 1044 return NULL; 1045 } 1046 1047 p->next = sc->sc_dma; 1048 sc->sc_dma = p; 1049 1050 return KERNADDR(p); 1051 } 1052 1053 static void 1054 cxdtv_mpeg_free(struct cxdtv_softc *sc, void *addr) 1055 { 1056 struct cxdtv_dma *p; 1057 struct cxdtv_dma **pp; 1058 1059 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) { 1060 if (KERNADDR(p) == addr) { 1061 cxdtv_freemem(sc, p); 1062 *pp = p->next; 1063 kmem_free(p, sizeof(*p)); 1064 return; 1065 } 1066 } 1067 1068 device_printf(sc->sc_dev, "%p is already free\n", addr); 1069 1070 return; 1071 } 1072 1073 1074 /* ATI HDTV Wonder */ 1075 static void 1076 cxdtv_card_init_hdtvwonder(struct cxdtv_softc *sc) 1077 { 1078 int i, x; 1079 i2c_addr_t na; 1080 uint8_t nb[5][2] = { 1081 {0x10, 0x12}, {0x13, 0x04}, {0x16, 0x00}, 1082 {0x14, 0x04}, {0x17, 0x00} 1083 }; 1084 1085 /* prepare TUV1236D/TU1236F NIM */ 1086 1087 na = 0x0a; /* Nxt2004 address */ 1088 x = 0; 1089 1090 iic_acquire_bus(&sc->sc_i2c, 0); 1091 1092 for(i = 0; i < 5; i++) 1093 x |= iic_exec(&sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, na, 1094 nb[i], 2, NULL, 0, 0); 1095 1096 iic_release_bus(&sc->sc_i2c, 0); 1097 1098 if (x) 1099 aprint_error_dev(sc->sc_dev, "HDTV Wonder tuner init failed"); 1100 } 1101 1102 /* pcHDTV HD5500 */ 1103 #define cxdtv_write_field(_mask, _shift, _value) \ 1104 (((_value) & (_mask)) << (_shift)) 1105 1106 static void 1107 cxdtv_write_gpio(struct cxdtv_softc *sc, uint32_t mask, uint32_t value) 1108 { 1109 uint32_t v = 0; 1110 v |= cxdtv_write_field(0xff, 16, mask); 1111 v |= cxdtv_write_field(0xff, 8, mask); 1112 v |= cxdtv_write_field(0xff, 0, (mask & value)); 1113 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_GP0_IO, v); 1114 } 1115 1116 static void 1117 cxdtv_card_init_hd5500(struct cxdtv_softc *sc) 1118 { 1119 /* hardware (demod) reset */ 1120 cxdtv_write_gpio(sc, 1, 0); 1121 delay(100000); 1122 cxdtv_write_gpio(sc, 1, 1); 1123 delay(200000); 1124 } 1125 1126 MODULE(MODULE_CLASS_DRIVER, cxdtv, "tvpll,nxt2k,lg3303,pci"); 1127 1128 #ifdef _MODULE 1129 #include "ioconf.c" 1130 #endif 1131 1132 static int 1133 cxdtv_modcmd(modcmd_t cmd, void *opaque) 1134 { 1135 switch (cmd) { 1136 case MODULE_CMD_INIT: 1137 #ifdef _MODULE 1138 return config_init_component(cfdriver_ioconf_cxdtv, 1139 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1140 #else 1141 return 0; 1142 #endif 1143 case MODULE_CMD_FINI: 1144 #ifdef _MODULE 1145 return config_fini_component(cfdriver_ioconf_cxdtv, 1146 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1147 #else 1148 return 0; 1149 #endif 1150 default: 1151 return ENOTTY; 1152 } 1153 } 1154
Indexes created Fri Oct 03 02:09:57 GMT 2025