cxdtv.c revision 1.20
1 /* $NetBSD: cxdtv.c,v 1.20 2021/08/07 16:19:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.20 2021/08/07 16:19:14 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/proc.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_bitbang.h> 46 47 #include <dev/i2c/tvpllvar.h> 48 #include <dev/i2c/tvpll_tuners.h> 49 50 #include <dev/i2c/nxt2kvar.h> 51 #include <dev/i2c/lg3303var.h> 52 53 #include <dev/dtv/dtvif.h> 54 55 #include <dev/pci/cxdtvreg.h> 56 #include <dev/pci/cxdtvvar.h> 57 #include <dev/pci/cxdtv_boards.h> 58 59 #define CXDTV_MMBASE 0x10 60 61 #define CXDTV_SRAM_CH_MPEG 0 62 #define CXDTV_TS_PKTSIZE (188 * 8) 63 64 static int cxdtv_match(device_t, cfdata_t, void *); 65 static void cxdtv_attach(device_t, device_t, void *); 66 static int cxdtv_detach(device_t, int); 67 static int cxdtv_rescan(device_t, const char *, const int *); 68 static void cxdtv_childdet(device_t, device_t); 69 static int cxdtv_intr(void *); 70 71 static bool cxdtv_resume(device_t, const pmf_qual_t *); 72 73 static int cxdtv_iic_send_start(void *, int); 74 static int cxdtv_iic_send_stop(void *, int); 75 static int cxdtv_iic_initiate_xfer(void *, i2c_addr_t, int); 76 static int cxdtv_iic_read_byte(void *, uint8_t *, int); 77 static int cxdtv_iic_write_byte(void *, uint8_t, int); 78 79 static void cxdtv_i2cbb_set_bits(void *, uint32_t); 80 static void cxdtv_i2cbb_set_dir(void *, uint32_t); 81 static uint32_t cxdtv_i2cbb_read_bits(void *); 82 83 static int cxdtv_sram_ch_setup(struct cxdtv_softc *, 84 struct cxdtv_sram_ch *, uint32_t); 85 static int cxdtv_allocmem(struct cxdtv_softc *, size_t, size_t, 86 struct cxdtv_dma *); 87 static int cxdtv_freemem(struct cxdtv_softc *, struct cxdtv_dma *); 88 static int cxdtv_risc_buffer(struct cxdtv_softc *, uint32_t, uint32_t); 89 static int cxdtv_risc_field(struct cxdtv_softc *, uint32_t *, uint32_t); 90 91 static int cxdtv_mpeg_attach(struct cxdtv_softc *); 92 static int cxdtv_mpeg_detach(struct cxdtv_softc *, int flags); 93 static int cxdtv_mpeg_intr(struct cxdtv_softc *); 94 static int cxdtv_mpeg_reset(struct cxdtv_softc *); 95 96 static int cxdtv_mpeg_trigger(struct cxdtv_softc *, void *); 97 static int cxdtv_mpeg_halt(struct cxdtv_softc *); 98 static void * cxdtv_mpeg_malloc(struct cxdtv_softc *, size_t); 99 static void cxdtv_mpeg_free(struct cxdtv_softc *, void *); 100 101 static void cxdtv_card_init_hd5500(struct cxdtv_softc *); 102 static void cxdtv_card_init_hdtvwonder(struct cxdtv_softc *); 103 104 /* MPEG TS Port */ 105 static void cxdtv_dtv_get_devinfo(void *, struct dvb_frontend_info *); 106 static int cxdtv_dtv_open(void *, int); 107 static void cxdtv_dtv_close(void *); 108 static int cxdtv_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 109 static fe_status_t cxdtv_dtv_get_status(void *); 110 static uint16_t cxdtv_dtv_get_signal_strength(void *); 111 static uint16_t cxdtv_dtv_get_snr(void *); 112 static int cxdtv_dtv_start_transfer(void *, 113 void (*)(void *, const struct dtv_payload *), void *); 114 static int cxdtv_dtv_stop_transfer(void *); 115 116 static const struct dtv_hw_if cxdtv_dtv_if = { 117 .get_devinfo = cxdtv_dtv_get_devinfo, 118 .open = cxdtv_dtv_open, 119 .close = cxdtv_dtv_close, 120 .set_tuner = cxdtv_dtv_set_tuner, 121 .get_status = cxdtv_dtv_get_status, 122 .get_signal_strength = cxdtv_dtv_get_signal_strength, 123 .get_snr = cxdtv_dtv_get_snr, 124 .start_transfer = cxdtv_dtv_start_transfer, 125 .stop_transfer = cxdtv_dtv_stop_transfer, 126 }; 127 128 const struct i2c_bitbang_ops cxdtv_i2cbb_ops = { 129 cxdtv_i2cbb_set_bits, 130 cxdtv_i2cbb_set_dir, 131 cxdtv_i2cbb_read_bits, 132 { CXDTV_I2C_C_DATACONTROL_SDA, CXDTV_I2C_C_DATACONTROL_SCL, 0, 0 } 133 }; 134 135 /* Maybe make this dynamically allocated. */ 136 static struct cxdtv_sram_ch cxdtv_sram_chs[] = { 137 [CXDTV_SRAM_CH_MPEG] = { 138 .csc_cmds = 0x180200, /* CMDS for ch. 28 */ 139 .csc_iq = 0x180340, /* after last CMDS */ 140 .csc_iqsz = 0x40, /* 16 dwords */ 141 .csc_cdt = 0x180380, /* after iq */ 142 .csc_cdtsz = 0x40, /* cluster discriptor space */ 143 .csc_fifo = 0x180400, /* after cdt */ 144 .csc_fifosz = 0x001C00, /* let's just align this up */ 145 .csc_risc = 0x182000, /* after fifo */ 146 .csc_riscsz = 0x6000, /* room for dma programs */ 147 .csc_ptr1 = CXDTV_DMA28_PTR1, 148 .csc_ptr2 = CXDTV_DMA28_PTR2, 149 .csc_cnt1 = CXDTV_DMA28_CNT1, 150 .csc_cnt2 = CXDTV_DMA28_CNT2, 151 }, 152 }; 153 154 CFATTACH_DECL2_NEW(cxdtv, sizeof(struct cxdtv_softc), 155 cxdtv_match, cxdtv_attach, cxdtv_detach, NULL, 156 cxdtv_rescan, cxdtv_childdet); 157 158 static int 159 cxdtv_match(device_t parent, cfdata_t match, void *aux) 160 { 161 const struct pci_attach_args *pa; 162 pcireg_t reg; 163 164 pa = aux; 165 166 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 167 return 0; 168 169 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX2388XMPEG) 170 return 0; 171 172 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 173 if (cxdtv_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)) == NULL) 174 return 0; 175 176 return 1; 177 } 178 179 static void 180 cxdtv_attach(device_t parent, device_t self, void *aux) 181 { 182 struct cxdtv_softc *sc; 183 const struct pci_attach_args *pa = aux; 184 pci_intr_handle_t ih; 185 pcireg_t reg; 186 const char *intrstr; 187 struct i2cbus_attach_args iba; 188 char intrbuf[PCI_INTRSTR_LEN]; 189 190 sc = device_private(self); 191 192 sc->sc_dev = self; 193 sc->sc_pc = pa->pa_pc; 194 195 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 196 197 sc->sc_vendor = PCI_VENDOR(reg); 198 sc->sc_product = PCI_PRODUCT(reg); 199 200 sc->sc_board = cxdtv_board_lookup(sc->sc_vendor, sc->sc_product); 201 KASSERT(sc->sc_board != NULL); 202 203 pci_aprint_devinfo(pa, NULL); 204 205 if (pci_mapreg_map(pa, CXDTV_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 206 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 207 aprint_error_dev(self, "couldn't map memory space\n"); 208 return; 209 } 210 211 sc->sc_dmat = pa->pa_dmat; 212 213 if (pci_intr_map(pa, &ih)) { 214 aprint_error_dev(self, "couldn't map interrupt\n"); 215 return; 216 } 217 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 218 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_VM, cxdtv_intr, 219 sc, device_xname(self)); 220 if (sc->sc_ih == NULL) { 221 aprint_error_dev(self, "couldn't establish interrupt"); 222 if (intrstr != NULL) 223 aprint_error(" at %s", intrstr); 224 aprint_error("\n"); 225 return; 226 } 227 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 228 229 /* set master */ 230 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 231 reg |= PCI_COMMAND_MASTER_ENABLE; 232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 233 234 iic_tag_init(&sc->sc_i2c); 235 sc->sc_i2c.ic_cookie = sc; 236 sc->sc_i2c.ic_send_start = cxdtv_iic_send_start; 237 sc->sc_i2c.ic_send_stop = cxdtv_iic_send_stop; 238 sc->sc_i2c.ic_initiate_xfer = cxdtv_iic_initiate_xfer; 239 sc->sc_i2c.ic_read_byte = cxdtv_iic_read_byte; 240 sc->sc_i2c.ic_write_byte = cxdtv_iic_write_byte; 241 242 #if notyet 243 /* enable i2c compatible software mode */ 244 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, 245 CXDTV_I2C_C_DATACONTROL); 246 val = CXDTV_I2C_C_DATACONTROL_SCL | CXDTV_I2C_C_DATACONTROL_SDA; 247 bus_space_write_4(sc->sc_memt, sc->sc_memh, 248 CXDTV_I2C_C_DATACONTROL, val); 249 #endif 250 251 cxdtv_mpeg_attach(sc); 252 253 /* attach other devices to iic(4) */ 254 memset(&iba, 0, sizeof(iba)); 255 iba.iba_tag = &sc->sc_i2c; 256 config_found(self, &iba, iicbus_print, 257 CFARGS(.iattr = "i2cbus")); 258 259 if (!pmf_device_register(self, NULL, cxdtv_resume)) 260 aprint_error_dev(self, "couldn't establish power handler\n"); 261 262 return; 263 } 264 265 static int 266 cxdtv_detach(device_t self, int flags) 267 { 268 struct cxdtv_softc *sc = device_private(self); 269 int error; 270 271 error = cxdtv_mpeg_detach(sc, flags); 272 if (error) 273 return error; 274 275 if (sc->sc_ih) 276 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 277 278 if (sc->sc_mems) 279 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 280 281 iic_tag_fini(&sc->sc_i2c); 282 283 return 0; 284 } 285 286 static int 287 cxdtv_rescan(device_t self, const char *ifattr, const int *locs) 288 { 289 struct cxdtv_softc *sc = device_private(self); 290 struct dtv_attach_args daa; 291 292 daa.hw = &cxdtv_dtv_if; 293 daa.priv = sc; 294 295 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 296 sc->sc_dtvdev = config_found(sc->sc_dev, &daa, dtv_print, 297 CFARGS(.iattr = "dtvbus")); 298 299 return 0; 300 } 301 302 static void 303 cxdtv_childdet(device_t self, device_t child) 304 { 305 struct cxdtv_softc *sc = device_private(self); 306 307 if (child == sc->sc_dtvdev) 308 sc->sc_dtvdev = NULL; 309 } 310 311 static bool 312 cxdtv_resume(device_t dv, const pmf_qual_t *qual) 313 { 314 /* XXX revisit */ 315 316 aprint_debug_dev(dv, "%s\n", __func__); 317 318 return true; 319 } 320 321 static int 322 cxdtv_intr(void *intarg) 323 { 324 struct cxdtv_softc *sc = intarg; 325 uint32_t val; 326 327 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MSTAT); 328 if (val == 0) { 329 return 0; /* not ours */ 330 } 331 332 if (val & CXT_PI_TS_INT) { 333 cxdtv_mpeg_intr(sc); 334 } 335 336 if (val & ~CXT_PI_TS_INT) { 337 device_printf(sc->sc_dev, "%s, %08x\n", __func__, val); 338 } 339 340 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, val); 341 342 return 1; 343 } 344 345 /* I2C interface */ 346 347 static void 348 cxdtv_i2cbb_set_bits(void *cookie, uint32_t bits) 349 { 350 struct cxdtv_softc *sc = cookie; 351 352 bus_space_write_4(sc->sc_memt, sc->sc_memh, 353 CXDTV_I2C_C_DATACONTROL, bits); 354 (void)bus_space_read_4(sc->sc_memt, sc->sc_memh, 355 CXDTV_I2C_C_DATACONTROL); 356 357 return; 358 } 359 360 static void 361 cxdtv_i2cbb_set_dir(void *cookie, uint32_t bits) 362 { 363 return; 364 } 365 366 static uint32_t 367 cxdtv_i2cbb_read_bits(void *cookie) 368 { 369 struct cxdtv_softc *sc = cookie; 370 uint32_t value; 371 372 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 373 CXDTV_I2C_C_DATACONTROL); 374 375 return value; 376 } 377 378 static int 379 cxdtv_iic_send_start(void *cookie, int flags) 380 { 381 return i2c_bitbang_send_start(cookie, flags, &cxdtv_i2cbb_ops); 382 } 383 384 static int 385 cxdtv_iic_send_stop(void *cookie, int flags) 386 { 387 return i2c_bitbang_send_stop(cookie, flags, &cxdtv_i2cbb_ops); 388 } 389 390 static int 391 cxdtv_iic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 392 { 393 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &cxdtv_i2cbb_ops); 394 } 395 396 static int 397 cxdtv_iic_read_byte(void *cookie, uint8_t *data, int flags) 398 { 399 return i2c_bitbang_read_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 400 } 401 402 static int 403 cxdtv_iic_write_byte(void *cookie, uint8_t data, int flags) 404 { 405 return i2c_bitbang_write_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 406 } 407 408 int 409 cxdtv_mpeg_attach(struct cxdtv_softc *sc) 410 { 411 struct cxdtv_sram_ch *ch; 412 413 CX_DPRINTF(("cxdtv_mpeg_attach\n")); 414 415 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 416 417 sc->sc_riscbufsz = ch->csc_riscsz; 418 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 419 420 aprint_debug_dev(sc->sc_dev, "attaching frontend...\n"); 421 422 switch(sc->sc_vendor) { 423 case PCI_VENDOR_ATI: 424 cxdtv_card_init_hdtvwonder(sc); 425 break; 426 case PCI_VENDOR_PCHDTV: 427 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 428 cxdtv_card_init_hd5500(sc); 429 } 430 break; 431 } 432 433 KASSERT(sc->sc_tuner == NULL); 434 KASSERT(sc->sc_demod == NULL); 435 436 switch(sc->sc_board->cb_demod) { 437 case CXDTV_DEMOD_NXT2004: 438 sc->sc_demod = nxt2k_open(sc->sc_dev, &sc->sc_i2c, 0x0a, 0); 439 break; 440 case CXDTV_DEMOD_LG3303: 441 sc->sc_demod = lg3303_open(sc->sc_dev, &sc->sc_i2c, 0x59, 442 LG3303_CFG_SERIAL_INPUT); 443 break; 444 default: 445 break; 446 } 447 448 switch(sc->sc_board->cb_tuner) { 449 case CXDTV_TUNER_PLL: 450 if (sc->sc_vendor == PCI_VENDOR_ATI) 451 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tuv1236d_pll); 452 if (sc->sc_vendor == PCI_VENDOR_PCHDTV) 453 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tdvs_h06xf_pll); 454 break; 455 default: 456 break; 457 } 458 459 KASSERT(sc->sc_tuner != NULL); 460 KASSERT(sc->sc_demod != NULL); 461 462 cxdtv_rescan(sc->sc_dev, NULL, NULL); 463 464 return (sc->sc_dtvdev != NULL); 465 } 466 467 int 468 cxdtv_mpeg_detach(struct cxdtv_softc *sc, int flags) 469 { 470 int error = 0; 471 472 if (sc->sc_dtvdev) { 473 error = config_detach(sc->sc_dtvdev, flags); 474 if (error) 475 return error; 476 } 477 478 if (sc->sc_demod) { 479 switch (sc->sc_board->cb_demod) { 480 case CXDTV_DEMOD_NXT2004: 481 nxt2k_close(sc->sc_demod); 482 break; 483 case CXDTV_DEMOD_LG3303: 484 lg3303_close(sc->sc_demod); 485 break; 486 default: 487 break; 488 } 489 sc->sc_demod = NULL; 490 } 491 if (sc->sc_tuner) { 492 switch (sc->sc_board->cb_tuner) { 493 case CXDTV_TUNER_PLL: 494 tvpll_close(sc->sc_tuner); 495 break; 496 default: 497 break; 498 } 499 sc->sc_tuner = NULL; 500 } 501 502 if (sc->sc_riscbuf) { 503 kmem_free(sc->sc_riscbuf, sc->sc_riscbufsz); 504 sc->sc_riscbuf = NULL; 505 sc->sc_riscbufsz = 0; 506 } 507 508 return error; 509 } 510 511 static void 512 cxdtv_dtv_get_devinfo(void *priv, struct dvb_frontend_info *info) 513 { 514 memset(info, 0, sizeof(*info)); 515 strlcpy(info->name, "CX23880", sizeof(info->name)); 516 info->type = FE_ATSC; 517 info->frequency_min = 54000000; 518 info->frequency_max = 858000000; 519 info->frequency_stepsize = 62500; 520 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 521 } 522 523 static int 524 cxdtv_dtv_open(void *priv, int flags) 525 { 526 struct cxdtv_softc *sc = priv; 527 528 KASSERT(sc->sc_tsbuf == NULL); 529 530 cxdtv_mpeg_reset(sc); 531 532 /* allocate two alternating DMA areas for MPEG TS packets */ 533 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 534 535 if (sc->sc_tsbuf == NULL) 536 return ENOMEM; 537 538 return 0; 539 } 540 541 static void 542 cxdtv_dtv_close(void *priv) 543 { 544 struct cxdtv_softc *sc = priv; 545 546 cxdtv_dtv_stop_transfer(sc); 547 548 if (sc->sc_tsbuf != NULL) { 549 cxdtv_mpeg_free(sc, sc->sc_tsbuf); 550 sc->sc_tsbuf = NULL; 551 } 552 } 553 554 static int 555 cxdtv_dtv_set_tuner(void *priv, const struct dvb_frontend_parameters *params) 556 { 557 struct cxdtv_softc *sc = priv; 558 int error = -1; 559 560 switch(sc->sc_board->cb_tuner) { 561 case CXDTV_TUNER_PLL: 562 error = tvpll_tune_dtv(sc->sc_tuner, params); 563 } 564 if (error) 565 goto bad; 566 567 switch(sc->sc_board->cb_demod) { 568 case CXDTV_DEMOD_NXT2004: 569 error = nxt2k_set_modulation(sc->sc_demod, params->u.vsb.modulation); 570 break; 571 case CXDTV_DEMOD_LG3303: 572 error = lg3303_set_modulation(sc->sc_demod, params->u.vsb.modulation); 573 break; 574 default: 575 break; 576 } 577 578 bad: 579 return error; 580 } 581 582 static fe_status_t 583 cxdtv_dtv_get_status(void *priv) 584 { 585 struct cxdtv_softc *sc = priv; 586 587 switch(sc->sc_board->cb_demod) { 588 case CXDTV_DEMOD_NXT2004: 589 return nxt2k_get_dtv_status(sc->sc_demod); 590 case CXDTV_DEMOD_LG3303: 591 return lg3303_get_dtv_status(sc->sc_demod); 592 default: 593 return 0; 594 } 595 } 596 597 static uint16_t 598 cxdtv_dtv_get_signal_strength(void *priv) 599 { 600 struct cxdtv_softc *sc = priv; 601 602 switch(sc->sc_board->cb_demod) { 603 case CXDTV_DEMOD_NXT2004: 604 return 0; /* TODO */ 605 case CXDTV_DEMOD_LG3303: 606 return lg3303_get_signal_strength(sc->sc_demod); 607 } 608 609 return 0; 610 } 611 612 static uint16_t 613 cxdtv_dtv_get_snr(void *priv) 614 { 615 struct cxdtv_softc *sc = priv; 616 617 switch(sc->sc_board->cb_demod) { 618 case CXDTV_DEMOD_NXT2004: 619 return 0; /* TODO */ 620 case CXDTV_DEMOD_LG3303: 621 return lg3303_get_snr(sc->sc_demod); 622 } 623 624 return 0; 625 } 626 627 static int 628 cxdtv_dtv_start_transfer(void *priv, 629 void (*cb)(void *, const struct dtv_payload *), void *arg) 630 { 631 struct cxdtv_softc *sc = priv; 632 633 sc->sc_dtvsubmitcb = cb; 634 sc->sc_dtvsubmitarg = arg; 635 636 /* allocate two alternating DMA areas for MPEG TS packets */ 637 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 638 639 cxdtv_mpeg_trigger(sc, sc->sc_tsbuf); 640 641 return 0; 642 } 643 644 static int 645 cxdtv_dtv_stop_transfer(void *priv) 646 { 647 struct cxdtv_softc *sc = priv; 648 649 cxdtv_mpeg_halt(sc); 650 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 651 652 sc->sc_dtvsubmitcb = NULL; 653 sc->sc_dtvsubmitarg = NULL; 654 655 return 0; 656 } 657 658 int 659 cxdtv_mpeg_reset(struct cxdtv_softc *sc) 660 { 661 uint32_t v; 662 663 CX_DPRINTF(("cxdtv_mpeg_reset\n")); 664 665 v = (uint32_t)-1; 666 667 /* shutdown */ 668 /* hold RISC in reset */ 669 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 0); 670 /* disable FIFO and RISC */ 671 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 0); 672 /* mask off all interrupts */ 673 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 674 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 0); 675 676 /* clear interrupts */ 677 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, v); 678 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, v); 679 680 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 681 682 /* XXX magic */ 683 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_STHRSH, 0x0707); 684 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_DTHRSH, 0x0707); 685 686 /* reset external components*/ 687 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 0); 688 kpause("cxdtvrst", false, MAX(1, mstohz(1)), NULL); 689 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 1); 690 691 /* let error interrupts happen */ 692 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 693 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 694 v | 0x00fc00); /* XXX magic */ 695 696 return 0; 697 } 698 699 static int 700 cxdtv_risc_buffer(struct cxdtv_softc *sc, uint32_t bpl, uint32_t lines) 701 { 702 uint32_t *rm; 703 uint32_t size; 704 705 CX_DPRINTF(("cxdtv_risc_buffer: bpl=0x%x\n", bpl)); 706 707 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 708 size += 2; 709 710 device_printf(sc->sc_dev, "%s: est. inst. %d\n", __func__, size); 711 712 size *= 8; 713 device_printf(sc->sc_dev, "%s: est. qword %d\n", __func__, size); 714 715 if (sc->sc_riscbuf == NULL) { 716 device_printf(sc->sc_dev, "not enough memory for RISC\n"); 717 return ENOMEM; 718 } 719 720 rm = (uint32_t *)sc->sc_riscbuf; 721 cxdtv_risc_field(sc, rm, bpl); 722 723 return 0; 724 } 725 726 static int 727 cxdtv_risc_field(struct cxdtv_softc *sc, uint32_t *rm, uint32_t bpl) 728 { 729 struct cxdtv_dma *p; 730 731 CX_DPRINTF(("cxdtv_risc_field: bpl=0x%x\n", bpl)); 732 733 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 734 continue; 735 if (p == NULL) { 736 device_printf(sc->sc_dev, "cxdtv_risc_field: bad addr %p\n", 737 sc->sc_tsbuf); 738 return ENOENT; 739 } 740 741 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 742 743 rm = sc->sc_riscbuf; 744 745 /* htole32 will be done when program is copied to chip SRAM */ 746 747 /* XXX */ 748 *(rm++) = (CX_RISC_SYNC|0); 749 750 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 751 *(rm++) = (DMAADDR(p) + 0 * bpl); 752 753 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 754 *(rm++) = (DMAADDR(p) + 1 * bpl); 755 756 *(rm++) = (CX_RISC_JUMP|1); 757 *(rm++) = (cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG].csc_risc + 4); 758 759 return 0; 760 } 761 762 static int 763 cxdtv_sram_ch_setup(struct cxdtv_softc *sc, struct cxdtv_sram_ch *csc, 764 uint32_t bpl) 765 { 766 unsigned int i, lines; 767 uint32_t cdt; 768 769 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 770 771 /* XXX why round? */ 772 bpl = (bpl + 7) & ~7; 773 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 774 cdt = csc->csc_cdt; 775 lines = csc->csc_fifosz / bpl; 776 device_printf(sc->sc_dev, "%s %d lines\n", __func__, lines); 777 778 /* fill in CDT */ 779 for (i = 0; i < lines; i++) { 780 CX_DPRINTF(("CDT ent %08x, %08x\n", cdt + (16 * i), 781 csc->csc_fifo + (bpl * i))); 782 bus_space_write_4(sc->sc_memt, sc->sc_memh, 783 cdt + (16 * i), 784 csc->csc_fifo + (bpl * i)); 785 } 786 787 /* copy DMA program */ 788 789 /* converts program to little endian as it goes into SRAM */ 790 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 791 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 792 793 /* fill in CMDS */ 794 bus_space_write_4(sc->sc_memt, sc->sc_memh, 795 csc->csc_cmds + CX_CMDS_O_IRPC, csc->csc_risc); 796 797 bus_space_write_4(sc->sc_memt, sc->sc_memh, 798 csc->csc_cmds + CX_CMDS_O_CDTB, csc->csc_cdt); 799 bus_space_write_4(sc->sc_memt, sc->sc_memh, 800 csc->csc_cmds + CX_CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 801 802 bus_space_write_4(sc->sc_memt, sc->sc_memh, 803 csc->csc_cmds + CX_CMDS_O_IQB, csc->csc_iq); 804 bus_space_write_4(sc->sc_memt, sc->sc_memh, 805 csc->csc_cmds + CX_CMDS_O_IQS, 806 CX_CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 807 808 /* zero rest of CMDS */ 809 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x14, 0, 0x2c/4); 810 811 bus_space_write_4(sc->sc_memt, sc->sc_memh, 812 csc->csc_cnt1, (bpl >> 3) - 1); 813 814 bus_space_write_4(sc->sc_memt, sc->sc_memh, 815 csc->csc_ptr2, cdt); 816 bus_space_write_4(sc->sc_memt, sc->sc_memh, 817 csc->csc_cnt2, (lines * 16) >> 3); 818 819 return 0; 820 } 821 822 int 823 cxdtv_mpeg_trigger(struct cxdtv_softc *sc, void *buf) 824 { 825 struct cxdtv_dma *p; 826 struct cxdtv_sram_ch *ch; 827 uint32_t v; 828 829 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 830 831 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 832 continue; 833 if (p == NULL) { 834 device_printf(sc->sc_dev, "cxdtv_mpeg_trigger: bad addr %p\n", 835 buf); 836 return ENOENT; 837 } 838 839 CX_DPRINTF(("cxdtv_mpeg_trigger: buf=%p\n", buf)); 840 841 cxdtv_risc_buffer(sc, CXDTV_TS_PKTSIZE, 1); 842 cxdtv_sram_ch_setup(sc, ch, CXDTV_TS_PKTSIZE); 843 844 /* software reset */ 845 846 switch(sc->sc_vendor) { 847 case PCI_VENDOR_ATI: 848 /* both ATI boards with DTV are the same */ 849 bus_space_write_4(sc->sc_memt, sc->sc_memh, 850 CXDTV_TS_GEN_CONTROL, IPB_SW_RST); 851 delay(100); 852 /* parallel MPEG port */ 853 bus_space_write_4(sc->sc_memt, sc->sc_memh, 854 CXDTV_PINMUX_IO, MPEG_PAR_EN); 855 break; 856 case PCI_VENDOR_PCHDTV: 857 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 858 bus_space_write_4(sc->sc_memt, sc->sc_memh, 859 CXDTV_TS_GEN_CONTROL, IPB_SW_RST|IPB_SMODE); 860 delay(100); 861 bus_space_write_4(sc->sc_memt, sc->sc_memh, 862 CXDTV_PINMUX_IO, 0x00); /* serial MPEG port */ 863 /* byte-width start-of-packet */ 864 bus_space_write_4(sc->sc_memt, sc->sc_memh, 865 CXDTV_HW_SOP_CONTROL, 866 0x47 << 16 | 188 << 4 | 1); 867 bus_space_write_4(sc->sc_memt, sc->sc_memh, 868 CXDTV_TS_SOP_STATUS, IPB_SOP_BYTEWIDE); 869 /* serial MPEG port on HD5500 */ 870 bus_space_write_4(sc->sc_memt, sc->sc_memh, 871 CXDTV_TS_GEN_CONTROL, IPB_SMODE); 872 } 873 break; 874 default: 875 break; 876 } 877 878 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_LNGTH, 879 CXDTV_TS_PKTSIZE); 880 881 /* Configure for standard MPEG TS, 1 good packet to sync */ 882 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_HW_SOP_CONTROL, 883 0x47 << 16 | 188 << 4 | 1); 884 885 /* zero counter */ 886 bus_space_write_4(sc->sc_memt, sc->sc_memh, 887 CXDTV_TS_GP_CNT_CNTRL, 0x03); 888 889 /* enable bad packet interrupt */ 890 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_BD_PKT_STATUS, 891 0x1000); 892 893 /* enable overflow counter */ 894 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_FIFO_OVFL_STAT, 895 0x1000); 896 897 /* unmask TS interrupt */ 898 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 899 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 900 v | CXT_PI_TS_INT); 901 902 /* unmask all TS interrupts */ 903 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 904 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 905 v | 0x1f1011); 906 907 /* enable RISC DMA engine */ 908 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2); 909 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 910 v | CXDTV_DEV_CNTRL2_RUN_RISC); 911 912 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 913 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 914 v | CXDTV_TS_RISC_EN | CXDTV_TS_FIFO_EN); 915 916 return 0; 917 } 918 919 int 920 cxdtv_mpeg_halt(struct cxdtv_softc *sc) 921 { 922 uint32_t v; 923 924 CX_DPRINTF(("cxdtv_mpeg_halt\n")); 925 926 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 927 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 928 v & ~(CXDTV_TS_RISC_EN|CXDTV_TS_FIFO_EN)); 929 930 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 931 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 932 v & ~CXT_PI_TS_INT); 933 934 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 935 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 936 v & ~0x1f1011); 937 938 return 0; 939 } 940 941 int 942 cxdtv_mpeg_intr(struct cxdtv_softc *sc) 943 { 944 struct dtv_payload payload; 945 uint32_t s, m; 946 947 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT); 948 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 949 if ((s & m) == 0) 950 return 0; 951 952 if ( (s & ~CXDTV_TS_RISCI) != 0 ) 953 device_printf(sc->sc_dev, "unexpected TS IS %08x\n", s); 954 955 if (sc->sc_dtvsubmitcb == NULL) 956 goto done; 957 958 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 959 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 960 0, CXDTV_TS_PKTSIZE, 961 BUS_DMASYNC_POSTREAD); 962 payload.data = KERNADDR(sc->sc_dma); 963 payload.size = CXDTV_TS_PKTSIZE; 964 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 965 } 966 967 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 968 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 969 CXDTV_TS_PKTSIZE, CXDTV_TS_PKTSIZE, 970 BUS_DMASYNC_POSTREAD); 971 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CXDTV_TS_PKTSIZE; 972 payload.size = CXDTV_TS_PKTSIZE; 973 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 974 } 975 976 done: 977 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, s); 978 979 return 1; 980 } 981 982 static int 983 cxdtv_allocmem(struct cxdtv_softc *sc, size_t size, size_t align, 984 struct cxdtv_dma *p) 985 { 986 int err; 987 988 p->size = size; 989 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 990 p->segs, __arraycount(p->segs), 991 &p->nsegs, BUS_DMA_NOWAIT); 992 if (err) 993 return err; 994 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 995 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 996 if (err) 997 goto free; 998 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 999 BUS_DMA_NOWAIT, &p->map); 1000 if (err) 1001 goto unmap; 1002 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 1003 BUS_DMA_NOWAIT); 1004 if (err) 1005 goto destroy; 1006 1007 return 0; 1008 1009 destroy: 1010 bus_dmamap_destroy(sc->sc_dmat, p->map); 1011 unmap: 1012 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1013 free: 1014 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1015 1016 return err; 1017 } 1018 1019 static int 1020 cxdtv_freemem(struct cxdtv_softc *sc, struct cxdtv_dma *p) 1021 { 1022 1023 bus_dmamap_unload(sc->sc_dmat, p->map); 1024 bus_dmamap_destroy(sc->sc_dmat, p->map); 1025 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1026 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1027 1028 return 0; 1029 } 1030 1031 void * 1032 cxdtv_mpeg_malloc(struct cxdtv_softc *sc, size_t size) 1033 { 1034 struct cxdtv_dma *p; 1035 int err; 1036 1037 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1038 err = cxdtv_allocmem(sc, size, 16, p); 1039 if (err) { 1040 kmem_free(p, sizeof(*p)); 1041 device_printf(sc->sc_dev, "not enough memory\n"); 1042 return NULL; 1043 } 1044 1045 p->next = sc->sc_dma; 1046 sc->sc_dma = p; 1047 1048 return KERNADDR(p); 1049 } 1050 1051 static void 1052 cxdtv_mpeg_free(struct cxdtv_softc *sc, void *addr) 1053 { 1054 struct cxdtv_dma *p; 1055 struct cxdtv_dma **pp; 1056 1057 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) { 1058 if (KERNADDR(p) == addr) { 1059 cxdtv_freemem(sc, p); 1060 *pp = p->next; 1061 kmem_free(p, sizeof(*p)); 1062 return; 1063 } 1064 } 1065 1066 device_printf(sc->sc_dev, "%p is already free\n", addr); 1067 1068 return; 1069 } 1070 1071 1072 /* ATI HDTV Wonder */ 1073 static void 1074 cxdtv_card_init_hdtvwonder(struct cxdtv_softc *sc) 1075 { 1076 int i, x; 1077 i2c_addr_t na; 1078 uint8_t nb[5][2] = { 1079 {0x10, 0x12}, {0x13, 0x04}, {0x16, 0x00}, 1080 {0x14, 0x04}, {0x17, 0x00} 1081 }; 1082 1083 /* prepare TUV1236D/TU1236F NIM */ 1084 1085 na = 0x0a; /* Nxt2004 address */ 1086 x = 0; 1087 1088 iic_acquire_bus(&sc->sc_i2c, 0); 1089 1090 for(i = 0; i < 5; i++) 1091 x |= iic_exec(&sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, na, 1092 nb[i], 2, NULL, 0, 0); 1093 1094 iic_release_bus(&sc->sc_i2c, 0); 1095 1096 if (x) 1097 aprint_error_dev(sc->sc_dev, "HDTV Wonder tuner init failed"); 1098 } 1099 1100 /* pcHDTV HD5500 */ 1101 #define cxdtv_write_field(_mask, _shift, _value) \ 1102 (((_value) & (_mask)) << (_shift)) 1103 1104 static void 1105 cxdtv_write_gpio(struct cxdtv_softc *sc, uint32_t mask, uint32_t value) 1106 { 1107 uint32_t v = 0; 1108 v |= cxdtv_write_field(0xff, 16, mask); 1109 v |= cxdtv_write_field(0xff, 8, mask); 1110 v |= cxdtv_write_field(0xff, 0, (mask & value)); 1111 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_GP0_IO, v); 1112 } 1113 1114 static void 1115 cxdtv_card_init_hd5500(struct cxdtv_softc *sc) 1116 { 1117 /* hardware (demod) reset */ 1118 cxdtv_write_gpio(sc, 1, 0); 1119 delay(100000); 1120 cxdtv_write_gpio(sc, 1, 1); 1121 delay(200000); 1122 } 1123 1124 MODULE(MODULE_CLASS_DRIVER, cxdtv, "tvpll,nxt2k,lg3303,pci"); 1125 1126 #ifdef _MODULE 1127 #include "ioconf.c" 1128 #endif 1129 1130 static int 1131 cxdtv_modcmd(modcmd_t cmd, void *opaque) 1132 { 1133 switch (cmd) { 1134 case MODULE_CMD_INIT: 1135 #ifdef _MODULE 1136 return config_init_component(cfdriver_ioconf_cxdtv, 1137 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1138 #else 1139 return 0; 1140 #endif 1141 case MODULE_CMD_FINI: 1142 #ifdef _MODULE 1143 return config_fini_component(cfdriver_ioconf_cxdtv, 1144 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1145 #else 1146 return 0; 1147 #endif 1148 default: 1149 return ENOTTY; 1150 } 1151 } 1152
Indexes created Fri Oct 03 02:09:57 GMT 2025