cxdtv.c revision 1.4
1 /* $NetBSD: cxdtv.c,v 1.4 2011/07/15 03:35:13 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.4 2011/07/15 03:35:13 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/condvar.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_bitbang.h> 46 47 #include <dev/i2c/tvpllvar.h> 48 #include <dev/i2c/tvpll_tuners.h> 49 50 #include <dev/i2c/nxt2kvar.h> 51 #include <dev/i2c/lg3303var.h> 52 53 #include <dev/pci/cxdtvreg.h> 54 #include <dev/pci/cxdtvvar.h> 55 #include <dev/pci/cxdtv_boards.h> 56 57 #include <dev/dtv/dtvif.h> 58 59 #define CXDTV_MMBASE 0x10 60 61 #define CXDTV_SRAM_CH_MPEG 0 62 #define CXDTV_TS_PKTSIZE (188 * 8) 63 64 static int cxdtv_match(struct device *, struct cfdata *, void *); 65 static void cxdtv_attach(struct device *, struct device *, void *); 66 static int cxdtv_detach(struct device *, int); 67 static void cxdtv_childdet(struct device *, struct device *); 68 static int cxdtv_intr(void *); 69 70 static bool cxdtv_resume(device_t, const pmf_qual_t *); 71 72 static int cxdtv_iic_acquire_bus(void *, int); 73 static void cxdtv_iic_release_bus(void *, int); 74 static int cxdtv_iic_send_start(void *, int); 75 static int cxdtv_iic_send_stop(void *, int); 76 static int cxdtv_iic_initiate_xfer(void *, i2c_addr_t, int); 77 static int cxdtv_iic_read_byte(void *, uint8_t *, int); 78 static int cxdtv_iic_write_byte(void *, uint8_t, int); 79 80 static void cxdtv_i2cbb_set_bits(void *, uint32_t); 81 static void cxdtv_i2cbb_set_dir(void *, uint32_t); 82 static uint32_t cxdtv_i2cbb_read_bits(void *); 83 84 static int cxdtv_sram_ch_setup(struct cxdtv_softc *, 85 struct cxdtv_sram_ch *, uint32_t); 86 static int cxdtv_allocmem(struct cxdtv_softc *, size_t, size_t, 87 struct cxdtv_dma *); 88 static int cxdtv_freemem(struct cxdtv_softc *, struct cxdtv_dma *); 89 static int cxdtv_risc_buffer(struct cxdtv_softc *, uint32_t, uint32_t); 90 static int cxdtv_risc_field(struct cxdtv_softc *, uint32_t *, uint32_t); 91 92 static int cxdtv_mpeg_attach(struct cxdtv_softc *); 93 static int cxdtv_mpeg_detach(struct cxdtv_softc *, int flags); 94 static int cxdtv_mpeg_intr(struct cxdtv_softc *); 95 static int cxdtv_mpeg_reset(struct cxdtv_softc *); 96 97 static int cxdtv_mpeg_trigger(struct cxdtv_softc *, void *); 98 static int cxdtv_mpeg_halt(struct cxdtv_softc *); 99 static void * cxdtv_mpeg_malloc(struct cxdtv_softc *, size_t); 100 static void cxdtv_mpeg_free(struct cxdtv_softc *, void *); 101 102 static void cxdtv_card_init_hd5500(struct cxdtv_softc *); 103 static void cxdtv_card_init_hdtvwonder(struct cxdtv_softc *); 104 105 const struct i2c_bitbang_ops cxdtv_i2cbb_ops = { 106 cxdtv_i2cbb_set_bits, 107 cxdtv_i2cbb_set_dir, 108 cxdtv_i2cbb_read_bits, 109 { CXDTV_I2C_C_DATACONTROL_SDA, CXDTV_I2C_C_DATACONTROL_SCL, 0, 0 } 110 }; 111 112 /* Maybe make this dynamically allocated. */ 113 static struct cxdtv_sram_ch cxdtv_sram_chs[] = { 114 [CXDTV_SRAM_CH_MPEG] = { 115 .csc_cmds = 0x180200, /* CMDS for ch. 28 */ 116 .csc_iq = 0x180340, /* after last CMDS */ 117 .csc_iqsz = 0x40, /* 16 dwords */ 118 .csc_cdt = 0x180380, /* after iq */ 119 .csc_cdtsz = 0x40, /* cluster discriptor space */ 120 .csc_fifo = 0x180400, /* after cdt */ 121 .csc_fifosz = 0x001C00, /* let's just align this up */ 122 .csc_risc = 0x182000, /* after fifo */ 123 .csc_riscsz = 0x6000, /* room for dma programs */ 124 .csc_ptr1 = CXDTV_DMA28_PTR1, 125 .csc_ptr2 = CXDTV_DMA28_PTR2, 126 .csc_cnt1 = CXDTV_DMA28_CNT1, 127 .csc_cnt2 = CXDTV_DMA28_CNT2, 128 }, 129 }; 130 131 CFATTACH_DECL2_NEW(cxdtv, sizeof(struct cxdtv_softc), 132 cxdtv_match, cxdtv_attach, cxdtv_detach, NULL, NULL, cxdtv_childdet); 133 134 static int 135 cxdtv_match(device_t parent, cfdata_t match, void *aux) 136 { 137 const struct pci_attach_args *pa; 138 139 pa = aux; 140 141 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 142 return 0; 143 144 switch (PCI_PRODUCT(pa->pa_id)) { 145 case PCI_PRODUCT_CONEXANT_CX2388XMPEG: 146 return 1; 147 } 148 149 /* XXX only match supported boards */ 150 151 return 0; 152 } 153 154 static void 155 cxdtv_attach(device_t parent, device_t self, void *aux) 156 { 157 struct cxdtv_softc *sc; 158 const struct pci_attach_args *pa = aux; 159 pci_intr_handle_t ih; 160 pcireg_t reg; 161 const char *intrstr; 162 char devinfo[76]; 163 struct i2cbus_attach_args iba; 164 165 sc = device_private(self); 166 167 sc->sc_dev = self; 168 sc->sc_pc = pa->pa_pc; 169 170 aprint_naive("\n"); 171 172 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 173 174 sc->sc_vendor = PCI_VENDOR(reg); 175 sc->sc_product = PCI_PRODUCT(reg); 176 177 sc->sc_board = cxdtv_board_lookup(sc->sc_vendor, sc->sc_product); 178 179 if (sc->sc_board == NULL) { 180 aprint_error_dev(self ,"unsupported device 0x%08x\n", reg); 181 return; 182 } 183 184 pci_devinfo(reg, pa->pa_class, 0, devinfo, sizeof(devinfo)); 185 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 186 187 if (pci_mapreg_map(pa, CXDTV_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 188 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 189 aprint_error_dev(self, "couldn't map memory space\n"); 190 return; 191 } 192 193 sc->sc_dmat = pa->pa_dmat; 194 195 if (pci_intr_map(pa, &ih)) { 196 aprint_error_dev(self, "couldn't map interrupt\n"); 197 return; 198 } 199 intrstr = pci_intr_string(pa->pa_pc, ih); 200 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM, cxdtv_intr, sc); 201 if (sc->sc_ih == NULL) { 202 aprint_error_dev(self, "couldn't establish interrupt"); 203 if (intrstr != NULL) 204 aprint_error(" at %s", intrstr); 205 aprint_error("\n"); 206 return; 207 } 208 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 209 210 /* set master */ 211 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 212 reg |= PCI_COMMAND_MASTER_ENABLE; 213 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 214 215 mutex_init(&sc->sc_delaylock, MUTEX_DEFAULT, IPL_NONE); 216 cv_init(&sc->sc_delaycv, "cxdtvwait"); 217 218 mutex_init(&sc->sc_i2c_buslock, MUTEX_DRIVER, IPL_NONE); 219 sc->sc_i2c.ic_cookie = sc; 220 sc->sc_i2c.ic_exec = NULL; 221 sc->sc_i2c.ic_acquire_bus = cxdtv_iic_acquire_bus; 222 sc->sc_i2c.ic_release_bus = cxdtv_iic_release_bus; 223 sc->sc_i2c.ic_send_start = cxdtv_iic_send_start; 224 sc->sc_i2c.ic_send_stop = cxdtv_iic_send_stop; 225 sc->sc_i2c.ic_initiate_xfer = cxdtv_iic_initiate_xfer; 226 sc->sc_i2c.ic_read_byte = cxdtv_iic_read_byte; 227 sc->sc_i2c.ic_write_byte = cxdtv_iic_write_byte; 228 229 #if notyet 230 /* enable i2c compatible software mode */ 231 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, 232 CXDTV_I2C_C_DATACONTROL); 233 val = CXDTV_I2C_C_DATACONTROL_SCL | CXDTV_I2C_C_DATACONTROL_SDA; 234 bus_space_write_4(sc->sc_memt, sc->sc_memh, 235 CXDTV_I2C_C_DATACONTROL, val); 236 #endif 237 238 cxdtv_mpeg_attach(sc); 239 240 /* attach other devices to iic(4) */ 241 memset(&iba, 0, sizeof(iba)); 242 iba.iba_tag = &sc->sc_i2c; 243 config_found_ia(self, "i2cbus", &iba, iicbus_print); 244 245 if (!pmf_device_register(self, NULL, cxdtv_resume)) 246 aprint_error_dev(self, "couldn't establish power handler\n"); 247 248 return; 249 } 250 251 static int 252 cxdtv_detach(device_t self, int flags) 253 { 254 struct cxdtv_softc *sc = device_private(self); 255 int error; 256 257 error = cxdtv_mpeg_detach(sc, flags); 258 if (error) 259 return error; 260 261 if (sc->sc_ih) 262 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 263 264 if (sc->sc_mems) 265 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 266 267 mutex_destroy(&sc->sc_i2c_buslock); 268 mutex_destroy(&sc->sc_delaylock); 269 cv_destroy(&sc->sc_delaycv); 270 271 return 0; 272 } 273 274 static void 275 cxdtv_childdet(device_t self, device_t child) 276 { 277 struct cxdtv_softc *sc = device_private(self); 278 279 if (child == sc->sc_dtvdev) 280 sc->sc_dtvdev = NULL; 281 } 282 283 static bool 284 cxdtv_resume(device_t dv, const pmf_qual_t *qual) 285 { 286 struct cxdtv_softc *sc; 287 sc = device_private(dv); 288 289 /* XXX revisit */ 290 291 aprint_debug_dev(dv, "%s\n", __func__); 292 293 return true; 294 } 295 296 static int 297 cxdtv_intr(void *intarg) 298 { 299 struct cxdtv_softc *sc = intarg; 300 uint32_t val; 301 302 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MSTAT); 303 if (val == 0) { 304 return 0; /* not ours */ 305 } 306 307 if (val & CXT_PI_TS_INT) { 308 cxdtv_mpeg_intr(sc); 309 } 310 311 if (val & ~CXT_PI_TS_INT) { 312 device_printf(sc->sc_dev, "%s, %08x\n", __func__, val); 313 } 314 315 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, val); 316 317 return 1; 318 } 319 320 /* I2C interface */ 321 322 static void 323 cxdtv_i2cbb_set_bits(void *cookie, uint32_t bits) 324 { 325 struct cxdtv_softc *sc = cookie; 326 uint32_t value; 327 328 bus_space_write_4(sc->sc_memt, sc->sc_memh, 329 CXDTV_I2C_C_DATACONTROL, bits); 330 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 331 CXDTV_I2C_C_DATACONTROL); 332 333 return; 334 } 335 336 static void 337 cxdtv_i2cbb_set_dir(void *cookie, uint32_t bits) 338 { 339 return; 340 } 341 342 static uint32_t 343 cxdtv_i2cbb_read_bits(void *cookie) 344 { 345 struct cxdtv_softc *sc = cookie; 346 uint32_t value; 347 348 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 349 CXDTV_I2C_C_DATACONTROL); 350 351 return value; 352 } 353 354 static int 355 cxdtv_iic_acquire_bus(void *cookie, int flags) 356 { 357 struct cxdtv_softc *sc = cookie; 358 359 mutex_enter(&sc->sc_i2c_buslock); 360 361 return 0; 362 } 363 364 static void 365 cxdtv_iic_release_bus(void *cookie, int flags) 366 { 367 struct cxdtv_softc *sc = cookie; 368 369 mutex_exit(&sc->sc_i2c_buslock); 370 371 return; 372 } 373 374 static int 375 cxdtv_iic_send_start(void *cookie, int flags) 376 { 377 return i2c_bitbang_send_start(cookie, flags, &cxdtv_i2cbb_ops); 378 } 379 380 static int 381 cxdtv_iic_send_stop(void *cookie, int flags) 382 { 383 return i2c_bitbang_send_stop(cookie, flags, &cxdtv_i2cbb_ops); 384 } 385 386 static int 387 cxdtv_iic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 388 { 389 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &cxdtv_i2cbb_ops); 390 } 391 392 static int 393 cxdtv_iic_read_byte(void *cookie, uint8_t *data, int flags) 394 { 395 return i2c_bitbang_read_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 396 } 397 398 static int 399 cxdtv_iic_write_byte(void *cookie, uint8_t data, int flags) 400 { 401 return i2c_bitbang_write_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 402 } 403 404 /* MPEG TS Port */ 405 406 static void cxdtv_dtv_get_devinfo(void *, struct dvb_frontend_info *); 407 static int cxdtv_dtv_open(void *, int); 408 static void cxdtv_dtv_close(void *); 409 static int cxdtv_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 410 static fe_status_t cxdtv_dtv_get_status(void *); 411 static uint16_t cxdtv_dtv_get_signal_strength(void *); 412 static uint16_t cxdtv_dtv_get_snr(void *); 413 static int cxdtv_dtv_start_transfer(void *); 414 static int cxdtv_dtv_stop_transfer(void *); 415 416 static const struct dtv_hw_if cxdtv_dtv_if = { 417 .get_devinfo = cxdtv_dtv_get_devinfo, 418 .open = cxdtv_dtv_open, 419 .close = cxdtv_dtv_close, 420 .set_tuner = cxdtv_dtv_set_tuner, 421 .get_status = cxdtv_dtv_get_status, 422 .get_signal_strength = cxdtv_dtv_get_signal_strength, 423 .get_snr = cxdtv_dtv_get_snr, 424 .start_transfer = cxdtv_dtv_start_transfer, 425 .stop_transfer = cxdtv_dtv_stop_transfer, 426 }; 427 428 int 429 cxdtv_mpeg_attach(struct cxdtv_softc *sc) 430 { 431 struct dtv_attach_args daa; 432 struct cxdtv_sram_ch *ch; 433 434 CX_DPRINTF(("cxdtv_mpeg_attach\n")); 435 436 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 437 438 sc->sc_riscbufsz = ch->csc_riscsz; 439 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 440 441 if ( sc->sc_riscbuf == NULL ) 442 panic("riscbuf null"); 443 444 aprint_debug_dev(sc->sc_dev, "attaching frontend...\n"); 445 446 switch(sc->sc_vendor) { 447 case PCI_VENDOR_ATI: 448 cxdtv_card_init_hdtvwonder(sc); 449 break; 450 case PCI_VENDOR_PCHDTV: 451 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 452 cxdtv_card_init_hd5500(sc); 453 } 454 break; 455 } 456 457 KASSERT(sc->sc_tuner == NULL); 458 KASSERT(sc->sc_demod == NULL); 459 460 switch(sc->sc_board->cb_demod) { 461 case CXDTV_DEMOD_NXT2004: 462 sc->sc_demod = nxt2k_open(sc->sc_dev, &sc->sc_i2c, 0x0a, 0); 463 break; 464 case CXDTV_DEMOD_LG3303: 465 sc->sc_demod = lg3303_open(sc->sc_dev, &sc->sc_i2c, 0x59, 466 LG3303_CFG_SERIAL_INPUT); 467 break; 468 default: 469 break; 470 } 471 472 switch(sc->sc_board->cb_tuner) { 473 case CXDTV_TUNER_PLL: 474 if (sc->sc_vendor == PCI_VENDOR_ATI) 475 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tuv1236d_pll); 476 if (sc->sc_vendor == PCI_VENDOR_PCHDTV) 477 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tdvs_h06xf_pll); 478 break; 479 default: 480 break; 481 } 482 483 KASSERT(sc->sc_tuner != NULL); 484 KASSERT(sc->sc_demod != NULL); 485 486 daa.hw = &cxdtv_dtv_if; 487 daa.priv = sc; 488 489 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", &daa, dtv_print); 490 491 return (sc->sc_dtvdev != NULL); 492 } 493 494 int 495 cxdtv_mpeg_detach(struct cxdtv_softc *sc, int flags) 496 { 497 int error = 0; 498 499 if (sc->sc_dtvdev) { 500 error = config_detach(sc->sc_dtvdev, flags); 501 if (error) 502 return error; 503 } 504 505 if (sc->sc_demod) { 506 switch (sc->sc_board->cb_demod) { 507 case CXDTV_DEMOD_NXT2004: 508 nxt2k_close(sc->sc_demod); 509 break; 510 case CXDTV_DEMOD_LG3303: 511 lg3303_close(sc->sc_demod); 512 break; 513 default: 514 break; 515 } 516 sc->sc_demod = NULL; 517 } 518 if (sc->sc_tuner) { 519 switch (sc->sc_board->cb_tuner) { 520 case CXDTV_TUNER_PLL: 521 tvpll_close(sc->sc_tuner); 522 break; 523 default: 524 break; 525 } 526 sc->sc_tuner = NULL; 527 } 528 529 if (sc->sc_riscbuf) { 530 kmem_free(sc->sc_riscbuf, sc->sc_riscbufsz); 531 sc->sc_riscbuf = NULL; 532 sc->sc_riscbufsz = 0; 533 } 534 535 return error; 536 } 537 538 static void 539 cxdtv_dtv_get_devinfo(void *priv, struct dvb_frontend_info *info) 540 { 541 memset(info, 0, sizeof(*info)); 542 strlcpy(info->name, "CX23880", sizeof(info->name)); 543 info->type = FE_ATSC; 544 info->frequency_min = 54000000; 545 info->frequency_max = 858000000; 546 info->frequency_stepsize = 62500; 547 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 548 } 549 550 static int 551 cxdtv_dtv_open(void *priv, int flags) 552 { 553 struct cxdtv_softc *sc = priv; 554 555 KASSERT(sc->sc_tsbuf == NULL); 556 557 cxdtv_mpeg_reset(sc); 558 559 printf("sc_dma %p\n", sc->sc_dma); 560 printf("sc_tsbuf %p\n", sc->sc_tsbuf); 561 /* allocate two alternating DMA areas for MPEG TS packets */ 562 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 563 printf("sc_dma %p\n", sc->sc_dma); 564 printf("sc_tsbuf %p\n", sc->sc_tsbuf); 565 566 if (sc->sc_tsbuf == NULL) 567 return EIO; 568 569 return 0; 570 } 571 572 static void 573 cxdtv_dtv_close(void *priv) 574 { 575 struct cxdtv_softc *sc = priv; 576 577 cxdtv_dtv_stop_transfer(sc); 578 579 if (sc->sc_tsbuf != NULL) { 580 cxdtv_mpeg_free(sc, sc->sc_tsbuf); 581 sc->sc_tsbuf = NULL; 582 } 583 } 584 585 static int 586 cxdtv_dtv_set_tuner(void *priv, const struct dvb_frontend_parameters *params) 587 { 588 struct cxdtv_softc *sc = priv; 589 int error = -1; 590 591 switch(sc->sc_board->cb_tuner) { 592 case CXDTV_TUNER_PLL: 593 error = tvpll_tune_dtv(sc->sc_tuner, params); 594 } 595 if (error) 596 goto bad; 597 598 switch(sc->sc_board->cb_demod) { 599 case CXDTV_DEMOD_NXT2004: 600 error = nxt2k_set_modulation(sc->sc_demod, params->u.vsb.modulation); 601 break; 602 case CXDTV_DEMOD_LG3303: 603 error = lg3303_set_modulation(sc->sc_demod, params->u.vsb.modulation); 604 break; 605 default: 606 break; 607 } 608 609 bad: 610 return error; 611 } 612 613 static fe_status_t 614 cxdtv_dtv_get_status(void *priv) 615 { 616 struct cxdtv_softc *sc = priv; 617 618 switch(sc->sc_board->cb_demod) { 619 case CXDTV_DEMOD_NXT2004: 620 return nxt2k_get_dtv_status(sc->sc_demod); 621 case CXDTV_DEMOD_LG3303: 622 return lg3303_get_dtv_status(sc->sc_demod); 623 default: 624 return 0; 625 } 626 } 627 628 static uint16_t 629 cxdtv_dtv_get_signal_strength(void *priv) 630 { 631 return 27; 632 } 633 634 static uint16_t 635 cxdtv_dtv_get_snr(void *priv) 636 { 637 return 42; 638 } 639 640 static int 641 cxdtv_dtv_start_transfer(void *priv) 642 { 643 struct cxdtv_softc *sc = priv; 644 645 printf("sc_dma %p\n", sc->sc_dma); 646 printf("sc_tsbuf %p\n", sc->sc_tsbuf); 647 /* allocate two alternating DMA areas for MPEG TS packets */ 648 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 649 printf("sc_dma %p\n", sc->sc_dma); 650 printf("sc_tsbuf %p\n", sc->sc_tsbuf); 651 652 printf("KERNADDR %p, DMAADDR %016lx\n", KERNADDR(sc->sc_dma), DMAADDR(sc->sc_dma)); 653 654 cxdtv_mpeg_trigger(sc, sc->sc_tsbuf); 655 656 return 0; 657 } 658 659 static int 660 cxdtv_dtv_stop_transfer(void *priv) 661 { 662 struct cxdtv_softc *sc = priv; 663 664 cxdtv_mpeg_halt(sc); 665 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 666 667 return 0; 668 } 669 670 int 671 cxdtv_mpeg_reset(struct cxdtv_softc *sc) 672 { 673 struct cxdtv_sram_ch *ch; 674 uint32_t v; 675 676 CX_DPRINTF(("cxdtv_mpeg_reset\n")); 677 678 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 679 v = (uint32_t)-1; 680 681 /* shutdown */ 682 /* hold RISC in reset */ 683 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 0); 684 /* disable FIFO and RISC */ 685 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 0); 686 /* mask off all interrupts */ 687 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 688 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 0); 689 690 /* clear interrupts */ 691 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, v); 692 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, v); 693 694 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 695 696 /* XXX magic */ 697 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_STHRSH, 0x0707); 698 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_DTHRSH, 0x0707); 699 700 /* reset external components*/ 701 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 0); 702 mutex_enter(&sc->sc_delaylock); 703 cv_timedwait(&sc->sc_delaycv, &sc->sc_delaylock, MAX(1, mstohz(1))); 704 mutex_exit(&sc->sc_delaylock); 705 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 1); 706 707 /* let error interrupts happen */ 708 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 709 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 710 v | 0x00fc00); /* XXX magic */ 711 712 return 0; 713 } 714 715 static int 716 cxdtv_risc_buffer(struct cxdtv_softc *sc, uint32_t bpl, uint32_t lines) 717 { 718 uint32_t *rm; 719 uint32_t size; 720 721 CX_DPRINTF(("cxdtv_risc_buffer: bpl=0x%x\n", bpl)); 722 723 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 724 size += 2; 725 726 device_printf(sc->sc_dev, "%s: est. inst. %d\n", __func__, size); 727 728 size *= 8; 729 device_printf(sc->sc_dev, "%s: est. qword %d\n", __func__, size); 730 731 if (sc->sc_riscbuf == NULL) { 732 device_printf(sc->sc_dev, "not enough memory for RISC\n"); 733 return ENOMEM; 734 } 735 736 rm = (uint32_t *)sc->sc_riscbuf; 737 cxdtv_risc_field(sc, rm, bpl); 738 739 return 0; 740 } 741 742 static int 743 cxdtv_risc_field(struct cxdtv_softc *sc, uint32_t *rm, uint32_t bpl) 744 { 745 struct cxdtv_dma *p; 746 747 CX_DPRINTF(("cxdtv_risc_field: bpl=0x%x\n", bpl)); 748 749 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 750 continue; 751 if (p == NULL) { 752 device_printf(sc->sc_dev, "cxdtv_risc_field: bad addr %p\n", 753 sc->sc_tsbuf); 754 return ENOENT; 755 } 756 757 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 758 759 rm = sc->sc_riscbuf; 760 761 /* htole32 will be done when program is copied to chip sram */ 762 763 /* XXX */ 764 *(rm++) = (CX_RISC_SYNC|0); 765 766 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 767 *(rm++) = (DMAADDR(p) + 0 * bpl); 768 769 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 770 *(rm++) = (DMAADDR(p) + 1 * bpl); 771 772 *(rm++) = (CX_RISC_JUMP|1); 773 *(rm++) = (cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG].csc_risc + 4); 774 775 return 0; 776 } 777 778 static int 779 cxdtv_sram_ch_setup(struct cxdtv_softc *sc, struct cxdtv_sram_ch *csc, 780 uint32_t bpl) 781 { 782 unsigned int i, lines; 783 uint32_t cdt; 784 785 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 786 787 /* XXX why round? */ 788 bpl = (bpl + 7) & ~7; 789 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 790 cdt = csc->csc_cdt; 791 lines = csc->csc_fifosz / bpl; 792 device_printf(sc->sc_dev, "%s %d lines\n", __func__, lines); 793 794 /* fill in CDT */ 795 for (i = 0; i < lines; i++) { 796 CX_DPRINTF(("CDT ent %08x, %08x\n", cdt + (16 * i), 797 csc->csc_fifo + (bpl * i))); 798 bus_space_write_4(sc->sc_memt, sc->sc_memh, 799 cdt + (16 * i), 800 csc->csc_fifo + (bpl * i)); 801 } 802 803 /* copy DMA program */ 804 805 /* converts program to little endian as it goes into SRAM */ 806 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 807 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 808 809 /* fill in CMDS */ 810 bus_space_write_4(sc->sc_memt, sc->sc_memh, 811 csc->csc_cmds + CX_CMDS_O_IRPC, csc->csc_risc); 812 813 bus_space_write_4(sc->sc_memt, sc->sc_memh, 814 csc->csc_cmds + CX_CMDS_O_CDTB, csc->csc_cdt); 815 bus_space_write_4(sc->sc_memt, sc->sc_memh, 816 csc->csc_cmds + CX_CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 817 818 bus_space_write_4(sc->sc_memt, sc->sc_memh, 819 csc->csc_cmds + CX_CMDS_O_IQB, csc->csc_iq); 820 bus_space_write_4(sc->sc_memt, sc->sc_memh, 821 csc->csc_cmds + CX_CMDS_O_IQS, 822 CX_CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 823 824 /* zero rest of CMDS */ 825 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x14, 0, 0x2c/4); 826 827 bus_space_write_4(sc->sc_memt, sc->sc_memh, 828 csc->csc_cnt1, (bpl >> 3) - 1); 829 830 bus_space_write_4(sc->sc_memt, sc->sc_memh, 831 csc->csc_ptr2, cdt); 832 bus_space_write_4(sc->sc_memt, sc->sc_memh, 833 csc->csc_cnt2, (lines * 16) >> 3); 834 835 return 0; 836 } 837 838 int 839 cxdtv_mpeg_trigger(struct cxdtv_softc *sc, void *buf) 840 { 841 struct cxdtv_dma *p; 842 struct cxdtv_sram_ch *ch; 843 uint32_t v; 844 uint32_t offset; 845 846 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 847 848 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 849 continue; 850 if (p == NULL) { 851 device_printf(sc->sc_dev, "cxdtv_mpeg_trigger: bad addr %p\n", 852 buf); 853 return ENOENT; 854 } 855 856 CX_DPRINTF(("cxdtv_mpeg_trigger: buf=%p\n", buf)); 857 858 cxdtv_risc_buffer(sc, CXDTV_TS_PKTSIZE, 1); 859 cxdtv_sram_ch_setup(sc, ch, CXDTV_TS_PKTSIZE); 860 861 /* software reset */ 862 863 /* serial MPEG port on HD5500 */ 864 switch(sc->sc_vendor) { 865 case PCI_VENDOR_ATI: 866 /* both ATI boards with DTV are the same */ 867 bus_space_write_4(sc->sc_memt, sc->sc_memh, 868 CXDTV_TS_GEN_CONTROL, 0x40); 869 delay(100); 870 /* parallel MPEG port */ 871 bus_space_write_4(sc->sc_memt, sc->sc_memh, 872 CXDTV_PINMUX_IO, 0x80); /* XXX bit defines */ 873 break; 874 case PCI_VENDOR_PCHDTV: 875 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 876 bus_space_write_4(sc->sc_memt, sc->sc_memh, 877 CXDTV_TS_GEN_CONTROL, 0x48); 878 delay(100); 879 /* serial MPEG port */ 880 bus_space_write_4(sc->sc_memt, sc->sc_memh, 881 CXDTV_PINMUX_IO, 0x00); /* XXX bit defines */ 882 /* byte-width start-of-packet */ 883 bus_space_write_4(sc->sc_memt, sc->sc_memh, 884 CXDTV_HW_SOP_CONTROL, 885 0x47 << 16 | 188 << 4 | 1); 886 bus_space_write_4(sc->sc_memt, sc->sc_memh, 887 CXDTV_TS_SOP_STATUS, 1 << 13); 888 bus_space_write_4(sc->sc_memt, sc->sc_memh, 889 CXDTV_TS_GEN_CONTROL, 0x08); 890 } 891 break; 892 default: 893 break; 894 } 895 896 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_LNGTH, 897 CXDTV_TS_PKTSIZE); 898 899 /* Configure for standard MPEG TS, 1 good to sync */ 900 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_HW_SOP_CONTROL, 901 0x47 << 16 | 188 << 4 | 1); 902 903 offset = CXDTV_TS_GEN_CONTROL; 904 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, offset); 905 printf("CXDTV_TS_GEN_CONTROL %06x %08x\n", offset, v); 906 907 #if 0 908 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_GEN_CONTROL, 0x00); 909 mutex_enter(&sc->sc_delaylock); 910 cv_timedwait(&sc->sc_delaycv, &sc->sc_delaylock, mstohz(100)); 911 mutex_exit(&sc->sc_delaylock); 912 #endif 913 914 /* zero counter */ 915 bus_space_write_4(sc->sc_memt, sc->sc_memh, 916 CXDTV_TS_GP_CNT_CNTRL, 0x03); 917 918 /* enable bad packet interrupt */ 919 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_BD_PKT_STATUS, 920 0x1000); 921 922 /* enable overflow counter */ 923 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_FIFO_OVFL_STAT, 924 0x1000); 925 926 /* unmask TS interrupt */ 927 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 928 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 929 v | CXT_PI_TS_INT); 930 931 /* unmask all TS interrupts */ 932 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 933 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 934 v | 0x1f1011); 935 936 /* enable RISC DMA engine */ 937 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2); 938 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 939 v | CXDTV_DEV_CNTRL2_RUN_RISC); 940 941 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 942 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 943 v | CXDTV_TS_RISC_EN | CXDTV_TS_FIFO_EN); 944 945 #if 0 946 mutex_enter(&sc->sc_delaylock); 947 cv_timedwait(&sc->sc_delaycv, &sc->sc_delaylock, mstohz(1000)); 948 mutex_exit(&sc->sc_delaylock); 949 950 for(offset = 0x33c040; offset < 0x33c064; offset += 4) { 951 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, offset); 952 printf("%06x %08x\n", offset, v); 953 } 954 for(offset = 0x200070; offset < 0x200080; offset += 4) { 955 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, offset); 956 printf("%06x %08x\n", offset, v); 957 } 958 #endif 959 960 return 0; 961 } 962 963 int 964 cxdtv_mpeg_halt(struct cxdtv_softc *sc) 965 { 966 uint32_t v; 967 968 CX_DPRINTF(("cxdtv_mpeg_halt\n")); 969 970 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 971 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 972 v & ~(CXDTV_TS_RISC_EN|CXDTV_TS_FIFO_EN)); 973 974 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 975 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 976 v & ~CXT_PI_TS_INT); 977 978 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 979 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 980 v & ~0x1f1011); 981 982 return 0; 983 } 984 985 int 986 cxdtv_mpeg_intr(struct cxdtv_softc *sc) 987 { 988 struct dtv_payload payload; 989 uint32_t s, m; 990 991 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT); 992 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 993 if ((s & m) == 0) 994 return 0; 995 996 if ( (s & ~CXDTV_TS_RISCI) != 0 ) 997 device_printf(sc->sc_dev, "unexpected TS IS %08x\n", s); 998 999 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 1000 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 1001 0, CXDTV_TS_PKTSIZE, 1002 BUS_DMASYNC_POSTREAD); 1003 payload.data = KERNADDR(sc->sc_dma); 1004 payload.size = CXDTV_TS_PKTSIZE; 1005 dtv_submit_payload(sc->sc_dtvdev, &payload); 1006 } 1007 1008 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 1009 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 1010 CXDTV_TS_PKTSIZE, CXDTV_TS_PKTSIZE, 1011 BUS_DMASYNC_POSTREAD); 1012 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CXDTV_TS_PKTSIZE; 1013 payload.size = CXDTV_TS_PKTSIZE; 1014 dtv_submit_payload(sc->sc_dtvdev, &payload); 1015 } 1016 1017 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, s); 1018 1019 return 1; 1020 } 1021 1022 static int 1023 cxdtv_allocmem(struct cxdtv_softc *sc, size_t size, size_t align, 1024 struct cxdtv_dma *p) 1025 { 1026 int err; 1027 1028 p->size = size; 1029 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 1030 p->segs, __arraycount(p->segs), 1031 &p->nsegs, BUS_DMA_NOWAIT); 1032 if (err) 1033 return err; 1034 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 1035 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1036 if (err) 1037 goto free; 1038 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 1039 BUS_DMA_NOWAIT, &p->map); 1040 if (err) 1041 goto unmap; 1042 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 1043 BUS_DMA_NOWAIT); 1044 if (err) 1045 goto destroy; 1046 1047 return 0; 1048 1049 destroy: 1050 bus_dmamap_destroy(sc->sc_dmat, p->map); 1051 unmap: 1052 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1053 free: 1054 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1055 1056 return err; 1057 } 1058 1059 static int 1060 cxdtv_freemem(struct cxdtv_softc *sc, struct cxdtv_dma *p) 1061 { 1062 1063 bus_dmamap_unload(sc->sc_dmat, p->map); 1064 bus_dmamap_destroy(sc->sc_dmat, p->map); 1065 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1066 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1067 1068 return 0; 1069 } 1070 1071 void * 1072 cxdtv_mpeg_malloc(struct cxdtv_softc *sc, size_t size) 1073 { 1074 struct cxdtv_dma *p; 1075 int err; 1076 1077 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1078 if (p == NULL) { 1079 return NULL; 1080 } 1081 1082 err = cxdtv_allocmem(sc, size, 16, p); 1083 if (err) { 1084 kmem_free(p, sizeof(*p)); 1085 device_printf(sc->sc_dev, "not enough memory\n"); 1086 return NULL; 1087 } 1088 1089 p->next = sc->sc_dma; 1090 sc->sc_dma = p; 1091 1092 return KERNADDR(p); 1093 } 1094 1095 static void 1096 cxdtv_mpeg_free(struct cxdtv_softc *sc, void *addr) 1097 { 1098 struct cxdtv_dma *p; 1099 struct cxdtv_dma **pp; 1100 1101 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) { 1102 if (KERNADDR(p) == addr) { 1103 cxdtv_freemem(sc, p); 1104 *pp = p->next; 1105 kmem_free(p, sizeof(*p)); 1106 return; 1107 } 1108 } 1109 1110 device_printf(sc->sc_dev, "%p is already free\n", addr); 1111 1112 return; 1113 } 1114 1115 1116 /* ATI HDTV Wonder */ 1117 static void 1118 cxdtv_card_init_hdtvwonder(struct cxdtv_softc *sc) 1119 { 1120 int i, x; 1121 i2c_addr_t na; 1122 uint8_t nb[5][2] = { 1123 {0x10, 0x12}, {0x13, 0x04}, {0x16, 0x00}, 1124 {0x14, 0x04}, {0x17, 0x00} 1125 }; 1126 1127 /* prepare TUV1236D/TU1236F NIM */ 1128 1129 na = 0x0a; /* Nxt2004 address */ 1130 x = 0; 1131 1132 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 1133 1134 for(i = 0; i < 5; i++) 1135 x |= iic_exec(&sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, na, 1136 nb[i], 2, NULL, 0, I2C_F_POLL); 1137 1138 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 1139 1140 if (x) 1141 aprint_error_dev(sc->sc_dev, "HDTV Wonder tuner init failed"); 1142 } 1143 1144 /* pcHDTV HD5500 */ 1145 #define cxdtv_write_field(_mask, _shift, _value) \ 1146 (((_value) & (_mask)) << (_shift)) 1147 1148 static void 1149 cxdtv_write_gpio(struct cxdtv_softc *sc, uint32_t mask, uint32_t value) 1150 { 1151 uint32_t v = 0; 1152 v |= cxdtv_write_field(0xff, 16, mask); 1153 v |= cxdtv_write_field(0xff, 8, mask); 1154 v |= cxdtv_write_field(0xff, 0, (mask & value)); 1155 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_GP0_IO, v); 1156 } 1157 1158 static void 1159 cxdtv_card_init_hd5500(struct cxdtv_softc *sc) 1160 { 1161 /* hardware (demod) reset */ 1162 cxdtv_write_gpio(sc, 1, 0); 1163 delay(100000); 1164 cxdtv_write_gpio(sc, 1, 1); 1165 delay(200000); 1166 } 1167 1168 MODULE(MODULE_CLASS_DRIVER, cxdtv, "dtv,tvpll,nxt2k,lg3303"); 1169 1170 #ifdef _MODULE 1171 #include "ioconf.c" 1172 #endif 1173 1174 static int 1175 cxdtv_modcmd(modcmd_t cmd, void *opaque) 1176 { 1177 switch (cmd) { 1178 case MODULE_CMD_INIT: 1179 #ifdef _MODULE 1180 return config_init_component(cfdriver_ioconf_cxdtv, 1181 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1182 #else 1183 return 0; 1184 #endif 1185 case MODULE_CMD_FINI: 1186 #ifdef _MODULE 1187 return config_fini_component(cfdriver_ioconf_cxdtv, 1188 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1189 #else 1190 return 0; 1191 #endif 1192 default: 1193 return ENOTTY; 1194 } 1195 } 1196
Indexes created Fri Oct 03 02:09:57 GMT 2025