cxgb_firmware_exports.h revision 1.2 1 1.1 jklos /**************************************************************************
2 1.1 jklos
3 1.1 jklos Copyright (c) 2007, Chelsio Inc.
4 1.1 jklos All rights reserved.
5 1.1 jklos
6 1.1 jklos Redistribution and use in source and binary forms, with or without
7 1.1 jklos modification, are permitted provided that the following conditions are met:
8 1.1 jklos
9 1.1 jklos 1. Redistributions of source code must retain the above copyright notice,
10 1.1 jklos this list of conditions and the following disclaimer.
11 1.1 jklos
12 1.1 jklos 2. Neither the name of the Chelsio Corporation nor the names of its
13 1.1 jklos contributors may be used to endorse or promote products derived from
14 1.1 jklos this software without specific prior written permission.
15 1.1 jklos
16 1.1 jklos THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 1.1 jklos AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 1.1 jklos IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 1.1 jklos ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 1.1 jklos LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 1.1 jklos CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 1.1 jklos SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 1.1 jklos INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 1.1 jklos CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 1.1 jklos ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 1.1 jklos POSSIBILITY OF SUCH DAMAGE.
27 1.1 jklos
28 1.1 jklos ***************************************************************************/
29 1.1 jklos #ifndef _FIRMWARE_EXPORTS_H_
30 1.1 jklos #define _FIRMWARE_EXPORTS_H_
31 1.1 jklos
32 1.1 jklos /* WR OPCODES supported by the firmware.
33 1.1 jklos */
34 1.1 jklos #define FW_WROPCODE_FORWARD 0x01
35 1.1 jklos #define FW_WROPCODE_BYPASS 0x05
36 1.1 jklos
37 1.1 jklos #define FW_WROPCODE_TUNNEL_TX_PKT 0x03
38 1.1 jklos
39 1.1 jklos #define FW_WROPOCDE_ULPTX_DATA_SGL 0x00
40 1.1 jklos #define FW_WROPCODE_ULPTX_MEM_READ 0x02
41 1.1 jklos #define FW_WROPCODE_ULPTX_PKT 0x04
42 1.1 jklos #define FW_WROPCODE_ULPTX_INVALIDATE 0x06
43 1.1 jklos
44 1.1 jklos #define FW_WROPCODE_TUNNEL_RX_PKT 0x07
45 1.1 jklos
46 1.1 jklos #define FW_WROPCODE_OFLD_GETTCB_RPL 0x08
47 1.1 jklos #define FW_WROPCODE_OFLD_CLOSE_CON 0x09
48 1.1 jklos #define FW_WROPCODE_OFLD_TP_ABORT_CON_REQ 0x0A
49 1.1 jklos #define FW_WROPCODE_OFLD_HOST_ABORT_CON_RPL 0x0F
50 1.1 jklos #define FW_WROPCODE_OFLD_HOST_ABORT_CON_REQ 0x0B
51 1.1 jklos #define FW_WROPCODE_OFLD_TP_ABORT_CON_RPL 0x0C
52 1.1 jklos #define FW_WROPCODE_OFLD_TX_DATA 0x0D
53 1.1 jklos #define FW_WROPCODE_OFLD_TX_DATA_ACK 0x0E
54 1.1 jklos
55 1.1 jklos #define FW_WROPCODE_RI_RDMA_INIT 0x10
56 1.1 jklos #define FW_WROPCODE_RI_RDMA_WRITE 0x11
57 1.1 jklos #define FW_WROPCODE_RI_RDMA_READ_REQ 0x12
58 1.1 jklos #define FW_WROPCODE_RI_RDMA_READ_RESP 0x13
59 1.1 jklos #define FW_WROPCODE_RI_SEND 0x14
60 1.1 jklos #define FW_WROPCODE_RI_TERMINATE 0x15
61 1.1 jklos #define FW_WROPCODE_RI_RDMA_READ 0x16
62 1.1 jklos #define FW_WROPCODE_RI_RECEIVE 0x17
63 1.1 jklos #define FW_WROPCODE_RI_BIND_MW 0x18
64 1.1 jklos #define FW_WROPCODE_RI_FASTREGISTER_MR 0x19
65 1.1 jklos #define FW_WROPCODE_RI_LOCAL_INV 0x1A
66 1.1 jklos #define FW_WROPCODE_RI_MODIFY_QP 0x1B
67 1.1 jklos #define FW_WROPCODE_RI_BYPASS 0x1C
68 1.1 jklos
69 1.1 jklos #define FW_WROPOCDE_RSVD 0x1E
70 1.1 jklos
71 1.1 jklos #define FW_WROPCODE_SGE_EGRESSCONTEXT_RR 0x1F
72 1.1 jklos
73 1.1 jklos #define FW_WROPCODE_MNGT 0x1D
74 1.1 jklos #define FW_MNGTOPCODE_PKTSCHED_SET 0x00
75 1.1 jklos
76 1.1 jklos /* Maximum size of a WR sent from the host, limited by the SGE.
77 1.1 jklos *
78 1.1 jklos * Note: WR coming from ULP or TP are only limited by CIM.
79 1.1 jklos */
80 1.1 jklos #define FW_WR_SIZE 128
81 1.1 jklos
82 1.1 jklos /* Maximum number of outstanding WRs sent from the host. Value must be
83 1.1 jklos * programmed in the CTRL/TUNNEL/QP SGE Egress Context and used by
84 1.1 jklos * offload modules to limit the number of WRs per connection.
85 1.1 jklos */
86 1.1 jklos #define FW_T3_WR_NUM 16
87 1.1 jklos #define FW_N3_WR_NUM 7
88 1.1 jklos
89 1.1 jklos #ifndef N3
90 1.1 jklos # define FW_WR_NUM FW_T3_WR_NUM
91 1.1 jklos #else
92 1.1 jklos # define FW_WR_NUM FW_N3_WR_NUM
93 1.1 jklos #endif
94 1.1 jklos
95 1.1 jklos /* FW_TUNNEL_NUM corresponds to the number of supported TUNNEL Queues. These
96 1.1 jklos * queues must start at SGE Egress Context FW_TUNNEL_SGEEC_START and must
97 1.1 jklos * start at 'TID' (or 'uP Token') FW_TUNNEL_TID_START.
98 1.1 jklos *
99 1.1 jklos * Ingress Traffic (e.g. DMA completion credit) for TUNNEL Queue[i] is sent
100 1.1 jklos * to RESP Queue[i].
101 1.1 jklos */
102 1.1 jklos #define FW_TUNNEL_NUM 8
103 1.1 jklos #define FW_TUNNEL_SGEEC_START 8
104 1.1 jklos #define FW_TUNNEL_TID_START 65544
105 1.1 jklos
106 1.1 jklos
107 1.1 jklos /* FW_CTRL_NUM corresponds to the number of supported CTRL Queues. These queues
108 1.1 jklos * must start at SGE Egress Context FW_CTRL_SGEEC_START and must start at 'TID'
109 1.1 jklos * (or 'uP Token') FW_CTRL_TID_START.
110 1.1 jklos *
111 1.1 jklos * Ingress Traffic for CTRL Queue[i] is sent to RESP Queue[i].
112 1.1 jklos */
113 1.1 jklos #define FW_CTRL_NUM 8
114 1.1 jklos #define FW_CTRL_SGEEC_START 65528
115 1.1 jklos #define FW_CTRL_TID_START 65536
116 1.1 jklos
117 1.1 jklos /* FW_OFLD_NUM corresponds to the number of supported OFFLOAD Queues. These
118 1.1 jklos * queues must start at SGE Egress Context FW_OFLD_SGEEC_START.
119 1.1 jklos *
120 1.1 jklos * Note: the 'uP Token' in the SGE Egress Context fields is irrelevant for
121 1.1 jklos * OFFLOAD Queues, as the host is responsible for providing the correct TID in
122 1.1 jklos * every WR.
123 1.1 jklos *
124 1.2 andvar * Ingress Traffic for OFFLOAD Queue[i] is sent to RESP Queue[i].
125 1.1 jklos */
126 1.1 jklos #define FW_OFLD_NUM 8
127 1.1 jklos #define FW_OFLD_SGEEC_START 0
128 1.1 jklos
129 1.1 jklos /*
130 1.1 jklos *
131 1.1 jklos */
132 1.1 jklos #define FW_RI_NUM 1
133 1.1 jklos #define FW_RI_SGEEC_START 65527
134 1.1 jklos #define FW_RI_TID_START 65552
135 1.1 jklos
136 1.1 jklos /*
137 1.1 jklos * The RX_PKT_TID
138 1.1 jklos */
139 1.1 jklos #define FW_RX_PKT_NUM 1
140 1.1 jklos #define FW_RX_PKT_TID_START 65553
141 1.1 jklos
142 1.1 jklos /* FW_WRC_NUM corresponds to the number of Work Request Context that supported
143 1.1 jklos * by the firmware.
144 1.1 jklos */
145 1.1 jklos #define FW_WRC_NUM \
146 1.1 jklos (65536 + FW_TUNNEL_NUM + FW_CTRL_NUM + FW_RI_NUM + FW_RX_PKT_NUM)
147 1.1 jklos
148 1.1 jklos /*
149 1.1 jklos * FW type and version.
150 1.1 jklos */
151 1.1 jklos #define S_FW_VERSION_TYPE 28
152 1.1 jklos #define M_FW_VERSION_TYPE 0xF
153 1.1 jklos #define V_FW_VERSION_TYPE(x) ((x) << S_FW_VERSION_TYPE)
154 1.1 jklos #define G_FW_VERSION_TYPE(x) \
155 1.1 jklos (((x) >> S_FW_VERSION_TYPE) & M_FW_VERSION_TYPE)
156 1.1 jklos
157 1.1 jklos #define S_FW_VERSION_MAJOR 16
158 1.1 jklos #define M_FW_VERSION_MAJOR 0xFFF
159 1.1 jklos #define V_FW_VERSION_MAJOR(x) ((x) << S_FW_VERSION_MAJOR)
160 1.1 jklos #define G_FW_VERSION_MAJOR(x) \
161 1.1 jklos (((x) >> S_FW_VERSION_MAJOR) & M_FW_VERSION_MAJOR)
162 1.1 jklos
163 1.1 jklos #define S_FW_VERSION_MINOR 8
164 1.1 jklos #define M_FW_VERSION_MINOR 0xFF
165 1.1 jklos #define V_FW_VERSION_MINOR(x) ((x) << S_FW_VERSION_MINOR)
166 1.1 jklos #define G_FW_VERSION_MINOR(x) \
167 1.1 jklos (((x) >> S_FW_VERSION_MINOR) & M_FW_VERSION_MINOR)
168 1.1 jklos
169 1.1 jklos #define S_FW_VERSION_MICRO 0
170 1.1 jklos #define M_FW_VERSION_MICRO 0xFF
171 1.1 jklos #define V_FW_VERSION_MICRO(x) ((x) << S_FW_VERSION_MICRO)
172 1.1 jklos #define G_FW_VERSION_MICRO(x) \
173 1.1 jklos (((x) >> S_FW_VERSION_MICRO) & M_FW_VERSION_MICRO)
174 1.1 jklos
175 1.1 jklos #endif /* _FIRMWARE_EXPORTS_H_ */
176