cxgb_osdep.h revision 1.2.14.1
1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 29 ***************************************************************************/ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/endian.h> 34 35 #include <dev/mii/mii.h> 36 37 #ifndef _CXGB_OSDEP_H_ 38 #define _CXGB_OSDEP_H_ 39 40 typedef char *caddr_t; 41 #include <dev/pci/cxgb/cxgb_version.h> 42 #include <dev/pci/cxgb/cxgb_config.h> 43 #include <sys/mbuf.h> 44 #include <sys/bus.h> 45 46 #include <netinet/in_systm.h> 47 #include <netinet/in.h> 48 #include <netinet/ip.h> 49 50 #include <sys/simplelock.h> 51 52 #include <sys/kthread.h> 53 #include <sys/workqueue.h> 54 55 #include <sys/atomic.h> 56 57 void pci_enable_busmaster(device_t dev); 58 59 struct cxgb_task 60 { 61 const char *name; 62 void (*func)(struct work *, void *); 63 struct workqueue *wq; 64 struct work w; 65 void *context; 66 }; 67 68 void cxgb_make_task(void *); 69 70 void m_cljset(struct mbuf *m, void *cl, int type); 71 72 #define mtx simplelock 73 #define mtx_init(a, b, c, d) { (a)->lock_data = __SIMPLELOCK_UNLOCKED; } 74 #define mtx_destroy(a) 75 #define mtx_lock(a) simple_lock(a) 76 #define mtx_unlock(a) simple_unlock(a) 77 #define mtx_trylock(a) simple_lock_try(a) 78 #define MA_OWNED 1 79 #define MA_NOTOWNED 0 80 #define mtx_assert(a, w) 81 82 #if 0 83 #define RT_LOCK_INIT(_rt) \ 84 mtx_init(&(_rt)->rt_mtx, "rtentry", NULL, MTX_DEF | MTX_DUPOK) 85 #define RT_LOCK(_rt) mtx_lock(&(_rt)->rt_mtx) 86 #define RT_UNLOCK(_rt) mtx_unlock(&(_rt)->rt_mtx) 87 #define RT_LOCK_DESTROY(_rt) mtx_destroy(&(_rt)->rt_mtx) 88 #define RT_LOCK_ASSERT(_rt) mtx_assert(&(_rt)->rt_mtx, MA_OWNED) 89 #else 90 #define RT_LOCK_INIT(_rt) 91 #define RT_LOCK(_rt) 92 #define RT_UNLOCK(_rt) 93 #define RT_LOCK_DESTROY(_rt) 94 #define RT_LOCK_ASSERT(_rt) 95 #endif 96 97 #define RT_ADDREF(_rt) do { \ 98 RT_LOCK_ASSERT(_rt); \ 99 KASSERT((_rt)->rt_refcnt >= 0); \ 100 (_rt)->rt_refcnt++; \ 101 } while (0) 102 #define RT_REMREF(_rt) do { \ 103 RT_LOCK_ASSERT(_rt); \ 104 KASSERT((_rt)->rt_refcnt > 0); \ 105 (_rt)->rt_refcnt--; \ 106 } while (0) 107 108 109 #define EVL_VLID_MASK 0x0FFF 110 111 static inline void critical_enter(void) 112 { 113 } 114 115 static inline void critical_exit(void) 116 { 117 } 118 119 int atomic_fetchadd_int(volatile int *p, int v); 120 #if 0 121 int atomic_add_int(volatile int *p, int v); 122 #endif 123 int atomic_load_acq_int(volatile int *p); 124 void atomic_store_rel_int(volatile int *p, int v); 125 126 u_short in_cksum_hdr(struct ip *ih); 127 128 #define if_drv_flags if_flags 129 #define IFF_DRV_RUNNING IFF_RUNNING 130 #define IFF_DRV_OACTIVE IFF_OACTIVE 131 132 #define MJUM16BYTES (16*1024) 133 #define MJUMPAGESIZE PAGE_SIZE 134 135 #if 0 136 #define rw_rlock(x) rw_enter(x, RW_READER) 137 #define rw_runlock(x) rw_exit(x) 138 #define rw_wlock(x) rw_enter(x, RW_WRITER) 139 #define rw_wunlock(x) rw_exit(x) 140 #endif 141 142 #define callout_drain(x) callout_stop(x) 143 144 static inline int atomic_cmpset_ptr(volatile long *dst, long exp, long src) 145 { 146 if (*dst == exp) 147 { 148 *dst = src; 149 return (1); 150 } 151 return (0); 152 } 153 #define atomic_cmpset_int(a, b, c) atomic_cmpset_ptr((volatile long *)a, (long)b, (long)c) 154 155 static inline int atomic_set_int(volatile int *dst, int val) 156 { 157 *dst = val; 158 159 return (val); 160 } 161 162 static inline void log(int x, ...) 163 { 164 } 165 166 struct cxgb_attach_args 167 { 168 int port; 169 }; 170 171 #define INT3 __asm("int $3") 172 173 typedef struct adapter adapter_t; 174 struct sge_rspq; 175 176 struct t3_mbuf_hdr { 177 struct mbuf *mh_head; 178 struct mbuf *mh_tail; 179 }; 180 181 182 #define PANIC_IF(exp) do { \ 183 if (exp) \ 184 panic("BUG: %s", exp); \ 185 } while (0) 186 187 188 #define m_get_priority(m) ((uintptr_t)(m)->m_pkthdr.rcvif) 189 #define m_set_priority(m, pri) ((m)->m_pkthdr.rcvif = (struct ifnet *)((uintptr_t)pri)) 190 191 #define if_name(ifp) (ifp)->if_xname 192 #define M_SANITY(m, n) 193 194 /* 195 * Workaround for weird Chelsio issue 196 */ 197 #define CXGB_TX_CLEANUP_THRESHOLD 32 198 199 #define LOG_WARNING 1 200 #define LOG_ERR 2 201 202 #define DPRINTF printf 203 204 #define TX_MAX_SIZE (1 << 16) /* 64KB */ 205 #define TX_MAX_SEGS 36 /* maximum supported by card */ 206 #define TX_MAX_DESC 4 /* max descriptors per packet */ 207 208 #define TX_START_MIN_DESC (TX_MAX_DESC << 2) 209 210 #if 0 211 #define TX_START_MAX_DESC (TX_ETH_Q_SIZE >> 2) /* maximum number of descriptors */ 212 #endif 213 214 #define TX_START_MAX_DESC (TX_MAX_DESC << 3) /* maximum number of descriptors 215 * call to start used per */ 216 217 #define TX_CLEAN_MAX_DESC (TX_MAX_DESC << 4) /* maximum tx descriptors 218 * to clean per iteration */ 219 220 221 #if defined(__i386__) || defined(__amd64__) 222 #define mb() __asm volatile("mfence":::"memory") 223 #define rmb() __asm volatile("lfence":::"memory") 224 #define wmb() __asm volatile("sfence" ::: "memory") 225 #define smp_mb() mb() 226 227 #define L1_CACHE_BYTES 64 228 static __inline 229 void prefetch(void *x) 230 { 231 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 232 } 233 234 extern void kdb_backtrace(void); 235 236 #define WARN_ON(condition) do { \ 237 if (unlikely((condition)!=0)) { \ 238 log(LOG_WARNING, "BUG: warning at %s:%d/%s()\n", __FILE__, __LINE__, __func__); \ 239 kdb_backtrace(); \ 240 } \ 241 } while (0) 242 243 244 #else /* !i386 && !amd64 */ 245 #define mb() 246 #define rmb() 247 #define wmb() 248 #define smp_mb() 249 #define prefetch(x) 250 #define L1_CACHE_BYTES 32 251 #endif 252 #define DBG_RX (1 << 0) 253 static const int debug_flags = DBG_RX; 254 255 #ifdef DEBUG_PRINT 256 #define DBG(flag, msg) do { \ 257 if ((flag & debug_flags)) \ 258 printf msg; \ 259 } while (0) 260 #else 261 #define DBG(...) 262 #endif 263 264 #define promisc_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_PROMISC) 265 #define allmulti_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_ALLMULTI) 266 267 #define CH_ERR(adap, fmt, ...) { } 268 269 #define CH_WARN(adap, fmt, ...) { } 270 #define CH_ALERT(adap, fmt, ...) { } 271 272 #define t3_os_sleep(x) DELAY((x) * 1000) 273 274 #define test_and_clear_bit(bit, p) atomic_cmpset_int((p), ((*(p)) | bit), ((*(p)) & ~bit)) 275 276 277 #define max_t(type, a, b) (type)max((a), (b)) 278 #define net_device ifnet 279 #define cpu_to_be32 htobe32 280 281 282 283 /* Standard PHY definitions */ 284 #define BMCR_LOOPBACK BMCR_LOOP 285 #define BMCR_ISOLATE BMCR_ISO 286 #define BMCR_ANENABLE BMCR_AUTOEN 287 #define BMCR_SPEED1000 BMCR_SPEED1 288 #define BMCR_SPEED100 BMCR_SPEED0 289 #define BMCR_ANRESTART BMCR_STARTNEG 290 #define BMCR_FULLDPLX BMCR_FDX 291 #define BMSR_LSTATUS BMSR_LINK 292 #define BMSR_ANEGCOMPLETE BMSR_ACOMP 293 294 #define MII_LPA MII_ANLPAR 295 #define MII_ADVERTISE MII_ANAR 296 #define MII_CTRL1000 MII_100T2CR 297 298 #define ADVERTISE_PAUSE_CAP ANAR_FC 299 #define ADVERTISE_PAUSE_ASYM 0x0800 300 #define ADVERTISE_1000HALF ANAR_X_HD 301 #define ADVERTISE_1000FULL ANAR_X_FD 302 #define ADVERTISE_10FULL ANAR_10_FD 303 #define ADVERTISE_10HALF ANAR_10 304 #define ADVERTISE_100FULL ANAR_TX_FD 305 #define ADVERTISE_100HALF ANAR_TX 306 307 /* Standard PCI Extended Capaibilities definitions */ 308 #define PCI_CAP_ID_VPD 0x03 309 #define PCI_VPD_ADDR 2 310 #define PCI_VPD_ADDR_F 0x8000 311 #define PCI_VPD_DATA 4 312 313 #define PCI_CAP_ID_EXP 0x10 314 #define PCI_EXP_DEVCTL 8 315 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 316 #define PCI_EXP_LNKCTL 16 317 #define PCI_EXP_LNKSTA 18 318 319 /* 320 * Linux compatibility macros 321 */ 322 323 /* Some simple translations */ 324 #define __devinit 325 #define udelay(x) DELAY(x) 326 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 327 #define le32_to_cpu(x) le32toh(x) 328 #define cpu_to_le32(x) htole32(x) 329 #define swab32(x) bswap32(x) 330 #define simple_strtoul strtoul 331 332 /* More types and endian definitions */ 333 typedef uint8_t u8; 334 typedef uint16_t u16; 335 typedef uint32_t u32; 336 typedef uint64_t u64; 337 338 typedef uint8_t __u8; 339 typedef uint16_t __u16; 340 typedef uint32_t __u32; 341 typedef uint8_t __be8; 342 typedef uint16_t __be16; 343 typedef uint32_t __be32; 344 typedef uint64_t __be64; 345 346 #if BYTE_ORDER == BIG_ENDIAN 347 #define __BIG_ENDIAN_BITFIELD 348 #elif BYTE_ORDER == LITTLE_ENDIAN 349 #define __LITTLE_ENDIAN_BITFIELD 350 #else 351 #error "Must set BYTE_ORDER" 352 #endif 353 354 /* Indicates what features are supported by the interface. */ 355 #define SUPPORTED_10baseT_Half (1 << 0) 356 #define SUPPORTED_10baseT_Full (1 << 1) 357 #define SUPPORTED_100baseT_Half (1 << 2) 358 #define SUPPORTED_100baseT_Full (1 << 3) 359 #define SUPPORTED_1000baseT_Half (1 << 4) 360 #define SUPPORTED_1000baseT_Full (1 << 5) 361 #define SUPPORTED_Autoneg (1 << 6) 362 #define SUPPORTED_TP (1 << 7) 363 #define SUPPORTED_AUI (1 << 8) 364 #define SUPPORTED_MII (1 << 9) 365 #define SUPPORTED_FIBRE (1 << 10) 366 #define SUPPORTED_BNC (1 << 11) 367 #define SUPPORTED_10000baseT_Full (1 << 12) 368 #define SUPPORTED_Pause (1 << 13) 369 #define SUPPORTED_Asym_Pause (1 << 14) 370 371 /* Indicates what features are advertised by the interface. */ 372 #define ADVERTISED_10baseT_Half (1 << 0) 373 #define ADVERTISED_10baseT_Full (1 << 1) 374 #define ADVERTISED_100baseT_Half (1 << 2) 375 #define ADVERTISED_100baseT_Full (1 << 3) 376 #define ADVERTISED_1000baseT_Half (1 << 4) 377 #define ADVERTISED_1000baseT_Full (1 << 5) 378 #define ADVERTISED_Autoneg (1 << 6) 379 #define ADVERTISED_TP (1 << 7) 380 #define ADVERTISED_AUI (1 << 8) 381 #define ADVERTISED_MII (1 << 9) 382 #define ADVERTISED_FIBRE (1 << 10) 383 #define ADVERTISED_BNC (1 << 11) 384 #define ADVERTISED_10000baseT_Full (1 << 12) 385 #define ADVERTISED_Pause (1 << 13) 386 #define ADVERTISED_Asym_Pause (1 << 14) 387 388 /* Enable or disable autonegotiation. If this is set to enable, 389 * the forced link modes above are completely ignored. 390 */ 391 #define AUTONEG_DISABLE 0x00 392 #define AUTONEG_ENABLE 0x01 393 394 #define SPEED_10 10 395 #define SPEED_100 100 396 #define SPEED_1000 1000 397 #define SPEED_10000 10000 398 #define DUPLEX_HALF 0 399 #define DUPLEX_FULL 1 400 401 #endif 402
Indexes created Tue Oct 28 12:10:06 GMT 2025