cy82c693.c revision 1.11 1 /* $NetBSD: cy82c693.c,v 1.11 2024/08/17 14:58:51 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Common routines to read/write control registers on the Cypress 82c693
34 * hyperCache(tm) Stand-Alone PCI Peripheral Controller with USB.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: cy82c693.c,v 1.11 2024/08/17 14:58:51 thorpej Exp $");
39
40 #include <sys/param.h>
41 #include <sys/device.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/once.h>
45
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48
49 #include <dev/pci/cy82c693reg.h>
50 #include <dev/pci/cy82c693var.h>
51
52 ONCE_DECL(cyhc_once);
53
54 static struct cy82c693_handle cyhc_handle;
55 static int cyhc_initialized;
56
57 static kmutex_t cyhc_lock;
58
59 static int
60 cy82c693_onceinit(void)
61 {
62
63 mutex_init(&cyhc_lock, MUTEX_DEFAULT, IPL_NONE);
64 return 0;
65 }
66
67 const struct cy82c693_handle *
68 cy82c693_init(bus_space_tag_t iot)
69 {
70 bus_space_handle_t ioh;
71 int err;
72
73 err = RUN_ONCE(&cyhc_once, cy82c693_onceinit);
74 if (err)
75 return NULL;
76
77 mutex_enter(&cyhc_lock);
78
79 if (cyhc_initialized) {
80 mutex_exit(&cyhc_lock);
81 KASSERT(bus_space_is_equal(iot, cyhc_handle.cyhc_iot));
82 return &cyhc_handle;
83 }
84
85 if (bus_space_map(iot, CYHC_CONFIG_ADDR, 2, 0, &ioh) != 0) {
86 mutex_exit(&cyhc_lock);
87 return NULL;
88 }
89
90 cyhc_handle.cyhc_iot = iot;
91 cyhc_handle.cyhc_ioh = ioh;
92
93 cyhc_initialized = 1;
94
95 mutex_exit(&cyhc_lock);
96
97 return &cyhc_handle;
98 }
99
100 u_int8_t
101 cy82c693_read(const struct cy82c693_handle *cyhc, int reg)
102 {
103 uint8_t rv;
104
105 KASSERT(cyhc != NULL);
106 KASSERT(cyhc_initialized);
107
108 mutex_enter(&cyhc_lock);
109
110 bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
111 rv = bus_space_read_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 1);
112
113 mutex_exit(&cyhc_lock);
114
115 return rv;
116 }
117
118 void
119 cy82c693_write(const struct cy82c693_handle *cyhc, int reg, u_int8_t val)
120 {
121
122 KASSERT(cyhc != NULL);
123 KASSERT(cyhc_initialized);
124
125 mutex_enter(&cyhc_lock);
126
127 bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
128 bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 1, val);
129
130 mutex_exit(&cyhc_lock);
131 }
132