cy82c693.c revision 1.8 1 /* $NetBSD: cy82c693.c,v 1.8 2010/04/19 18:24:27 dyoung Exp $ */
2
3 /*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Common routines to read/write control registers on the Cypress 82c693
34 * hyperCache(tm) Stand-Alone PCI Peripheral Controller with USB.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: cy82c693.c,v 1.8 2010/04/19 18:24:27 dyoung Exp $");
39
40 #include "opt_multiprocessor.h"
41 #include "opt_lockdebug.h"
42
43 #include <sys/param.h>
44 #include <sys/device.h>
45 #include <sys/systm.h>
46 #include <sys/bus.h>
47 #include <sys/simplelock.h>
48
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51
52 #include <dev/pci/cy82c693reg.h>
53 #include <dev/pci/cy82c693var.h>
54
55 static struct cy82c693_handle cyhc_handle;
56 static int cyhc_initialized;
57
58 static struct simplelock cyhc_slock = SIMPLELOCK_INITIALIZER;
59
60 #define CYHC_LOCK(s) \
61 do { \
62 s = splhigh(); \
63 simple_lock(&cyhc_slock); \
64 } while (0)
65
66 #define CYHC_UNLOCK(s) \
67 do { \
68 simple_unlock(&cyhc_slock); \
69 splx(s); \
70 } while (0)
71
72 const struct cy82c693_handle *
73 cy82c693_init(bus_space_tag_t iot)
74 {
75 bus_space_handle_t ioh;
76 int s;
77
78 CYHC_LOCK(s);
79
80 if (cyhc_initialized) {
81 CYHC_UNLOCK(s);
82 KASSERT(bus_space_is_equal(iot, cyhc_handle.cyhc_iot));
83 return (&cyhc_handle);
84 }
85
86 if (bus_space_map(iot, CYHC_CONFIG_ADDR, 2, 0, &ioh) != 0) {
87 CYHC_UNLOCK(s);
88 return (NULL);
89 }
90
91 cyhc_handle.cyhc_iot = iot;
92 cyhc_handle.cyhc_ioh = ioh;
93
94 cyhc_initialized = 1;
95
96 CYHC_UNLOCK(s);
97
98 return (&cyhc_handle);
99 }
100
101 u_int8_t
102 cy82c693_read(const struct cy82c693_handle *cyhc, int reg)
103 {
104 int s;
105 u_int8_t rv;
106
107 CYHC_LOCK(s);
108
109 if (cyhc_initialized == 0) {
110 CYHC_UNLOCK(s);
111 panic("cy82c693_read");
112 }
113
114 bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
115 rv = bus_space_read_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 1);
116
117 CYHC_UNLOCK(s);
118
119 return (rv);
120 }
121
122 void
123 cy82c693_write(const struct cy82c693_handle *cyhc, int reg, u_int8_t val)
124 {
125 int s;
126
127 CYHC_LOCK(s);
128
129 if (cyhc_initialized == 0) {
130 CYHC_UNLOCK(s);
131 panic("cy82c693_write");
132 }
133
134 bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
135 bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 1, val);
136
137 CYHC_UNLOCK(s);
138 }
139