cypide.c revision 1.19
1 /* $NetBSD: cypide.c,v 1.19 2006/11/16 01:33:08 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: cypide.c,v 1.19 2006/11/16 01:33:08 christos Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciidereg.h> 43 #include <dev/pci/pciidevar.h> 44 #include <dev/pci/pciide_cy693_reg.h> 45 #include <dev/pci/cy82c693var.h> 46 47 static void cy693_chip_map(struct pciide_softc*, struct pci_attach_args*); 48 static void cy693_setup_channel(struct ata_channel*); 49 50 static int cypide_match(struct device *, struct cfdata *, void *); 51 static void cypide_attach(struct device *, struct device *, void *); 52 53 CFATTACH_DECL(cypide, sizeof(struct pciide_softc), 54 cypide_match, cypide_attach, NULL, NULL); 55 56 static const struct pciide_product_desc pciide_cypress_products[] = { 57 { PCI_PRODUCT_CONTAQ_82C693, 58 IDE_16BIT_IOSPACE, 59 "Cypress 82C693 IDE Controller", 60 cy693_chip_map, 61 }, 62 { 0, 63 0, 64 NULL, 65 NULL 66 } 67 }; 68 69 static int 70 cypide_match(struct device *parent, struct cfdata *match, 71 void *aux) 72 { 73 struct pci_attach_args *pa = aux; 74 75 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CONTAQ && 76 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 77 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 78 if (pciide_lookup_product(pa->pa_id, pciide_cypress_products)) 79 return (2); 80 } 81 return (0); 82 } 83 84 static void 85 cypide_attach(struct device *parent, struct device *self, void *aux) 86 { 87 struct pci_attach_args *pa = aux; 88 struct pciide_softc *sc = (struct pciide_softc *)self; 89 90 pciide_common_attach(sc, pa, 91 pciide_lookup_product(pa->pa_id, pciide_cypress_products)); 92 93 } 94 95 static void 96 cy693_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 97 { 98 struct pciide_channel *cp; 99 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 100 bus_size_t cmdsize, ctlsize; 101 102 if (pciide_chipen(sc, pa) == 0) 103 return; 104 105 /* 106 * this chip has 2 PCI IDE functions, one for primary and one for 107 * secondary. So we need to call pciide_mapregs_compat() with 108 * the real channel 109 */ 110 if (pa->pa_function == 1) { 111 sc->sc_cy_compatchan = 0; 112 } else if (pa->pa_function == 2) { 113 sc->sc_cy_compatchan = 1; 114 } else { 115 aprint_error("%s: unexpected PCI function %d\n", 116 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, pa->pa_function); 117 return; 118 } 119 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 120 aprint_normal("%s: bus-master DMA support present", 121 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 122 pciide_mapreg_dma(sc, pa); 123 } else { 124 aprint_normal("%s: hardware does not support DMA", 125 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 126 sc->sc_dma_ok = 0; 127 } 128 aprint_normal("\n"); 129 130 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 131 if (sc->sc_cy_handle == NULL) { 132 aprint_error("%s: unable to map hyperCache control registers\n", 133 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 134 sc->sc_dma_ok = 0; 135 } 136 137 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 138 if (sc->sc_dma_ok) { 139 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 140 sc->sc_wdcdev.irqack = pciide_irqack; 141 } 142 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 143 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 144 sc->sc_wdcdev.sc_atac.atac_set_modes = cy693_setup_channel; 145 146 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 147 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 148 149 wdc_allocate_regs(&sc->sc_wdcdev); 150 151 /* Only one channel for this chip; if we are here it's enabled */ 152 cp = &sc->pciide_channels[0]; 153 sc->wdc_chanarray[0] = &cp->ata_channel; 154 cp->name = PCIIDE_CHANNEL_NAME(0); 155 cp->ata_channel.ch_channel = 0; 156 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 157 cp->ata_channel.ch_queue = 158 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 159 cp->ata_channel.ch_ndrive = 2; 160 if (cp->ata_channel.ch_queue == NULL) { 161 aprint_error("%s primary channel: " 162 "can't allocate memory for command queue", 163 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 164 return; 165 } 166 aprint_normal("%s: primary channel %s to ", 167 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 168 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 169 "configured" : "wired"); 170 if (interface & PCIIDE_INTERFACE_PCI(0)) { 171 aprint_normal("native-PCI mode\n"); 172 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 173 pciide_pci_intr); 174 } else { 175 aprint_normal("compatibility mode\n"); 176 pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, &cmdsize, 177 &ctlsize); 178 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 179 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan); 180 } 181 wdcattach(&cp->ata_channel); 182 } 183 184 static void 185 cy693_setup_channel(struct ata_channel *chp) 186 { 187 struct ata_drive_datas *drvp; 188 int drive; 189 u_int32_t cy_cmd_ctrl; 190 u_int32_t idedma_ctl; 191 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 192 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 193 int dma_mode = -1; 194 195 ATADEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 196 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 197 198 cy_cmd_ctrl = idedma_ctl = 0; 199 200 /* setup DMA if needed */ 201 pciide_channel_dma_setup(cp); 202 203 for (drive = 0; drive < 2; drive++) { 204 drvp = &chp->ch_drive[drive]; 205 /* If no drive, skip */ 206 if ((drvp->drive_flags & DRIVE) == 0) 207 continue; 208 /* add timing values, setup DMA if needed */ 209 if (drvp->drive_flags & DRIVE_DMA) { 210 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 211 /* use Multiword DMA */ 212 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 213 dma_mode = drvp->DMA_mode; 214 } 215 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 216 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 217 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 218 CY_CMD_CTRL_IOW_REC_OFF(drive)); 219 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 220 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 221 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 222 CY_CMD_CTRL_IOR_REC_OFF(drive)); 223 } 224 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 225 chp->ch_drive[0].DMA_mode = dma_mode; 226 chp->ch_drive[1].DMA_mode = dma_mode; 227 228 if (dma_mode == -1) 229 dma_mode = 0; 230 231 if (sc->sc_cy_handle != NULL) { 232 /* Note: `multiple' is implied. */ 233 cy82c693_write(sc->sc_cy_handle, 234 (sc->sc_cy_compatchan == 0) ? 235 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 236 } 237 238 if (idedma_ctl != 0) { 239 /* Add software bits in status register */ 240 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 241 idedma_ctl); 242 } 243 ATADEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 244 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 245 } 246
Indexes created Wed Oct 22 13:09:56 GMT 2025