cypide.c revision 1.2
1 /* $NetBSD: cypide.c,v 1.2 2003/10/11 17:40:15 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 #include <dev/pci/pciide_cy693_reg.h> 42 #include <dev/pci/cy82c693var.h> 43 44 static void cy693_chip_map(struct pciide_softc*, struct pci_attach_args*); 45 static void cy693_setup_channel(struct channel_softc*); 46 47 static int cypide_match(struct device *, struct cfdata *, void *); 48 static void cypide_attach(struct device *, struct device *, void *); 49 50 CFATTACH_DECL(cypide, sizeof(struct pciide_softc), 51 cypide_match, cypide_attach, NULL, NULL); 52 53 static const struct pciide_product_desc pciide_cypress_products[] = { 54 { PCI_PRODUCT_CONTAQ_82C693, 55 IDE_16BIT_IOSPACE, 56 "Cypress 82C693 IDE Controller", 57 cy693_chip_map, 58 }, 59 { 0, 60 0, 61 NULL, 62 NULL 63 } 64 }; 65 66 static int 67 cypide_match(struct device *parent, struct cfdata *match, void *aux) 68 { 69 struct pci_attach_args *pa = aux; 70 71 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CONTAQ) { 72 if (pciide_lookup_product(pa->pa_id, pciide_cypress_products)) 73 return (2); 74 } 75 return (0); 76 } 77 78 static void 79 cypide_attach(struct device *parent, struct device *self, void *aux) 80 { 81 struct pci_attach_args *pa = aux; 82 struct pciide_softc *sc = (struct pciide_softc *)self; 83 84 pciide_common_attach(sc, pa, 85 pciide_lookup_product(pa->pa_id, pciide_cypress_products)); 86 87 } 88 89 static void 90 cy693_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 91 { 92 struct pciide_channel *cp; 93 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 94 bus_size_t cmdsize, ctlsize; 95 96 if (pciide_chipen(sc, pa) == 0) 97 return; 98 99 /* 100 * this chip has 2 PCI IDE functions, one for primary and one for 101 * secondary. So we need to call pciide_mapregs_compat() with 102 * the real channel 103 */ 104 if (pa->pa_function == 1) { 105 sc->sc_cy_compatchan = 0; 106 } else if (pa->pa_function == 2) { 107 sc->sc_cy_compatchan = 1; 108 } else { 109 aprint_error("%s: unexpected PCI function %d\n", 110 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 111 return; 112 } 113 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 114 aprint_normal("%s: bus-master DMA support present", 115 sc->sc_wdcdev.sc_dev.dv_xname); 116 pciide_mapreg_dma(sc, pa); 117 } else { 118 aprint_normal("%s: hardware does not support DMA", 119 sc->sc_wdcdev.sc_dev.dv_xname); 120 sc->sc_dma_ok = 0; 121 } 122 aprint_normal("\n"); 123 124 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 125 if (sc->sc_cy_handle == NULL) { 126 aprint_error("%s: unable to map hyperCache control registers\n", 127 sc->sc_wdcdev.sc_dev.dv_xname); 128 sc->sc_dma_ok = 0; 129 } 130 131 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 132 WDC_CAPABILITY_MODE; 133 if (sc->sc_dma_ok) { 134 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 135 sc->sc_wdcdev.irqack = pciide_irqack; 136 } 137 sc->sc_wdcdev.PIO_cap = 4; 138 sc->sc_wdcdev.DMA_cap = 2; 139 sc->sc_wdcdev.set_modes = cy693_setup_channel; 140 141 sc->sc_wdcdev.channels = sc->wdc_chanarray; 142 sc->sc_wdcdev.nchannels = 1; 143 144 /* Only one channel for this chip; if we are here it's enabled */ 145 cp = &sc->pciide_channels[0]; 146 sc->wdc_chanarray[0] = &cp->wdc_channel; 147 cp->name = PCIIDE_CHANNEL_NAME(0); 148 cp->wdc_channel.channel = 0; 149 cp->wdc_channel.wdc = &sc->sc_wdcdev; 150 cp->wdc_channel.ch_queue = 151 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 152 if (cp->wdc_channel.ch_queue == NULL) { 153 aprint_error("%s primary channel: " 154 "can't allocate memory for command queue", 155 sc->sc_wdcdev.sc_dev.dv_xname); 156 return; 157 } 158 aprint_normal("%s: primary channel %s to ", 159 sc->sc_wdcdev.sc_dev.dv_xname, 160 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 161 "configured" : "wired"); 162 if (interface & PCIIDE_INTERFACE_PCI(0)) { 163 aprint_normal("native-PCI mode\n"); 164 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 165 pciide_pci_intr); 166 } else { 167 aprint_normal("compatibility mode\n"); 168 pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, &cmdsize, 169 &ctlsize); 170 } 171 wdcattach(&cp->wdc_channel); 172 } 173 174 static void 175 cy693_setup_channel(struct channel_softc *chp) 176 { 177 struct ata_drive_datas *drvp; 178 int drive; 179 u_int32_t cy_cmd_ctrl; 180 u_int32_t idedma_ctl; 181 struct pciide_channel *cp = (struct pciide_channel*)chp; 182 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 183 int dma_mode = -1; 184 185 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 186 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 187 188 cy_cmd_ctrl = idedma_ctl = 0; 189 190 /* setup DMA if needed */ 191 pciide_channel_dma_setup(cp); 192 193 for (drive = 0; drive < 2; drive++) { 194 drvp = &chp->ch_drive[drive]; 195 /* If no drive, skip */ 196 if ((drvp->drive_flags & DRIVE) == 0) 197 continue; 198 /* add timing values, setup DMA if needed */ 199 if (drvp->drive_flags & DRIVE_DMA) { 200 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 201 /* use Multiword DMA */ 202 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 203 dma_mode = drvp->DMA_mode; 204 } 205 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 206 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 207 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 208 CY_CMD_CTRL_IOW_REC_OFF(drive)); 209 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 210 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 211 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 212 CY_CMD_CTRL_IOR_REC_OFF(drive)); 213 } 214 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 215 chp->ch_drive[0].DMA_mode = dma_mode; 216 chp->ch_drive[1].DMA_mode = dma_mode; 217 218 if (dma_mode == -1) 219 dma_mode = 0; 220 221 if (sc->sc_cy_handle != NULL) { 222 /* Note: `multiple' is implied. */ 223 cy82c693_write(sc->sc_cy_handle, 224 (sc->sc_cy_compatchan == 0) ? 225 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 226 } 227 228 if (idedma_ctl != 0) { 229 /* Add software bits in status register */ 230 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 231 IDEDMA_CTL, idedma_ctl); 232 } 233 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 234 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 235 } 236
Indexes created Mon Oct 20 16:09:52 GMT 2025