cypide.c revision 1.29.2.2
1 /* $NetBSD: cypide.c,v 1.29.2.2 2014/08/20 00:03:42 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: cypide.c,v 1.29.2.2 2014/08/20 00:03:42 tls Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_cy693_reg.h> 40 #include <dev/pci/cy82c693var.h> 41 42 static void cy693_chip_map(struct pciide_softc*, const struct pci_attach_args*); 43 static void cy693_setup_channel(struct ata_channel*); 44 45 static int cypide_match(device_t, cfdata_t, void *); 46 static void cypide_attach(device_t, device_t, void *); 47 48 CFATTACH_DECL_NEW(cypide, sizeof(struct pciide_softc), 49 cypide_match, cypide_attach, pciide_detach, NULL); 50 51 static const struct pciide_product_desc pciide_cypress_products[] = { 52 { PCI_PRODUCT_CONTAQ_82C693, 53 IDE_16BIT_IOSPACE, 54 "Cypress 82C693 IDE Controller", 55 cy693_chip_map, 56 }, 57 { 0, 58 0, 59 NULL, 60 NULL 61 } 62 }; 63 64 static int 65 cypide_match(device_t parent, cfdata_t match, void *aux) 66 { 67 struct pci_attach_args *pa = aux; 68 69 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CONTAQ && 70 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 71 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 72 if (pciide_lookup_product(pa->pa_id, pciide_cypress_products)) 73 return (2); 74 } 75 return (0); 76 } 77 78 static void 79 cypide_attach(device_t parent, device_t self, void *aux) 80 { 81 struct pci_attach_args *pa = aux; 82 struct pciide_softc *sc = device_private(self); 83 84 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 85 86 sc->sc_wdcdev.sc_atac.atac_dev = self; 87 88 pciide_common_attach(sc, pa, 89 pciide_lookup_product(pa->pa_id, pciide_cypress_products)); 90 91 } 92 93 static void 94 cy693_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 95 { 96 struct pciide_channel *cp; 97 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 98 99 if (pciide_chipen(sc, pa) == 0) 100 return; 101 102 /* 103 * this chip has 2 PCI IDE functions, one for primary and one for 104 * secondary. So we need to call pciide_mapregs_compat() with 105 * the real channel 106 */ 107 if (pa->pa_function == 1) { 108 sc->sc_cy_compatchan = 0; 109 } else if (pa->pa_function == 2) { 110 sc->sc_cy_compatchan = 1; 111 } else { 112 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 113 "unexpected PCI function %d\n", pa->pa_function); 114 return; 115 } 116 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 117 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 118 "bus-master DMA support present\n"); 119 pciide_mapreg_dma(sc, pa); 120 } else { 121 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 122 "hardware does not support DMA\n"); 123 sc->sc_dma_ok = 0; 124 } 125 126 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 127 if (sc->sc_cy_handle == NULL) { 128 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 129 "unable to map hyperCache control registers\n"); 130 sc->sc_dma_ok = 0; 131 } 132 133 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 134 if (sc->sc_dma_ok) { 135 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 136 sc->sc_wdcdev.irqack = pciide_irqack; 137 } 138 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 139 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 140 sc->sc_wdcdev.sc_atac.atac_set_modes = cy693_setup_channel; 141 142 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 143 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 144 sc->sc_wdcdev.wdc_maxdrives = 2; 145 146 wdc_allocate_regs(&sc->sc_wdcdev); 147 148 /* Only one channel for this chip; if we are here it's enabled */ 149 cp = &sc->pciide_channels[0]; 150 sc->wdc_chanarray[0] = &cp->ata_channel; 151 cp->name = PCIIDE_CHANNEL_NAME(0); 152 cp->ata_channel.ch_channel = 0; 153 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 154 cp->ata_channel.ch_queue = 155 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 156 if (cp->ata_channel.ch_queue == NULL) { 157 aprint_error("%s primary channel: " 158 "can't allocate memory for command queue", 159 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 160 return; 161 } 162 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 163 "primary channel %s to ", 164 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 165 "configured" : "wired"); 166 if (interface & PCIIDE_INTERFACE_PCI(0)) { 167 aprint_normal("native-PCI mode\n"); 168 pciide_mapregs_native(pa, cp, pciide_pci_intr); 169 } else { 170 aprint_normal("compatibility mode\n"); 171 pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan); 172 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 173 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan); 174 } 175 wdcattach(&cp->ata_channel); 176 } 177 178 static void 179 cy693_setup_channel(struct ata_channel *chp) 180 { 181 struct ata_drive_datas *drvp; 182 int drive; 183 u_int32_t cy_cmd_ctrl; 184 u_int32_t idedma_ctl; 185 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 186 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 187 int dma_mode = -1; 188 189 ATADEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 190 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 191 192 cy_cmd_ctrl = idedma_ctl = 0; 193 194 /* setup DMA if needed */ 195 pciide_channel_dma_setup(cp); 196 197 for (drive = 0; drive < 2; drive++) { 198 drvp = &chp->ch_drive[drive]; 199 /* If no drive, skip */ 200 if (drvp->drive_type == ATA_DRIVET_NONE) 201 continue; 202 /* add timing values, setup DMA if needed */ 203 if (drvp->drive_flags & ATA_DRIVE_DMA) { 204 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 205 /* use Multiword DMA */ 206 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 207 dma_mode = drvp->DMA_mode; 208 } 209 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 210 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 211 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 212 CY_CMD_CTRL_IOW_REC_OFF(drive)); 213 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 214 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 215 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 216 CY_CMD_CTRL_IOR_REC_OFF(drive)); 217 } 218 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 219 chp->ch_drive[0].DMA_mode = dma_mode; 220 chp->ch_drive[1].DMA_mode = dma_mode; 221 222 if (dma_mode == -1) 223 dma_mode = 0; 224 225 if (sc->sc_cy_handle != NULL) { 226 /* Note: `multiple' is implied. */ 227 cy82c693_write(sc->sc_cy_handle, 228 (sc->sc_cy_compatchan == 0) ? 229 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 230 } 231 232 if (idedma_ctl != 0) { 233 /* Add software bits in status register */ 234 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 235 idedma_ctl); 236 } 237 ATADEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 238 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 239 } 240
Indexes created Sat Oct 18 23:09:54 GMT 2025