cz.c revision 1.16.4.1
1 /* $NetBSD: cz.c,v 1.16.4.1 2001/09/07 04:45:27 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej (at) zembu.com> 8 * Bill Studenmund <wrstuden (at) zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only utilize RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/proc.h> 78 #include <sys/device.h> 79 #include <sys/malloc.h> 80 #include <sys/tty.h> 81 #include <sys/conf.h> 82 #include <sys/time.h> 83 #include <sys/kernel.h> 84 #include <sys/fcntl.h> 85 #include <sys/syslog.h> 86 #include <sys/vnode.h> 87 88 #include <sys/callout.h> 89 90 #include <miscfs/specfs/specdev.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/czreg.h> 96 97 #include <dev/pci/plx9060reg.h> 98 #include <dev/pci/plx9060var.h> 99 100 #include <dev/microcode/cyclades-z/cyzfirm.h> 101 102 #define CZ_DRIVER_VERSION 0x20000411 103 104 #define CZ_POLL_MS 20 105 106 /* These are the interrupts we always use. */ 107 #define CZ_INTERRUPTS \ 108 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 109 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 110 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 111 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 112 113 /* 114 * cztty_softc: 115 * 116 * Per-channel (TTY) state. 117 */ 118 struct cztty_softc { 119 struct cz_softc *sc_parent; 120 struct tty *sc_tty; 121 122 struct callout sc_diag_ch; 123 124 int sc_channel; /* Also used to flag unattached chan */ 125 #define CZTTY_CHANNEL_DEAD -1 126 127 bus_space_tag_t sc_chan_st; /* channel space tag */ 128 bus_space_handle_t sc_chan_sh; /* channel space handle */ 129 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 130 131 u_int sc_overflows, 132 sc_parity_errors, 133 sc_framing_errors, 134 sc_errors; 135 136 int sc_swflags; 137 138 u_int32_t sc_rs_control_dtr, 139 sc_chanctl_hw_flow, 140 sc_chanctl_comm_baud, 141 sc_chanctl_rs_control, 142 sc_chanctl_comm_data_l, 143 sc_chanctl_comm_parity; 144 }; 145 146 /* 147 * cz_softc: 148 * 149 * Per-board state. 150 */ 151 struct cz_softc { 152 struct device cz_dev; /* generic device info */ 153 struct plx9060_config cz_plx; /* PLX 9060 config info */ 154 bus_space_tag_t cz_win_st; /* window space tag */ 155 bus_space_handle_t cz_win_sh; /* window space handle */ 156 struct callout cz_callout; /* callout for polling-mode */ 157 158 void *cz_ih; /* interrupt handle */ 159 160 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 161 int cz_nchannels; /* number of channels */ 162 int cz_nopenchan; /* number of open channels */ 163 struct cztty_softc *cz_ports; /* our array of ports */ 164 165 bus_addr_t cz_fwctl; /* offset of firmware control */ 166 }; 167 168 int cz_match(struct device *, struct cfdata *, void *); 169 void cz_attach(struct device *, struct device *, void *); 170 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 171 172 struct cfattach cz_ca = { 173 sizeof(struct cz_softc), cz_match, cz_attach 174 }; 175 176 void cz_reset_board(struct cz_softc *); 177 int cz_load_firmware(struct cz_softc *); 178 179 int cz_intr(void *); 180 void cz_poll(void *); 181 int cztty_transmit(struct cztty_softc *, struct tty *); 182 int cztty_receive(struct cztty_softc *, struct tty *); 183 184 struct cztty_softc * cztty_getttysoftc(dev_t dev); 185 int cztty_findmajor(void); 186 int cztty_major; 187 int cztty_attached_ttys; 188 int cz_timeout_ticks; 189 190 cdev_decl(cztty); 191 192 void czttystart(struct tty *tp); 193 int czttyparam(struct tty *tp, struct termios *t); 194 void cztty_shutdown(struct cztty_softc *sc); 195 void cztty_modem(struct cztty_softc *sc, int onoff); 196 void cztty_break(struct cztty_softc *sc, int onoff); 197 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 198 int cztty_to_tiocm(struct cztty_softc *sc); 199 void cztty_diag(void *arg); 200 201 extern struct cfdriver cz_cd; 202 203 /* Macros to clear/set/test flags. */ 204 #define SET(t, f) (t) |= (f) 205 #define CLR(t, f) (t) &= ~(f) 206 #define ISSET(t, f) ((t) & (f)) 207 208 /* 209 * Macros to read and write the PLX. 210 */ 211 #define CZ_PLX_READ(cz, reg) \ 212 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 213 #define CZ_PLX_WRITE(cz, reg, val) \ 214 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 215 (reg), (val)) 216 217 /* 218 * Macros to read and write the FPGA. We must already be in the FPGA 219 * window for this. 220 */ 221 #define CZ_FPGA_READ(cz, reg) \ 222 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 223 #define CZ_FPGA_WRITE(cz, reg, val) \ 224 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 225 226 /* 227 * Macros to read and write the firmware control structures in board RAM. 228 */ 229 #define CZ_FWCTL_READ(cz, off) \ 230 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 231 (cz)->cz_fwctl + (off)) 232 233 #define CZ_FWCTL_WRITE(cz, off, val) \ 234 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 235 (cz)->cz_fwctl + (off), (val)) 236 237 /* 238 * Convenience macros for cztty routines. PLX window MUST be to RAM. 239 */ 240 #define CZTTY_CHAN_READ(sc, off) \ 241 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 242 243 #define CZTTY_CHAN_WRITE(sc, off, val) \ 244 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 245 (off), (val)) 246 247 #define CZTTY_BUF_READ(sc, off) \ 248 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 249 250 #define CZTTY_BUF_WRITE(sc, off, val) \ 251 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 252 (off), (val)) 253 254 /* 255 * Convenience macros. 256 */ 257 #define CZ_WIN_RAM(cz) \ 258 do { \ 259 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 260 delay(100); \ 261 } while (0) 262 263 #define CZ_WIN_FPGA(cz) \ 264 do { \ 265 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 266 delay(100); \ 267 } while (0) 268 269 /***************************************************************************** 270 * Cyclades-Z controller code starts here... 271 *****************************************************************************/ 272 273 /* 274 * cz_match: 275 * 276 * Determine if the given PCI device is a Cyclades-Z board. 277 */ 278 int 279 cz_match(struct device *parent, 280 struct cfdata *match, 281 void *aux) 282 { 283 struct pci_attach_args *pa = aux; 284 285 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 286 switch (PCI_PRODUCT(pa->pa_id)) { 287 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 288 return (1); 289 } 290 } 291 292 return (0); 293 } 294 295 /* 296 * cz_attach: 297 * 298 * A Cyclades-Z board was found; attach it. 299 */ 300 void 301 cz_attach(struct device *parent, 302 struct device *self, 303 void *aux) 304 { 305 struct cz_softc *cz = (void *) self; 306 struct pci_attach_args *pa = aux; 307 pci_intr_handle_t ih; 308 const char *intrstr = NULL; 309 struct cztty_softc *sc; 310 struct tty *tp; 311 int i; 312 313 printf(": Cyclades-Z multiport serial\n"); 314 315 cz->cz_plx.plx_pc = pa->pa_pc; 316 cz->cz_plx.plx_tag = pa->pa_tag; 317 318 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 319 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 320 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 321 printf("%s: unable to map PLX registers\n", 322 cz->cz_dev.dv_xname); 323 return; 324 } 325 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 326 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 327 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 328 printf("%s: unable to map device window\n", 329 cz->cz_dev.dv_xname); 330 return; 331 } 332 333 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 334 cz->cz_nopenchan = 0; 335 336 /* 337 * Make sure that the board is completely stopped. 338 */ 339 CZ_WIN_FPGA(cz); 340 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 341 342 /* 343 * Load the board's firmware. 344 */ 345 if (cz_load_firmware(cz) != 0) 346 return; 347 348 /* 349 * Now that we're ready to roll, map and establish the interrupt 350 * handler. 351 */ 352 if (pci_intr_map(pa, &ih) != 0) { 353 /* 354 * The common case is for Cyclades-Z boards to run 355 * in polling mode, and thus not have an interrupt 356 * mapped for them. Don't bother reporting that 357 * the interrupt is not mappable, since this isn't 358 * really an error. 359 */ 360 cz->cz_ih = NULL; 361 goto polling_mode; 362 } else { 363 intrstr = pci_intr_string(pa->pa_pc, ih); 364 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 365 cz_intr, cz); 366 } 367 if (cz->cz_ih == NULL) { 368 printf("%s: unable to establish interrupt", 369 cz->cz_dev.dv_xname); 370 if (intrstr != NULL) 371 printf(" at %s", intrstr); 372 printf("\n"); 373 /* We will fall-back on polling mode. */ 374 } else 375 printf("%s: interrupting at %s\n", 376 cz->cz_dev.dv_xname, intrstr); 377 378 polling_mode: 379 if (cz->cz_ih == NULL) { 380 callout_init(&cz->cz_callout); 381 if (cz_timeout_ticks == 0) 382 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 383 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 384 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 385 cz_timeout_ticks == 1 ? "" : "s"); 386 } 387 388 if (cztty_major == 0) 389 cztty_major = cztty_findmajor(); 390 /* 391 * Allocate sufficient pointers for the children and 392 * attach them. Set all ports to a reasonable initial 393 * configuration while we're at it: 394 * 395 * disabled 396 * 8N1 397 * default baud rate 398 * hardware flow control. 399 */ 400 CZ_WIN_RAM(cz); 401 402 if (cz->cz_nchannels == 0) { 403 /* No channels? No more work to do! */ 404 return; 405 } 406 407 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 408 M_DEVBUF, M_WAITOK); 409 cztty_attached_ttys += cz->cz_nchannels; 410 memset(cz->cz_ports, 0, 411 sizeof(struct cztty_softc) * cz->cz_nchannels); 412 413 for (i = 0; i < cz->cz_nchannels; i++) { 414 sc = &cz->cz_ports[i]; 415 416 sc->sc_channel = i; 417 sc->sc_chan_st = cz->cz_win_st; 418 sc->sc_parent = cz; 419 420 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 421 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 422 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 423 printf("%s: unable to subregion channel %d control\n", 424 cz->cz_dev.dv_xname, i); 425 sc->sc_channel = CZTTY_CHANNEL_DEAD; 426 continue; 427 } 428 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 429 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 430 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 431 printf("%s: unable to subregion channel %d buffer\n", 432 cz->cz_dev.dv_xname, i); 433 sc->sc_channel = CZTTY_CHANNEL_DEAD; 434 continue; 435 } 436 437 callout_init(&sc->sc_diag_ch); 438 439 tp = ttymalloc(); 440 tp->t_oproc = czttystart; 441 tp->t_param = czttyparam; 442 tty_attach(tp); 443 444 sc->sc_tty = tp; 445 446 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 447 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 448 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 449 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 450 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 451 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 452 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 453 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 454 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 455 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 456 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 457 } 458 } 459 460 /* 461 * cz_reset_board: 462 * 463 * Reset the board via the PLX. 464 */ 465 void 466 cz_reset_board(struct cz_softc *cz) 467 { 468 u_int32_t reg; 469 470 reg = CZ_PLX_READ(cz, PLX_CONTROL); 471 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 472 delay(1000); 473 474 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 475 delay(1000); 476 477 /* Now reload the PLX from its EEPROM. */ 478 reg = CZ_PLX_READ(cz, PLX_CONTROL); 479 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 480 delay(1000); 481 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 482 } 483 484 /* 485 * cz_load_firmware: 486 * 487 * Load the ZFIRM firmware into the board's RAM and start it 488 * running. 489 */ 490 int 491 cz_load_firmware(struct cz_softc *cz) 492 { 493 struct zfirm_header *zfh; 494 struct zfirm_config *zfc; 495 struct zfirm_block *zfb, *zblocks; 496 const u_int8_t *cp; 497 const char *board; 498 u_int32_t fid; 499 int i, j, nconfigs, nblocks, nbytes; 500 501 zfh = (struct zfirm_header *) cycladesz_firmware; 502 503 /* Find the config header. */ 504 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 505 printf("%s: bad ZFIRM config offset: 0x%x\n", 506 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 507 return (EIO); 508 } 509 zfc = (struct zfirm_config *)(cycladesz_firmware + 510 le32toh(zfh->zfh_configoff)); 511 nconfigs = le32toh(zfh->zfh_nconfig); 512 513 /* Locate the correct configuration for our board. */ 514 for (i = 0; i < nconfigs; i++, zfc++) { 515 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 516 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 517 break; 518 } 519 if (i == nconfigs) { 520 printf("%s: unable to locate config header\n", 521 cz->cz_dev.dv_xname); 522 return (EIO); 523 } 524 525 nblocks = le32toh(zfc->zfc_nblocks); 526 zblocks = (struct zfirm_block *)(cycladesz_firmware + 527 le32toh(zfh->zfh_blockoff)); 528 529 /* 530 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 531 * necessary. 532 */ 533 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 534 #if 0 535 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 536 #endif 537 ) { 538 #ifdef CZ_DEBUG 539 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 540 #endif 541 CZ_WIN_FPGA(cz); 542 for (i = 0; i < nblocks; i++) { 543 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 544 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 545 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 546 nbytes = le32toh(zfb->zfb_size); 547 cp = &cycladesz_firmware[ 548 le32toh(zfb->zfb_fileoff)]; 549 for (j = 0; j < nbytes; j++, cp++) { 550 bus_space_write_1(cz->cz_win_st, 551 cz->cz_win_sh, 0, *cp); 552 /* FPGA needs 30-100us to settle. */ 553 delay(10); 554 } 555 } 556 } 557 #ifdef CZ_DEBUG 558 printf("done\n"); 559 #endif 560 } 561 562 /* Now load the firmware. */ 563 CZ_WIN_RAM(cz); 564 565 for (i = 0; i < nblocks; i++) { 566 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 567 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 568 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 569 const u_int32_t *lp; 570 u_int32_t ro = le32toh(zfb->zfb_ramoff); 571 nbytes = le32toh(zfb->zfb_size); 572 lp = (const u_int32_t *) 573 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 574 for (j = 0; j < nbytes; j += 4, lp++) { 575 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 576 ro + j, le32toh(*lp)); 577 delay(10); 578 } 579 } 580 } 581 582 /* Now restart the MIPS. */ 583 CZ_WIN_FPGA(cz); 584 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 585 586 /* Wait for the MIPS to start, then report the results. */ 587 CZ_WIN_RAM(cz); 588 589 #ifdef CZ_DEBUG 590 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 591 #endif 592 for (i = 0; i < 100; i++) { 593 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 594 ZFIRM_SIG_OFF); 595 if (fid == ZFIRM_SIG) { 596 /* MIPS has booted. */ 597 break; 598 } else if (fid == ZFIRM_HLT) { 599 /* 600 * The MIPS has halted, usually due to a power 601 * shortage on the expansion module. 602 */ 603 printf("%s: MIPS halted; possible power supply " 604 "problem\n", cz->cz_dev.dv_xname); 605 return (EIO); 606 } else { 607 #ifdef CZ_DEBUG 608 if ((i % 8) == 0) 609 printf("."); 610 #endif 611 delay(250000); 612 } 613 } 614 #ifdef CZ_DEBUG 615 printf("\n"); 616 #endif 617 if (i == 100) { 618 CZ_WIN_FPGA(cz); 619 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 620 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 621 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 622 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 623 CZ_FPGA_READ(cz, FPGA_VERSION)); 624 return (EIO); 625 } 626 627 /* 628 * Locate the firmware control structures. 629 */ 630 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 631 ZFIRM_CTRLADDR_OFF); 632 #ifdef CZ_DEBUG 633 printf("%s: FWCTL structure at offset 0x%08lx\n", 634 cz->cz_dev.dv_xname, cz->cz_fwctl); 635 #endif 636 637 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 638 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 639 640 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 641 642 switch (cz->cz_mailbox0) { 643 case MAILBOX0_8Zo_V1: 644 board = "Cyclades-8Zo ver. 1"; 645 break; 646 647 case MAILBOX0_8Zo_V2: 648 board = "Cyclades-8Zo ver. 2"; 649 break; 650 651 case MAILBOX0_Ze_V1: 652 board = "Cyclades-Ze"; 653 break; 654 655 default: 656 board = "unknown Cyclades Z-series"; 657 break; 658 } 659 660 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 661 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 662 if (cz->cz_nchannels == 0) 663 printf("no channels attached, "); 664 else 665 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 666 cz->cz_nchannels, cztty_attached_ttys, 667 cztty_attached_ttys + (cz->cz_nchannels - 1)); 668 printf("firmware %x.%x.%x\n", 669 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 670 671 return (0); 672 } 673 674 /* 675 * cz_poll: 676 * 677 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 678 * ms. 679 */ 680 void 681 cz_poll(void *arg) 682 { 683 int s = spltty(); 684 struct cz_softc *cz = arg; 685 686 cz_intr(cz); 687 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 688 689 splx(s); 690 } 691 692 /* 693 * cz_intr: 694 * 695 * Interrupt service routine. 696 * 697 * We either are receiving an interrupt directly from the board, or we are 698 * in polling mode and it's time to poll. 699 */ 700 int 701 cz_intr(void *arg) 702 { 703 int rval = 0; 704 u_int command, channel, param; 705 struct cz_softc *cz = arg; 706 struct cztty_softc *sc; 707 struct tty *tp; 708 709 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 710 rval = 1; 711 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 712 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 713 714 /* now clear this interrupt, posslibly enabling another */ 715 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 716 717 if (cz->cz_ports == NULL) { 718 #ifdef CZ_DEBUG 719 printf("%s: interrupt on channel %d, but no channels\n", 720 cz->cz_dev.dv_xname, channel); 721 #endif 722 continue; 723 } 724 725 sc = &cz->cz_ports[channel]; 726 727 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 728 break; 729 730 tp = sc->sc_tty; 731 732 switch (command) { 733 case C_CM_TXFEMPTY: /* transmit cases */ 734 case C_CM_TXBEMPTY: 735 case C_CM_TXLOWWM: 736 case C_CM_INTBACK: 737 if (!ISSET(tp->t_state, TS_ISOPEN)) { 738 #ifdef CZ_DEBUG 739 printf("%s: tx intr on closed channel %d\n", 740 cz->cz_dev.dv_xname, channel); 741 #endif 742 break; 743 } 744 745 if (cztty_transmit(sc, tp)) { 746 /* 747 * Do wakeup stuff here. 748 */ 749 ttwakeup(tp); 750 wakeup(tp); 751 } 752 break; 753 754 case C_CM_RXNNDT: /* receive cases */ 755 case C_CM_RXHIWM: 756 case C_CM_INTBACK2: /* from restart ?? */ 757 #if 0 758 case C_CM_ICHAR: 759 #endif 760 if (!ISSET(tp->t_state, TS_ISOPEN)) { 761 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 762 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 763 break; 764 } 765 766 if (cztty_receive(sc, tp)) { 767 /* 768 * Do wakeup stuff here. 769 */ 770 ttwakeup(tp); 771 wakeup(tp); 772 } 773 break; 774 775 case C_CM_MDCD: 776 if (!ISSET(tp->t_state, TS_ISOPEN)) 777 break; 778 779 (void) (*tp->t_linesw->l_modem)(tp, 780 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 781 CHNCTL_RS_STATUS))); 782 break; 783 784 case C_CM_MDSR: 785 case C_CM_MRI: 786 case C_CM_MCTS: 787 case C_CM_MRTS: 788 break; 789 790 case C_CM_IOCTLW: 791 break; 792 793 case C_CM_PR_ERROR: 794 sc->sc_parity_errors++; 795 goto error_common; 796 797 case C_CM_FR_ERROR: 798 sc->sc_framing_errors++; 799 goto error_common; 800 801 case C_CM_OVR_ERROR: 802 sc->sc_overflows++; 803 error_common: 804 if (sc->sc_errors++ == 0) 805 callout_reset(&sc->sc_diag_ch, 60 * hz, 806 cztty_diag, sc); 807 break; 808 809 case C_CM_RXBRK: 810 if (!ISSET(tp->t_state, TS_ISOPEN)) 811 break; 812 813 /* 814 * A break is a \000 character with TTY_FE error 815 * flags set. So TTY_FE by itself works. 816 */ 817 (*tp->t_linesw->l_rint)(TTY_FE, tp); 818 ttwakeup(tp); 819 wakeup(tp); 820 break; 821 822 default: 823 #ifdef CZ_DEBUG 824 printf("%s: channel %d: Unknown interrupt 0x%x\n", 825 cz->cz_dev.dv_xname, sc->sc_channel, command); 826 #endif 827 break; 828 } 829 } 830 831 return (rval); 832 } 833 834 /* 835 * cz_wait_pci_doorbell: 836 * 837 * Wait for the pci doorbell to be clear - wait for pending 838 * activity to drain. 839 */ 840 int 841 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 842 { 843 int error; 844 845 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 846 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 847 if ((error != 0) && (error != EWOULDBLOCK)) 848 return (error); 849 } 850 return (0); 851 } 852 853 /***************************************************************************** 854 * Cyclades-Z TTY code starts here... 855 *****************************************************************************/ 856 857 #define CZTTYDIALOUT_MASK 0x80000 858 859 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 860 #define CZTTY_CZ(sc) ((sc)->sc_parent) 861 862 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 863 864 struct cztty_softc * 865 cztty_getttysoftc(dev_t dev) 866 { 867 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 868 struct cz_softc *cz; 869 870 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 871 k = j; 872 cz = device_lookup(&cz_cd, i); 873 if (cz == NULL) 874 continue; 875 if (cz->cz_ports == NULL) 876 continue; 877 j += cz->cz_nchannels; 878 if (j > u) 879 break; 880 } 881 882 if (i >= cz_cd.cd_ndevs) 883 return (NULL); 884 else 885 return (&cz->cz_ports[u - k]); 886 } 887 888 int 889 cztty_findmajor(void) 890 { 891 int maj; 892 893 for (maj = 0; maj < nchrdev; maj++) { 894 if (cdevsw[maj].d_open == czttyopen) 895 break; 896 } 897 898 return (maj == nchrdev) ? 0 : maj; 899 } 900 901 /* 902 * czttytty: 903 * 904 * Return a pointer to our tty. 905 */ 906 struct tty * 907 czttytty(struct vnode *devvp) 908 { 909 struct cztty_softc *sc = devvp->v_devcookie; 910 911 #ifdef DIAGNOSTIC 912 if (sc == NULL) 913 panic("czttytty"); 914 #endif 915 916 return (sc->sc_tty); 917 } 918 919 /* 920 * cztty_shutdown: 921 * 922 * Shut down a port. 923 */ 924 void 925 cztty_shutdown(struct cztty_softc *sc) 926 { 927 struct cz_softc *cz = CZTTY_CZ(sc); 928 struct tty *tp = sc->sc_tty; 929 int s; 930 931 s = spltty(); 932 933 /* Clear any break condition set with TIOCSBRK. */ 934 cztty_break(sc, 0); 935 936 /* 937 * Hang up if necessary. Wait a bit, so the other side has time to 938 * notice even if we immediately open the port again. 939 */ 940 if (ISSET(tp->t_cflag, HUPCL)) { 941 cztty_modem(sc, 0); 942 (void) tsleep(tp, TTIPRI, ttclos, hz); 943 } 944 945 /* Disable the channel. */ 946 cz_wait_pci_doorbell(cz, "czdis"); 947 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 948 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 949 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 950 951 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 952 #ifdef CZ_DEBUG 953 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 954 #endif 955 callout_stop(&cz->cz_callout); 956 } 957 958 splx(s); 959 } 960 961 /* 962 * czttyopen: 963 * 964 * Open a Cyclades-Z serial port. 965 */ 966 int 967 czttyopen(struct vnode *devvp, int flags, int mode, struct proc *p) 968 { 969 struct cztty_softc *sc = CZTTY_SOFTC(devvp->v_rdev); 970 struct cz_softc *cz; 971 struct tty *tp; 972 int s, error; 973 974 if (sc == NULL) 975 return (ENXIO); 976 977 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 978 return (ENXIO); 979 980 devvp->v_devcookie = sc; 981 982 cz = CZTTY_CZ(sc); 983 tp = sc->sc_tty; 984 985 if (ISSET(tp->t_state, TS_ISOPEN) && 986 ISSET(tp->t_state, TS_XCLUDE) && 987 p->p_ucred->cr_uid != 0) 988 return (EBUSY); 989 990 s = spltty(); 991 992 /* 993 * Do the following iff this is a first open. 994 */ 995 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 996 struct termios t; 997 998 tp->t_devvp = devvp; 999 1000 /* If we're turning things on, enable interrupts */ 1001 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 1002 #ifdef CZ_DEBUG 1003 printf("%s: Enabling polling.\n", 1004 cz->cz_dev.dv_xname); 1005 #endif 1006 callout_reset(&cz->cz_callout, cz_timeout_ticks, 1007 cz_poll, cz); 1008 } 1009 1010 /* 1011 * Enable the channel. Don't actually ring the 1012 * doorbell here; czttyparam() will do it for us. 1013 */ 1014 cz_wait_pci_doorbell(cz, "czopen"); 1015 1016 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1017 1018 /* 1019 * Initialize the termios status to the defaults. Add in the 1020 * sticky bits from TIOCSFLAGS. 1021 */ 1022 t.c_ispeed = 0; 1023 t.c_ospeed = TTYDEF_SPEED; 1024 t.c_cflag = TTYDEF_CFLAG; 1025 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1026 SET(t.c_cflag, CLOCAL); 1027 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1028 SET(t.c_cflag, CRTSCTS); 1029 1030 /* 1031 * Reset the input and output rings. Do this before 1032 * we call czttyparam(), as that function enables 1033 * the channel. 1034 */ 1035 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1036 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1037 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1038 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1039 1040 /* Make sure czttyparam() will see changes. */ 1041 tp->t_ospeed = 0; 1042 (void) czttyparam(tp, &t); 1043 tp->t_iflag = TTYDEF_IFLAG; 1044 tp->t_oflag = TTYDEF_OFLAG; 1045 tp->t_lflag = TTYDEF_LFLAG; 1046 ttychars(tp); 1047 ttsetwater(tp); 1048 1049 /* 1050 * Turn on DTR. We must always do this, even if carrier is not 1051 * present, because otherwise we'd have to use TIOCSDTR 1052 * immediately after setting CLOCAL, which applications do not 1053 * expect. We always assert DTR while the device is open 1054 * unless explicitly requested to deassert it. 1055 */ 1056 cztty_modem(sc, 1); 1057 } 1058 1059 splx(s); 1060 1061 error = ttyopen(tp, CZTTY_DIALOUT(devvp->v_rdev), 1062 ISSET(flags, O_NONBLOCK)); 1063 if (error) 1064 goto bad; 1065 1066 error = (*tp->t_linesw->l_open)(devvp, tp); 1067 if (error) 1068 goto bad; 1069 1070 return (0); 1071 1072 bad: 1073 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1074 /* 1075 * We failed to open the device, and nobody else had it opened. 1076 * Clean up the state as appropriate. 1077 */ 1078 cztty_shutdown(sc); 1079 } 1080 1081 return (error); 1082 } 1083 1084 /* 1085 * czttyclose: 1086 * 1087 * Close a Cyclades-Z serial port. 1088 */ 1089 int 1090 czttyclose(struct vnode *devvp, int flags, int mode, struct proc *p) 1091 { 1092 struct cztty_softc *sc = devvp->v_devcookie; 1093 struct tty *tp = sc->sc_tty; 1094 1095 /* XXX This is for cons.c. */ 1096 if (!ISSET(tp->t_state, TS_ISOPEN)) 1097 return (0); 1098 1099 (*tp->t_linesw->l_close)(tp, flags); 1100 ttyclose(tp); 1101 1102 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1103 /* 1104 * Although we got a last close, the device may still be in 1105 * use; e.g. if this was the dialout node, and there are still 1106 * processes waiting for carrier on the non-dialout node. 1107 */ 1108 cztty_shutdown(sc); 1109 } 1110 1111 return (0); 1112 } 1113 1114 /* 1115 * czttyread: 1116 * 1117 * Read from a Cyclades-Z serial port. 1118 */ 1119 int 1120 czttyread(struct vnode *devvp, struct uio *uio, int flags) 1121 { 1122 struct cztty_softc *sc = devvp->v_devcookie; 1123 struct tty *tp = sc->sc_tty; 1124 1125 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1126 } 1127 1128 /* 1129 * czttywrite: 1130 * 1131 * Write to a Cyclades-Z serial port. 1132 */ 1133 int 1134 czttywrite(struct vnode *devvp, struct uio *uio, int flags) 1135 { 1136 struct cztty_softc *sc = devvp->v_devcookie; 1137 struct tty *tp = sc->sc_tty; 1138 1139 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1140 } 1141 1142 /* 1143 * czttypoll: 1144 * 1145 * Poll a Cyclades-Z serial port. 1146 */ 1147 int 1148 czttypoll(devvp, events, p) 1149 struct vnode *devvp; 1150 int events; 1151 struct proc *p; 1152 { 1153 struct cztty_softc *sc = devvp->v_devcookie; 1154 struct tty *tp = sc->sc_tty; 1155 1156 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1157 } 1158 1159 /* 1160 * czttyioctl: 1161 * 1162 * Perform a control operation on a Cyclades-Z serial port. 1163 */ 1164 int 1165 czttyioctl(struct vnode *devvp, u_long cmd, caddr_t data, int flag, 1166 struct proc *p) 1167 { 1168 struct cztty_softc *sc = devvp->v_devcookie; 1169 struct tty *tp = sc->sc_tty; 1170 int s, error; 1171 1172 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 1173 if (error >= 0) 1174 return (error); 1175 1176 error = ttioctl(tp, cmd, data, flag, p); 1177 if (error >= 0) 1178 return (error); 1179 1180 error = 0; 1181 1182 s = spltty(); 1183 1184 switch (cmd) { 1185 case TIOCSBRK: 1186 cztty_break(sc, 1); 1187 break; 1188 1189 case TIOCCBRK: 1190 cztty_break(sc, 0); 1191 break; 1192 1193 case TIOCGFLAGS: 1194 *(int *)data = sc->sc_swflags; 1195 break; 1196 1197 case TIOCSFLAGS: 1198 error = suser(p->p_ucred, &p->p_acflag); 1199 if (error) 1200 break; 1201 sc->sc_swflags = *(int *)data; 1202 break; 1203 1204 case TIOCSDTR: 1205 cztty_modem(sc, 1); 1206 break; 1207 1208 case TIOCCDTR: 1209 cztty_modem(sc, 0); 1210 break; 1211 1212 case TIOCMSET: 1213 case TIOCMBIS: 1214 case TIOCMBIC: 1215 tiocm_to_cztty(sc, cmd, *(int *)data); 1216 break; 1217 1218 case TIOCMGET: 1219 *(int *)data = cztty_to_tiocm(sc); 1220 break; 1221 1222 default: 1223 error = ENOTTY; 1224 break; 1225 } 1226 1227 splx(s); 1228 1229 return (error); 1230 } 1231 1232 /* 1233 * cztty_break: 1234 * 1235 * Set or clear BREAK on a port. 1236 */ 1237 void 1238 cztty_break(struct cztty_softc *sc, int onoff) 1239 { 1240 struct cz_softc *cz = CZTTY_CZ(sc); 1241 1242 cz_wait_pci_doorbell(cz, "czbreak"); 1243 1244 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1245 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1246 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1247 } 1248 1249 /* 1250 * cztty_modem: 1251 * 1252 * Set or clear DTR on a port. 1253 */ 1254 void 1255 cztty_modem(struct cztty_softc *sc, int onoff) 1256 { 1257 struct cz_softc *cz = CZTTY_CZ(sc); 1258 1259 if (sc->sc_rs_control_dtr == 0) 1260 return; 1261 1262 cz_wait_pci_doorbell(cz, "czmod"); 1263 1264 if (onoff) 1265 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1266 else 1267 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1268 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1269 1270 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1271 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1272 } 1273 1274 /* 1275 * tiocm_to_cztty: 1276 * 1277 * Process TIOCM* ioctls. 1278 */ 1279 void 1280 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1281 { 1282 struct cz_softc *cz = CZTTY_CZ(sc); 1283 u_int32_t czttybits; 1284 1285 czttybits = 0; 1286 if (ISSET(ttybits, TIOCM_DTR)) 1287 SET(czttybits, C_RS_DTR); 1288 if (ISSET(ttybits, TIOCM_RTS)) 1289 SET(czttybits, C_RS_RTS); 1290 1291 cz_wait_pci_doorbell(cz, "cztiocm"); 1292 1293 switch (how) { 1294 case TIOCMBIC: 1295 CLR(sc->sc_chanctl_rs_control, czttybits); 1296 break; 1297 1298 case TIOCMBIS: 1299 SET(sc->sc_chanctl_rs_control, czttybits); 1300 break; 1301 1302 case TIOCMSET: 1303 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1304 SET(sc->sc_chanctl_rs_control, czttybits); 1305 break; 1306 } 1307 1308 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1309 1310 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1311 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1312 } 1313 1314 /* 1315 * cztty_to_tiocm: 1316 * 1317 * Process the TIOCMGET ioctl. 1318 */ 1319 int 1320 cztty_to_tiocm(struct cztty_softc *sc) 1321 { 1322 struct cz_softc *cz = CZTTY_CZ(sc); 1323 u_int32_t rs_status, op_mode; 1324 int ttybits = 0; 1325 1326 cz_wait_pci_doorbell(cz, "cztty"); 1327 1328 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1329 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1330 1331 if (ISSET(rs_status, C_RS_RTS)) 1332 SET(ttybits, TIOCM_RTS); 1333 if (ISSET(rs_status, C_RS_CTS)) 1334 SET(ttybits, TIOCM_CTS); 1335 if (ISSET(rs_status, C_RS_DCD)) 1336 SET(ttybits, TIOCM_CAR); 1337 if (ISSET(rs_status, C_RS_DTR)) 1338 SET(ttybits, TIOCM_DTR); 1339 if (ISSET(rs_status, C_RS_RI)) 1340 SET(ttybits, TIOCM_RNG); 1341 if (ISSET(rs_status, C_RS_DSR)) 1342 SET(ttybits, TIOCM_DSR); 1343 1344 if (ISSET(op_mode, C_CH_ENABLE)) 1345 SET(ttybits, TIOCM_LE); 1346 1347 return (ttybits); 1348 } 1349 1350 /* 1351 * czttyparam: 1352 * 1353 * Set Cyclades-Z serial port parameters from termios. 1354 * 1355 * XXX Should just copy the whole termios after making 1356 * XXX sure all the changes could be done. 1357 */ 1358 int 1359 czttyparam(struct tty *tp, struct termios *t) 1360 { 1361 struct cztty_softc *sc = tp->t_devvp->v_devcookie; 1362 struct cz_softc *cz = CZTTY_CZ(sc); 1363 u_int32_t rs_status; 1364 int ospeed, cflag; 1365 1366 ospeed = t->c_ospeed; 1367 cflag = t->c_cflag; 1368 1369 /* Check requested parameters. */ 1370 if (ospeed < 0) 1371 return (EINVAL); 1372 if (t->c_ispeed && t->c_ispeed != ospeed) 1373 return (EINVAL); 1374 1375 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1376 SET(cflag, CLOCAL); 1377 CLR(cflag, HUPCL); 1378 } 1379 1380 /* 1381 * If there were no changes, don't do anything. This avoids dropping 1382 * input and improves performance when all we did was frob things like 1383 * VMIN and VTIME. 1384 */ 1385 if (tp->t_ospeed == ospeed && 1386 tp->t_cflag == cflag) 1387 return (0); 1388 1389 /* Data bits. */ 1390 sc->sc_chanctl_comm_data_l = 0; 1391 switch (t->c_cflag & CSIZE) { 1392 case CS5: 1393 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1394 break; 1395 1396 case CS6: 1397 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1398 break; 1399 1400 case CS7: 1401 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1402 break; 1403 1404 case CS8: 1405 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1406 break; 1407 } 1408 1409 /* Stop bits. */ 1410 if (t->c_cflag & CSTOPB) { 1411 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1412 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1413 else 1414 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1415 } else 1416 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1417 1418 /* Parity. */ 1419 if (t->c_cflag & PARENB) { 1420 if (t->c_cflag & PARODD) 1421 sc->sc_chanctl_comm_parity = C_PR_ODD; 1422 else 1423 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1424 } else 1425 sc->sc_chanctl_comm_parity = C_PR_NONE; 1426 1427 /* 1428 * Initialize flow control pins depending on the current flow control 1429 * mode. 1430 */ 1431 if (ISSET(t->c_cflag, CRTSCTS)) { 1432 sc->sc_rs_control_dtr = C_RS_DTR; 1433 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1434 } else if (ISSET(t->c_cflag, MDMBUF)) { 1435 sc->sc_rs_control_dtr = 0; 1436 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1437 } else { 1438 /* 1439 * If no flow control, then always set RTS. This will make 1440 * the other side happy if it mistakenly thinks we're doing 1441 * RTS/CTS flow control. 1442 */ 1443 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1444 sc->sc_chanctl_hw_flow = 0; 1445 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1446 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1447 else 1448 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1449 } 1450 1451 /* Baud rate. */ 1452 sc->sc_chanctl_comm_baud = ospeed; 1453 1454 /* Copy to tty. */ 1455 tp->t_ispeed = 0; 1456 tp->t_ospeed = t->c_ospeed; 1457 tp->t_cflag = t->c_cflag; 1458 1459 /* 1460 * Now load the channel control structure. 1461 */ 1462 1463 cz_wait_pci_doorbell(cz, "czparam"); 1464 1465 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1466 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1467 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1468 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1469 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1470 1471 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1472 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1473 1474 cz_wait_pci_doorbell(cz, "czparam"); 1475 1476 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1477 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1478 1479 cz_wait_pci_doorbell(cz, "czparam"); 1480 1481 /* 1482 * Update the tty layer's idea of the carrier bit, in case we changed 1483 * CLOCAL. We don't hang up here; we only do that by explicit 1484 * request. 1485 */ 1486 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1487 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1488 1489 return (0); 1490 } 1491 1492 /* 1493 * czttystart: 1494 * 1495 * Start or restart transmission. 1496 */ 1497 void 1498 czttystart(struct tty *tp) 1499 { 1500 struct cztty_softc *sc = tp->t_devvp->v_devcookie; 1501 int s; 1502 1503 s = spltty(); 1504 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1505 goto out; 1506 1507 if (tp->t_outq.c_cc <= tp->t_lowat) { 1508 if (ISSET(tp->t_state, TS_ASLEEP)) { 1509 CLR(tp->t_state, TS_ASLEEP); 1510 wakeup(&tp->t_outq); 1511 } 1512 selwakeup(&tp->t_wsel); 1513 if (tp->t_outq.c_cc == 0) 1514 goto out; 1515 } 1516 1517 cztty_transmit(sc, tp); 1518 out: 1519 splx(s); 1520 } 1521 1522 /* 1523 * czttystop: 1524 * 1525 * Stop output, e.g., for ^S or output flush. 1526 */ 1527 void 1528 czttystop(struct tty *tp, int flag) 1529 { 1530 1531 /* 1532 * XXX We don't do anything here, yet. Mostly, I don't know 1533 * XXX exactly how this should be implemented on this device. 1534 * XXX We've given a big chunk of data to the MIPS already, 1535 * XXX and I don't know how we request the MIPS to stop sending 1536 * XXX the data. So, punt for now. --thorpej 1537 */ 1538 } 1539 1540 /* 1541 * cztty_diag: 1542 * 1543 * Issue a scheduled diagnostic message. 1544 */ 1545 void 1546 cztty_diag(void *arg) 1547 { 1548 struct cztty_softc *sc = arg; 1549 struct cz_softc *cz = CZTTY_CZ(sc); 1550 u_int overflows, parity_errors, framing_errors; 1551 int s; 1552 1553 s = spltty(); 1554 1555 overflows = sc->sc_overflows; 1556 sc->sc_overflows = 0; 1557 1558 parity_errors = sc->sc_parity_errors; 1559 sc->sc_parity_errors = 0; 1560 1561 framing_errors = sc->sc_framing_errors; 1562 sc->sc_framing_errors = 0; 1563 1564 sc->sc_errors = 0; 1565 1566 splx(s); 1567 1568 log(LOG_WARNING, 1569 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1570 cz->cz_dev.dv_xname, sc->sc_channel, 1571 overflows, overflows == 1 ? "" : "s", 1572 parity_errors, 1573 framing_errors, framing_errors == 1 ? "" : "s"); 1574 } 1575 1576 /* 1577 * tx and rx ring buffer size macros: 1578 * 1579 * The transmitter and receiver both use ring buffers. For each one, there 1580 * is a get (consumer) and a put (producer) offset. The get value is the 1581 * next byte to be read from the ring, and the put is the next one to be 1582 * put into the ring. get == put means the ring is empty. 1583 * 1584 * For each ring, the firmware controls one of (get, put) and this driver 1585 * controls the other. For transmission, this driver updates put to point 1586 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1587 * for receive, the driver controls put, and this driver controls get. 1588 */ 1589 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1590 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1591 1592 /* 1593 * cztty_transmit() 1594 * 1595 * Look at the tty for this port and start sending. 1596 */ 1597 int 1598 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1599 { 1600 struct cz_softc *cz = CZTTY_CZ(sc); 1601 u_int move, get, put, size, address; 1602 #ifdef HOSTRAMCODE 1603 int error, done = 0; 1604 #else 1605 int done = 0; 1606 #endif 1607 1608 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1609 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1610 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1611 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1612 1613 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1614 #ifdef HOSTRAMCODE 1615 if (0) { 1616 move = min(tp->t_outq.c_cc, move); 1617 error = q_to_b(&tp->t_outq, 0, move); 1618 if (error != move) { 1619 printf("%s: channel %d: error moving to " 1620 "transmit buf\n", cz->cz_dev.dv_xname, 1621 sc->sc_channel); 1622 move = error; 1623 } 1624 } else { 1625 #endif 1626 move = min(ndqb(&tp->t_outq, 0), move); 1627 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1628 address + put, tp->t_outq.c_cf, move); 1629 ndflush(&tp->t_outq, move); 1630 #ifdef HOSTRAMCODE 1631 } 1632 #endif 1633 1634 put = ((put + move) % size); 1635 done = 1; 1636 } 1637 if (done) { 1638 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1639 } 1640 return (done); 1641 } 1642 1643 int 1644 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1645 { 1646 struct cz_softc *cz = CZTTY_CZ(sc); 1647 u_int get, put, size, address; 1648 int done = 0, ch; 1649 1650 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1651 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1652 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1653 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1654 1655 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1656 #ifdef HOSTRAMCODE 1657 if (hostram) 1658 ch = ((char *)fifoaddr)[get]; 1659 } else { 1660 #endif 1661 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1662 address + get); 1663 #ifdef HOSTRAMCODE 1664 } 1665 #endif 1666 (*tp->t_linesw->l_rint)(ch, tp); 1667 get = (get + 1) % size; 1668 done = 1; 1669 } 1670 if (done) { 1671 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1672 } 1673 return (done); 1674 } 1675
Indexes created Thu Oct 02 01:09:59 GMT 2025