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czreg.h revision 1.1.104.1
      1  1.1.104.1     matt /*	$NetBSD: czreg.h,v 1.1.104.1 2008/01/09 01:53:40 matt Exp $	*/
      2        1.1  thorpej 
      3        1.1  thorpej /*-
      4        1.1  thorpej  * Copyright (c) 2000 Zembu Labs, Inc.
      5        1.1  thorpej  * All rights reserved.
      6        1.1  thorpej  *
      7        1.1  thorpej  * Author: Jason R. Thorpe <thorpej (at) zembu.com>
      8        1.1  thorpej  *
      9        1.1  thorpej  * Redistribution and use in source and binary forms, with or without
     10        1.1  thorpej  * modification, are permitted provided that the following conditions
     11        1.1  thorpej  * are met:
     12        1.1  thorpej  * 1. Redistributions of source code must retain the above copyright
     13        1.1  thorpej  *    notice, this list of conditions and the following disclaimer.
     14        1.1  thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     15        1.1  thorpej  *    notice, this list of conditions and the following disclaimer in the
     16        1.1  thorpej  *    documentation and/or other materials provided with the distribution.
     17        1.1  thorpej  * 3. All advertising materials mentioning features or use of this software
     18        1.1  thorpej  *    must display the following acknowledgement:
     19        1.1  thorpej  *	This product includes software developed by Zembu Labs, Inc.
     20        1.1  thorpej  * 4. Neither the name of Zembu Labs nor the names of its employees may
     21        1.1  thorpej  *    be used to endorse or promote products derived from this software
     22        1.1  thorpej  *    without specific prior written permission.
     23        1.1  thorpej  *
     24        1.1  thorpej  * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS
     25        1.1  thorpej  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR-
     26        1.1  thorpej  * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS-
     27        1.1  thorpej  * CLAIMED.  IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT,
     28        1.1  thorpej  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     29        1.1  thorpej  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     30        1.1  thorpej  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     31        1.1  thorpej  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     32        1.1  thorpej  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     33        1.1  thorpej  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     34        1.1  thorpej  */
     35        1.1  thorpej 
     36        1.1  thorpej /*
     37        1.1  thorpej  * Register and firmware communication definitions for the Cyclades
     38        1.1  thorpej  * Z series of multi-port serial adapters.
     39        1.1  thorpej  */
     40        1.1  thorpej 
     41        1.1  thorpej /*
     42        1.1  thorpej  * The Cyclades-Z series is an intelligent multi-port serial controller
     43        1.1  thorpej  * comprised of:
     44        1.1  thorpej  *
     45        1.1  thorpej  *	- PLX PCI9060ES PCI bus interface
     46        1.1  thorpej  *	- Xilinx XC5204 FPGA
     47        1.1  thorpej  *	- IDT R3052 MIPS CPU
     48        1.1  thorpej  *
     49        1.1  thorpej  * Communication is performed by modifying structures in board local
     50        1.1  thorpej  * RAM or in host RAM.  We define offsets into these structures so
     51        1.1  thorpej  * that either access method may be used.
     52        1.1  thorpej  *
     53        1.1  thorpej  * The Cyclades-Z comes in three basic flavors:
     54        1.1  thorpej  *
     55        1.1  thorpej  *	- Cyclades-8Zo rev 1 -- This is an older 8-port board with no
     56        1.1  thorpej  *	  FPGA.
     57        1.1  thorpej  *
     58        1.1  thorpej  *	- Cyclades-8Zo rev 2 -- This is the newer 8-port board, which
     59        1.1  thorpej  *	  uses an octopus cable.
     60        1.1  thorpej  *
     61        1.1  thorpej  *	- Cyclades-Ze -- This is the top-of-the-line of the Cyclades
     62        1.1  thorpej  *	  multiport serial controllers.  It uses a SCSI-2 cable to
     63        1.1  thorpej  *	  connect the card to a rack-mountable serial expansion box
     64        1.1  thorpej  *	  (1U high).  Each box has 16 RJ45 serial ports, and up to
     65        1.1  thorpej  *	  4 boxes can be chained together, for a total of 64 ports.
     66        1.1  thorpej  *	  Up to 2 boxes can be used without an extra power supply.
     67        1.1  thorpej  *	  Boxes 3 and 4 require their own external power supply,
     68        1.1  thorpej  *	  otherwise the firmware will refuse to start (as it cannot
     69        1.1  thorpej  *	  communicate with the UARTs in the boxes).
     70        1.1  thorpej  *
     71        1.1  thorpej  * The 8Zo flavors have not been tested, tho the programming interface
     72        1.1  thorpej  * is identical (except for the firmware load phase of the 8Zo rev 1;
     73        1.1  thorpej  * no FPGA load is done in that case), so they should work.
     74        1.1  thorpej  */
     75        1.1  thorpej 
     76        1.1  thorpej /*
     77        1.1  thorpej  * PLX Local Address Base values for the board RAM and FPGA regsiters.
     78        1.1  thorpej  *
     79        1.1  thorpej  * These values are specific to the Cyclades-Z.
     80        1.1  thorpej  */
     81        1.1  thorpej #define	LOCAL_ADDR0_RAM		(0x00000000 | LASBA_ENABLE)
     82        1.1  thorpej #define	LOCAL_ADDR0_FPGA	(0x14000000 | LASBA_ENABLE)
     83        1.1  thorpej 
     84        1.1  thorpej /*
     85        1.1  thorpej  * PLX Mailbox0 values.
     86        1.1  thorpej  *
     87        1.1  thorpej  * These values are specific to the Cyclades-Z.
     88        1.1  thorpej  */
     89        1.1  thorpej #define	MAILBOX0_8Zo_V1		0	/* Cyclades-8Zo ver. 1 */
     90        1.1  thorpej #define	MAILBOX0_8Zo_V2		1	/* Cyclades-8Zo ver. 2 */
     91        1.1  thorpej #define	MAILBOX0_Ze_V1		2	/* Cyclades-Ze ver. 1 */
     92        1.1  thorpej 
     93        1.1  thorpej /*
     94        1.1  thorpej  * Bits in the PLX INIT_CTRL register.
     95        1.1  thorpej  *
     96        1.1  thorpej  * These values are specific to the Cyclades-Z.
     97        1.1  thorpej  */
     98        1.1  thorpej #define	CONTROL_FPGA_LOADED	CONTROL_GPI
     99        1.1  thorpej 
    100        1.1  thorpej /*
    101        1.1  thorpej  * FPGA registers on the 8Zo boards.
    102        1.1  thorpej  */
    103        1.1  thorpej #define	FPGA_ID			0x00	/* FPGA ID */
    104        1.1  thorpej #define	FPGA_VERSION		0x04	/* FPGA version */
    105        1.1  thorpej #define	FPGA_CPU_START		0x08	/* CPU start */
    106        1.1  thorpej #define	FPGA_CPU_STOP		0x0c	/* CPU stop */
    107        1.1  thorpej #define	FPGA_MISC		0x10	/* Misc. register */
    108        1.1  thorpej #define	FPGA_IDT_MODE		0x14	/* IDT MIPS R3000 mode */
    109        1.1  thorpej #define	FPGA_UART_IRQ_STAT	0x18	/* UART interrupt status */
    110        1.1  thorpej #define	FPGA_CLEAR_TIMER0_IRQ	0x1c	/* clear timer 0 interrupt */
    111        1.1  thorpej #define	FPGA_CLEAR_TIMER1_IRQ	0x20	/* clear timer 1 interrupt */
    112        1.1  thorpej #define	FPGA_CLEAR_TIMER2_IRQ	0x24	/* clear timer 3 interrupt */
    113        1.1  thorpej #define	FPGA_TEST		0x28	/* test register */
    114        1.1  thorpej #define	FPGA_TEST_COUNT		0x2c	/* test count register */
    115        1.1  thorpej #define	FPGA_TIMER_SELECT	0x30	/* timer select */
    116        1.1  thorpej #define	FPGA_PR_UART_IRQ_STAT	0x34	/* prioritized UART interrupt status */
    117        1.1  thorpej #define	FPGA_RAM_WAIT_STATE	0x38	/* RAM wait state */
    118        1.1  thorpej #define	FPGA_UART_WAIT_STATE	0x3c	/* UART wait state */
    119        1.1  thorpej #define	FPGA_TIMER_WAIT_STATE	0x40	/* timer wait state */
    120        1.1  thorpej #define	FPGA_ACK_WAIT_STATE	0x44	/* ACK wait state */
    121        1.1  thorpej 
    122        1.1  thorpej /*
    123        1.1  thorpej  * FPGA registers on the Ze boards.  Note that the important registers
    124        1.1  thorpej  * (FPGA_ID, FPGA_VERSION, FPGA_CPU_START, FPGA_CPU_STOP) are all in the
    125        1.1  thorpej  * same place as on the 8Zo boards, and have the same meanings.
    126        1.1  thorpej  */
    127        1.1  thorpej #define	FPGA_ZE_ID		0x00	/* FPGA ID */
    128        1.1  thorpej #define	FPGA_ZE_VERSION		0x04	/* FPGA version */
    129        1.1  thorpej #define	FPGA_ZE_CPU_START	0x08	/* CPU start */
    130        1.1  thorpej #define	FPGA_ZE_CPU_STOP	0x0c	/* CPU stop */
    131        1.1  thorpej #define	FPGA_ZE_CTRL		0x10	/* CPU control */
    132        1.1  thorpej #define	FPGA_ZE_ZBUS_WAIT	0x14	/* Z-Bus wait state */
    133        1.1  thorpej #define	FPGA_ZE_TIMER_DIV	0x18	/* timer divisor */
    134        1.1  thorpej #define	FPGA_ZE_TIMER_IRQ_ACK	0x1c	/* timer interrupt ACK */
    135        1.1  thorpej 
    136        1.1  thorpej /*
    137        1.1  thorpej  * Values for FPGA ID.
    138        1.1  thorpej  */
    139        1.1  thorpej #define	FPGA_ID_8Zo_V1		0x95	/* Cyclades-8Zo ver. 1 */
    140        1.1  thorpej #define	FPGA_ID_8Zo_V2		0x84	/* Cyclades-8Zo ver. 2 */
    141        1.1  thorpej #define	FPGA_ID_Ze_V1		0x89	/* Cyclades-Ze ver. 1 */
    142        1.1  thorpej 
    143        1.1  thorpej /*
    144        1.1  thorpej  * Values for Cyclades-Ze timer divisor.
    145        1.1  thorpej  */
    146        1.1  thorpej #define	ZE_TIMER_DIV_1M		0x00
    147        1.1  thorpej #define	ZE_TIMER_DIV_256K	0x01
    148        1.1  thorpej #define	ZE_TIMER_DIV_128K	0x02
    149        1.1  thorpej #define	ZE_TIMER_DIV_32K	0x03
    150        1.1  thorpej 
    151        1.1  thorpej /*
    152        1.1  thorpej  * Firmware interface starts here.
    153        1.1  thorpej  *
    154        1.1  thorpej  * These values are valid for the following Cyclades-Z firmware:
    155        1.1  thorpej  *
    156        1.1  thorpej  *	@(#) Copyright (c) Cyclades Corporation, 1996, 1999
    157        1.1  thorpej  *	@(#) ZFIRM Cyclades-Z/PCI Firmware V_3.3.1 09/24/99
    158        1.1  thorpej  */
    159        1.1  thorpej 
    160        1.1  thorpej /*
    161        1.1  thorpej  * Structure of the firmware header.
    162        1.1  thorpej  */
    163        1.1  thorpej #define	ZFIRM_MAX_BLOCKS	16	/* max. # of firmware/FPGA blocks */
    164        1.1  thorpej struct zfirm_header {
    165        1.1  thorpej 	u_int8_t zfh_name[64];
    166        1.1  thorpej 	u_int8_t zfh_date[32];
    167        1.1  thorpej 	u_int8_t zfh_aux[32];
    168        1.1  thorpej 	u_int32_t zfh_nconfig;
    169        1.1  thorpej 	u_int32_t zfh_configoff;
    170        1.1  thorpej 	u_int32_t zfh_nblocks;
    171        1.1  thorpej 	u_int32_t zfh_blockoff;
    172        1.1  thorpej 	u_int32_t zfh_reserved[9];
    173  1.1.104.1     matt } __packed;
    174        1.1  thorpej 
    175        1.1  thorpej struct zfirm_config {
    176        1.1  thorpej 	u_int8_t zfc_name[64];
    177        1.1  thorpej 	u_int32_t zfc_mailbox;
    178        1.1  thorpej 	u_int32_t zfc_function;
    179        1.1  thorpej 	u_int32_t zfc_nblocks;
    180        1.1  thorpej 	u_int32_t zfc_blocklist[ZFIRM_MAX_BLOCKS];
    181  1.1.104.1     matt } __packed;
    182        1.1  thorpej 
    183        1.1  thorpej #define	ZFC_FUNCTION_NORMAL	0	/* normal operation */
    184        1.1  thorpej #define	ZFC_FUNCTION_TEST	1	/* test mode operation */
    185        1.1  thorpej 
    186        1.1  thorpej struct zfirm_block {
    187        1.1  thorpej 	u_int32_t zfb_type;
    188        1.1  thorpej 	u_int32_t zfb_fileoff;
    189        1.1  thorpej 	u_int32_t zfb_ramoff;
    190        1.1  thorpej 	u_int32_t zfb_size;
    191  1.1.104.1     matt } __packed;
    192        1.1  thorpej 
    193        1.1  thorpej #define	ZFB_TYPE_FIRMWARE	0	/* MIPS firmware */
    194        1.1  thorpej #define	ZFB_TYPE_FPGA		1	/* FPGA code */
    195        1.1  thorpej 
    196        1.1  thorpej #define	ZFIRM_MAX_CHANNELS	64	/* max. # channels per board */
    197        1.1  thorpej 
    198        1.1  thorpej /*
    199        1.1  thorpej  * Firmware ID structure, which the firmware sets up after it boots.
    200        1.1  thorpej  */
    201        1.1  thorpej #define	ZFIRM_SIG_OFF	   0x00000180	/* offset of signature in board RAM */
    202        1.1  thorpej #define	ZFIRM_CTRLADDR_OFF 0x00000184	/* offset of offset of control
    203        1.1  thorpej 					   structure */
    204        1.1  thorpej #define	ZFIRM_SIG	0x5557465A	/* ZFIRM signature */
    205        1.1  thorpej #define	ZFIRM_HLT	0x59505B5C	/* Halt due to power problem */
    206        1.1  thorpej #define	ZFIRM_RST	0x56040674	/* Firmware reset */
    207        1.1  thorpej 
    208        1.1  thorpej /*
    209        1.1  thorpej  * The firmware control structures are made up of the following:
    210        1.1  thorpej  *
    211        1.1  thorpej  *	BOARD CONTROL (64 bytes)
    212        1.1  thorpej  *	CHANNEL CONTROL (96 bytes * ZFIRM_MAX_CHANNELS)
    213        1.1  thorpej  *	BUFFER CONTROL (64 bytes * ZFIRM_MAX_CHANNELS)
    214        1.1  thorpej  */
    215        1.1  thorpej 
    216        1.1  thorpej #define	ZFIRM_BRDCTL_SIZE	64
    217        1.1  thorpej #define	ZFIRM_CHNCTL_SIZE	96
    218        1.1  thorpej #define	ZFIRM_BUFCTL_SIZE	64
    219        1.1  thorpej 
    220        1.1  thorpej #define	ZFIRM_CHNCTL_OFF(chan, reg)					\
    221        1.1  thorpej 	(ZFIRM_BRDCTL_SIZE + ((chan) * ZFIRM_CHNCTL_SIZE) + (reg))
    222        1.1  thorpej #define	ZFIRM_BUFCTL_OFF(chan, reg)					\
    223        1.1  thorpej 	(ZFIRM_CHNCTL_OFF(ZFIRM_MAX_CHANNELS, 0) + 			\
    224        1.1  thorpej 	 ((chan) * ZFIRM_BUFCTL_SIZE) + (reg))
    225        1.1  thorpej 
    226        1.1  thorpej /*
    227        1.1  thorpej  * Offsets in the BOARD CONTROL structure.
    228        1.1  thorpej  */
    229        1.1  thorpej 	/* static info provided by MIPS */
    230        1.1  thorpej #define	BRDCTL_NCHANNEL		0x00	/* number of channels */
    231        1.1  thorpej #define	BRDCTL_FWVERSION	0x04	/* firmware version */
    232        1.1  thorpej 	/* static info provided by driver */
    233        1.1  thorpej #define	BRDCTL_C_OS		0x08	/* operating system ID */
    234        1.1  thorpej #define	BRDCTL_DRVERSION	0x0c	/* driver version */
    235        1.1  thorpej 	/* board control area */
    236        1.1  thorpej #define	BRDCTL_INACTIVITY	0x10	/* inactivity control */
    237        1.1  thorpej 	/* host to firmware commands */
    238        1.1  thorpej #define	BRDCTL_HCMD_CHANNEL	0x14	/* channel number */
    239        1.1  thorpej #define	BRDCTL_HCMD_PARAM	0x18	/* parameter */
    240        1.1  thorpej 	/* firmware to host commands */
    241        1.1  thorpej #define	BRDCTL_FWCMD_CHANNEL	0x1c	/* channel number */
    242        1.1  thorpej #define	BRDCTL_FWCMD_PARAM	0x20	/* parameter */
    243        1.1  thorpej #define	BRDCTL_INT_QUEUE_OFF	0x24	/* offset to INT_QUEUE structure */
    244        1.1  thorpej 
    245        1.1  thorpej /*
    246        1.1  thorpej  * Offsets in the CHANNEL CONTROL structure.
    247        1.1  thorpej  */
    248        1.1  thorpej #define	CHNCTL_OP_MODE		0x00	/* operation mode */
    249        1.1  thorpej #define	CHNCTL_INTR_ENABLE	0x04	/* interrupt making for UART */
    250        1.1  thorpej #define	CHNCTL_SW_FLOW		0x08	/* SW flow control */
    251        1.1  thorpej #define	CHNCTL_FLOW_STATUS	0x0c	/* output flow status */
    252        1.1  thorpej #define	CHNCTL_COMM_BAUD	0x10	/* baud rate -- numerically specified */
    253        1.1  thorpej #define	CHNCTL_COMM_PARITY	0x14	/* parity */
    254        1.1  thorpej #define	CHNCTL_COMM_DATA_L	0x18	/* data length/stop */
    255        1.1  thorpej #define	CHNCTL_COMM_FLAGS	0x1c	/* other flags */
    256        1.1  thorpej #define	CHNCTL_HW_FLOW		0x20	/* HW flow control */
    257        1.1  thorpej #define	CHNCTL_RS_CONTROL	0x24	/* RS-232 outputs */
    258        1.1  thorpej #define	CHNCTL_RS_STATUS	0x28	/* RS-232 inputs */
    259        1.1  thorpej #define	CHNCTL_FLOW_XON		0x2c	/* XON character */
    260        1.1  thorpej #define	CHNCTL_FLOW_XOFF	0x30	/* XOFF character */
    261        1.1  thorpej #define	CHNCTL_HW_OVERFLOW	0x34	/* HW overflow counter */
    262        1.1  thorpej #define	CHNCTL_SW_OVERFLOW	0x38	/* SW overflow counter */
    263        1.1  thorpej #define	CHNCTL_COMM_ERROR	0x3c	/* frame/parity error counter */
    264        1.1  thorpej #define	CHNCTL_ICHAR		0x40	/* special interrupt character */
    265        1.1  thorpej 
    266        1.1  thorpej /*
    267        1.1  thorpej  * Offsets in the BUFFER CONTROL structure.
    268        1.1  thorpej  */
    269        1.1  thorpej #define	BUFCTL_FLAG_DMA		0x00	/* buffers are in Host memory */
    270        1.1  thorpej #define	BUFCTL_TX_BUFADDR	0x04	/* address of Tx buffer */
    271        1.1  thorpej #define	BUFCTL_TX_BUFSIZE	0x08	/* size of Tx buffer */
    272        1.1  thorpej #define	BUFCTL_TX_THRESHOLD	0x0c	/* Tx low water mark */
    273        1.1  thorpej #define	BUFCTL_TX_GET		0x10	/* tail index Tx buf */
    274        1.1  thorpej #define	BUFCTL_TX_PUT		0x14	/* head index Tx buf */
    275        1.1  thorpej #define	BUFCTL_RX_BUFADDR	0x18	/* address of Rx buffer */
    276        1.1  thorpej #define	BUFCTL_RX_BUFSIZE	0x1c	/* size of Rx buffer */
    277        1.1  thorpej #define	BUFCTL_RX_THRESHOLD	0x20	/* Rx high water mark */
    278        1.1  thorpej #define	BUFCTL_RX_GET		0x24	/* tail index Rx buf */
    279        1.1  thorpej #define	BUFCTL_RX_PUT		0x28	/* head index Rx buf */
    280        1.1  thorpej 
    281        1.1  thorpej /* Values for operating system ID (BOARD CONTROL) */
    282        1.1  thorpej #define	C_OS_SVR3		0x00000010	/* generic SVR3 */
    283        1.1  thorpej #define	C_OS_XENIX		0x00000011	/* SCO XENIX */
    284        1.1  thorpej #define	C_OS_SCO		0x00000012	/* SCO SVR3 */
    285        1.1  thorpej #define	C_OS_SVR4		0x00000020	/* generic SVR4 */
    286        1.1  thorpej #define	C_OS_UXWARE		0x00000021	/* UnixWare */
    287        1.1  thorpej #define	C_OS_LINUX		0x00000030	/* Linux */
    288        1.1  thorpej #define	C_OS_SOLARIS		0x00000040	/* Solaris */
    289        1.1  thorpej #define	C_OS_BSD		0x00000050	/* generic BSD */
    290        1.1  thorpej #define	C_OS_DOS		0x00000070	/* generic DOS */
    291        1.1  thorpej #define	C_OS_NT			0x00000080	/* Windows NT */
    292        1.1  thorpej #define	C_OS_OS2		0x00000090	/* IBM OS/2 */
    293        1.1  thorpej #define	C_OS_MACOS		0x000000a0	/* MacOS */
    294        1.1  thorpej #define	C_OS_AIX		0x000000b0	/* IBM AIX */
    295        1.1  thorpej 
    296        1.1  thorpej /* Values for op_mode (CHANNEL CONTROL) */
    297        1.1  thorpej #define	C_CH_DISABLE		0x00000000	/* channel is disabled */
    298        1.1  thorpej #define	C_CH_TXENABLE		0x00000001	/* channel Tx enabled */
    299        1.1  thorpej #define	C_CH_RXENABLE		0x00000002	/* channel Rx enabled */
    300        1.1  thorpej #define	C_CH_ENABLE		0x00000003	/* channel Tx/Rx enabled */
    301        1.1  thorpej #define	C_CH_LOOPBACK		0x00000004	/* Loopback mode */
    302        1.1  thorpej 
    303        1.1  thorpej /* Values for comm_parity (CHANNEL CONTROL) */
    304        1.1  thorpej #define	C_PR_NONE		0x00000000	/* None */
    305        1.1  thorpej #define	C_PR_ODD		0x00000001	/* Odd */
    306        1.1  thorpej #define	C_PR_EVEN		0x00000002	/* Even */
    307        1.1  thorpej #define	C_PR_MARK		0x00000004	/* Mark */
    308        1.1  thorpej #define	C_PR_SPACE		0x00000008	/* Space */
    309        1.1  thorpej #define	C_PR_PARITY		0x000000ff
    310        1.1  thorpej #define	C_PR_DISCARD		0x00000100	/* discard char with
    311        1.1  thorpej 						   frame/parity error */
    312        1.1  thorpej #define	C_PR_IGNORE		0x00000200	/* ignore frame/par error */
    313        1.1  thorpej 
    314        1.1  thorpej /* Values for comm_data_l (CHANNEL CONTROL) */
    315        1.1  thorpej #define	C_DL_CS5		0x00000001
    316        1.1  thorpej #define	C_DL_CS6		0x00000002
    317        1.1  thorpej #define	C_DL_CS7		0x00000004
    318        1.1  thorpej #define	C_DL_CS8		0x00000008
    319        1.1  thorpej #define	C_DL_CS			0x0000000f
    320        1.1  thorpej #define	C_DL_1STOP		0x00000010
    321        1.1  thorpej #define	C_DL_15STOP		0x00000020
    322        1.1  thorpej #define	C_DL_2STOP		0x00000040
    323        1.1  thorpej #define	C_DL_STOP		0x000000f0
    324        1.1  thorpej 
    325        1.1  thorpej /* Values for intr_enable (CHANNEL CONTROL) */
    326        1.1  thorpej #define	C_IN_DISABLE		0x00000000	/* zero, disable interrupts */
    327        1.1  thorpej #define	C_IN_TXBEMPTY		0x00000001	/* tx buffer empty */
    328        1.1  thorpej #define	C_IN_TXLOWWM		0x00000002	/* tx buffer below LWM */
    329        1.1  thorpej #define	C_IN_TXFEMPTY		0x00000004	/* tx buffer + FIFO +
    330        1.1  thorpej 						   shift reg. empty */
    331        1.1  thorpej #define	C_IN_RXHIWM		0x00000010	/* rx buffer above HWM */
    332        1.1  thorpej #define	C_IN_RXNNDT		0x00000020	/* rx no new data timeout */
    333        1.1  thorpej #define	C_IN_MDCD		0x00000100	/* modem DCD change */
    334        1.1  thorpej #define	C_IN_MDSR		0x00000200	/* modem DSR change */
    335        1.1  thorpej #define	C_IN_MRI		0x00000400	/* modem RI change */
    336        1.1  thorpej #define	C_IN_MCTS		0x00000800	/* modem CTS change */
    337        1.1  thorpej #define	C_IN_RXBRK		0x00001000	/* Break received */
    338        1.1  thorpej #define	C_IN_PR_ERROR		0x00002000	/* parity error */
    339        1.1  thorpej #define	C_IN_FR_ERROR		0x00004000	/* frame error */
    340        1.1  thorpej #define	C_IN_OVR_ERROR		0x00008000	/* overrun error */
    341        1.1  thorpej #define	C_IN_RXOFL		0x00010000	/* RX buffer overflow */
    342        1.1  thorpej #define	C_IN_IOCTLW		0x00020000	/* I/O control w/ wait */
    343        1.1  thorpej #define	C_IN_MRTS		0x00040000	/* modem RTS drop */
    344        1.1  thorpej #define	C_IN_ICHAR		0x00080000	/* special intr. char
    345        1.1  thorpej 						   received */
    346        1.1  thorpej 
    347        1.1  thorpej /* Values for flow control (CHANNEL CONTROL) */
    348        1.1  thorpej #define	C_FL_OXX		0x00000001	/* output Xon/Xoff flow
    349        1.1  thorpej 						   control */
    350        1.1  thorpej #define	C_FL_IXX		0x00000002	/* input Xon/Xoff flow
    351        1.1  thorpej 						   control */
    352        1.1  thorpej #define	C_FL_OIXANY		0x00000004	/* output Xon/Xoff (any xon) */
    353        1.1  thorpej #define	C_FL_SWFLOW		0x0000000f
    354        1.1  thorpej 
    355        1.1  thorpej /* Values for flow status (CHANNEL CONTROL) */
    356        1.1  thorpej #define	C_FS_TXIDLE		0x00000000	/* no Tx data in the buffer
    357        1.1  thorpej 						   or UART */
    358        1.1  thorpej #define	C_FS_SENDING		0x00000001      /* UART is sending data */
    359        1.1  thorpej #define C_FS_SWFLOW		0x00000002      /* Tx is stopped by received
    360        1.1  thorpej 						   Xoff */
    361        1.1  thorpej 
    362        1.1  thorpej /* Values for RS-232 signals (CHANNEL CONTROL) */
    363        1.1  thorpej #define	C_RS_PARAM		0x80000000	/* indicates presence of
    364        1.1  thorpej 						   parameter in IOCTL command */
    365        1.1  thorpej #define	C_RS_RTS		0x00000001	/* RTS */
    366        1.1  thorpej #define	C_RS_DTR		0x00000004	/* DTR */
    367        1.1  thorpej #define	C_RS_DCD		0x00000100	/* CD */
    368        1.1  thorpej #define	C_RS_DSR		0x00000200	/* DSR */
    369        1.1  thorpej #define	C_RS_RI			0x00000400	/* RI */
    370        1.1  thorpej #define	C_RS_CTS		0x00000800	/* CTS */
    371        1.1  thorpej 
    372        1.1  thorpej /* Commands Host <--> Board */
    373        1.1  thorpej #define	C_CM_RESET		0x01	/* resets/flushes buffers */
    374        1.1  thorpej #define	C_CM_IOCTL		0x02	/* re-reads CH_CTRL */
    375        1.1  thorpej #define	C_CM_IOCTLW		0x03	/* re-reads CH_CTRL, intr when done */
    376        1.1  thorpej #define	C_CM_IOCTLM		0x04	/* RS-232 outputs change */
    377        1.1  thorpej #define	C_CM_SENDXOFF		0x10	/* sends Xoff */
    378        1.1  thorpej #define	C_CM_SENDXON		0x11	/* sends Xon */
    379        1.1  thorpej #define	C_CM_CLFLOW		0x12	/* Clears flow control (resume) */
    380        1.1  thorpej #define	C_CM_SENDBRK		0x41	/* sends break */
    381        1.1  thorpej #define	C_CM_INTBACK		0x42	/* Interrupt back */
    382        1.1  thorpej #define	C_CM_SET_BREAK		0x43	/* Tx break on */
    383        1.1  thorpej #define	C_CM_CLR_BREAK		0x44	/* Tx break off */
    384        1.1  thorpej #define	C_CM_CMD_DONE		0x45	/* Previous command done */
    385        1.1  thorpej #define	C_CM_INTBACK2		0x46	/* Alternate Interrupt back */
    386        1.1  thorpej #define	C_CM_TINACT		0x51	/* sets inactivity detection */
    387        1.1  thorpej #define	C_CM_IRQ_ENBL		0x52	/* enables generation of interrupts */
    388        1.1  thorpej #define	C_CM_IRQ_DSBL		0x53	/* disables generation of interrupts */
    389        1.1  thorpej #define	C_CM_ACK_ENBL		0x54	/* enables acknolowdged interrupt
    390        1.1  thorpej 					   mode */
    391        1.1  thorpej #define	C_CM_ACK_DSBL		0x55	/* disables acknolowdged intr mode */
    392        1.1  thorpej #define	C_CM_FLUSH_RX		0x56	/* flushes Rx buffer */
    393        1.1  thorpej #define	C_CM_FLUSH_TX		0x57	/* flushes Tx buffer */
    394        1.1  thorpej #define	C_CM_Q_ENABLE		0x58	/* enables queue access from the
    395        1.1  thorpej 					   driver */
    396        1.1  thorpej #define	C_CM_Q_DISABLE		0x59	/* disables queue access from the
    397        1.1  thorpej 					   driver */
    398        1.1  thorpej #define	C_CM_TXBEMPTY		0x60	/* Tx buffer is empty */
    399        1.1  thorpej #define	C_CM_TXLOWWM		0x61	/* Tx buffer low water mark */
    400        1.1  thorpej #define	C_CM_RXHIWM		0x62	/* Rx buffer high water mark */
    401        1.1  thorpej #define	C_CM_RXNNDT		0x63	/* rx no new data timeout */
    402        1.1  thorpej #define	C_CM_TXFEMPTY		0x64	/* Tx buffer, FIFO and shift reg.
    403        1.1  thorpej 					   are empty */
    404        1.1  thorpej #define	C_CM_ICHAR		0x65	/* Special Interrupt Character
    405        1.1  thorpej 					   received */
    406        1.1  thorpej #define	C_CM_MDCD		0x70	/* modem DCD change */
    407        1.1  thorpej #define	C_CM_MDSR		0x71	/* modem DSR change */
    408        1.1  thorpej #define	C_CM_MRI		0x72	/* modem RI change */
    409        1.1  thorpej #define	C_CM_MCTS		0x73	/* modem CTS change */
    410        1.1  thorpej #define	C_CM_MRTS		0x74	/* modem RTS drop */
    411        1.1  thorpej #define	C_CM_RXBRK		0x84	/* Break received */
    412        1.1  thorpej #define	C_CM_PR_ERROR		0x85	/* Parity error */
    413        1.1  thorpej #define	C_CM_FR_ERROR		0x86	/* Frame error */
    414        1.1  thorpej #define	C_CM_OVR_ERROR		0x87	/* Overrun error */
    415        1.1  thorpej #define	C_CM_RXOFL		0x88	/* RX buffer overflow */
    416        1.1  thorpej #define	C_CM_CMDERROR		0x90	/* command error */
    417        1.1  thorpej #define	C_CM_FATAL		0x91	/* fatal error */
    418        1.1  thorpej #define	C_CM_HW_RESET		0x92	/* reset board */
    419