dpt_pci.c revision 1.3.2.3
1 1.3.2.3 he /* $NetBSD: dpt_pci.c,v 1.3.2.3 2000/01/18 20:05:21 he Exp $ */ 2 1.3.2.2 he 3 1.3.2.2 he /* 4 1.3.2.2 he * Copyright (c) 1999 Andy Doran <ad (at) NetBSD.org> 5 1.3.2.2 he * All rights reserved. 6 1.3.2.2 he * 7 1.3.2.2 he * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 he * modification, are permitted provided that the following conditions 9 1.3.2.2 he * are met: 10 1.3.2.2 he * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 he * notice, this list of conditions and the following disclaimer. 12 1.3.2.2 he * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 he * notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 he * documentation and/or other materials provided with the distribution. 15 1.3.2.2 he * 16 1.3.2.2 he * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 1.3.2.2 he * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.3.2.2 he * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.3.2.2 he * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 1.3.2.2 he * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.3.2.2 he * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.3.2.2 he * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.3.2.2 he * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.3.2.2 he * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.3.2.2 he * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.3.2.2 he * SUCH DAMAGE. 27 1.3.2.2 he * 28 1.3.2.2 he */ 29 1.3.2.2 he 30 1.3.2.2 he /* 31 1.3.2.2 he * PCI front-end for DPT EATA SCSI driver. 32 1.3.2.2 he */ 33 1.3.2.2 he 34 1.3.2.2 he #include <sys/cdefs.h> 35 1.3.2.3 he __KERNEL_RCSID(0, "$NetBSD: dpt_pci.c,v 1.3.2.3 2000/01/18 20:05:21 he Exp $"); 36 1.3.2.2 he 37 1.3.2.2 he #include <sys/param.h> 38 1.3.2.2 he #include <sys/systm.h> 39 1.3.2.2 he #include <sys/kernel.h> 40 1.3.2.2 he #include <sys/device.h> 41 1.3.2.2 he #include <sys/queue.h> 42 1.3.2.2 he #include <sys/proc.h> 43 1.3.2.2 he 44 1.3.2.2 he #include <machine/endian.h> 45 1.3.2.2 he #include <machine/bus.h> 46 1.3.2.2 he 47 1.3.2.2 he #include <dev/scsipi/scsi_all.h> 48 1.3.2.2 he #include <dev/scsipi/scsipi_all.h> 49 1.3.2.2 he #include <dev/scsipi/scsiconf.h> 50 1.3.2.2 he 51 1.3.2.2 he #include <dev/pci/pcidevs.h> 52 1.3.2.2 he #include <dev/pci/pcivar.h> 53 1.3.2.2 he 54 1.3.2.2 he #include <dev/ic/dptreg.h> 55 1.3.2.2 he #include <dev/ic/dptvar.h> 56 1.3.2.2 he 57 1.3.2.2 he #define PCI_CBMA 0x14 /* Configuration base memory address */ 58 1.3.2.2 he #define PCI_CBIO 0x10 /* Configuration base I/O address */ 59 1.3.2.2 he 60 1.3.2.2 he int dpt_pci_match __P((struct device *, struct cfdata *, void *)); 61 1.3.2.2 he void dpt_pci_attach __P((struct device *, struct device *, void *)); 62 1.3.2.2 he 63 1.3.2.2 he struct cfattach dpt_pci_ca = { 64 1.3.2.2 he sizeof(struct dpt_softc), dpt_pci_match, dpt_pci_attach 65 1.3.2.2 he }; 66 1.3.2.2 he 67 1.3.2.2 he int 68 1.3.2.2 he dpt_pci_match(parent, match, aux) 69 1.3.2.2 he struct device *parent; 70 1.3.2.2 he struct cfdata *match; 71 1.3.2.2 he void *aux; 72 1.3.2.2 he { 73 1.3.2.2 he struct pci_attach_args *pa = (struct pci_attach_args *) aux; 74 1.3.2.2 he 75 1.3.2.2 he if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_DPT && 76 1.3.2.2 he PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DPT_SC_RAID) 77 1.3.2.2 he return (1); 78 1.3.2.2 he 79 1.3.2.2 he return (0); 80 1.3.2.2 he } 81 1.3.2.2 he 82 1.3.2.2 he void 83 1.3.2.2 he dpt_pci_attach(parent, self, aux) 84 1.3.2.2 he struct device *parent; 85 1.3.2.2 he struct device *self; 86 1.3.2.2 he void *aux; 87 1.3.2.2 he { 88 1.3.2.2 he struct pci_attach_args *pa; 89 1.3.2.2 he struct dpt_softc *sc; 90 1.3.2.2 he pci_chipset_tag_t pc; 91 1.3.2.2 he pci_intr_handle_t ih; 92 1.3.2.3 he bus_space_handle_t ioh; 93 1.3.2.2 he const char *intrstr; 94 1.3.2.2 he pcireg_t csr; 95 1.3.2.2 he 96 1.3.2.2 he sc = (struct dpt_softc *)self; 97 1.3.2.2 he pa = (struct pci_attach_args *)aux; 98 1.3.2.2 he pc = pa->pa_pc; 99 1.3.2.2 he printf(": "); 100 1.3.2.2 he 101 1.3.2.2 he if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, &sc->sc_iot, 102 1.3.2.3 he &ioh, NULL, NULL)) { 103 1.3.2.2 he printf("can't map i/o space\n"); 104 1.3.2.2 he return; 105 1.3.2.2 he } 106 1.3.2.3 he 107 1.3.2.3 he /* Need to map in by 16 registers */ 108 1.3.2.3 he if (bus_space_subregion(sc->sc_iot, ioh, 16, 16, &sc->sc_ioh)) { 109 1.3.2.3 he printf("can't map i/o subregion\n"); 110 1.3.2.3 he return; 111 1.3.2.3 he } 112 1.3.2.2 he 113 1.3.2.2 he sc->sc_dmat = pa->pa_dmat; 114 1.3.2.2 he 115 1.3.2.2 he /* Enable the device. */ 116 1.3.2.2 he csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 117 1.3.2.2 he pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 118 1.3.2.2 he csr | PCI_COMMAND_MASTER_ENABLE); 119 1.3.2.2 he 120 1.3.2.2 he /* Map and establish the interrupt. */ 121 1.3.2.2 he if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 122 1.3.2.2 he pa->pa_intrline, &ih)) { 123 1.3.2.2 he printf("can't map interrupt\n"); 124 1.3.2.2 he return; 125 1.3.2.2 he } 126 1.3.2.2 he intrstr = pci_intr_string(pc, ih); 127 1.3.2.2 he sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, dpt_intr, sc); 128 1.3.2.2 he if (sc->sc_ih == NULL) { 129 1.3.2.2 he printf("can't establish interrupt"); 130 1.3.2.2 he if (intrstr != NULL) 131 1.3.2.2 he printf(" at %s", intrstr); 132 1.3.2.2 he printf("\n"); 133 1.3.2.2 he return; 134 1.3.2.2 he } 135 1.3.2.2 he 136 1.3.2.2 he /* Read the EATA configuration */ 137 1.3.2.2 he if (dpt_readcfg(sc)) { 138 1.3.2.2 he printf("%s: readcfg failed - see dpt(4)\n", 139 1.3.2.2 he sc->sc_dv.dv_xname); 140 1.3.2.2 he return; 141 1.3.2.2 he } 142 1.3.2.2 he 143 1.3.2.2 he /* Now attach to the bus-independent code */ 144 1.3.2.2 he dpt_init(sc, intrstr); 145 1.3.2.2 he } 146
Indexes created Fri Oct 03 02:09:57 GMT 2025