eapreg.h revision 1.10
1 /* $NetBSD: eapreg.h,v 1.10 2005/02/13 23:58:38 fredb Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson <augustss (at) NetBSD.org> and Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * ES1370/ES1371/ES1373 registers 41 */ 42 43 #define EAP_ICSC 0x00 /* interrupt / chip select control */ 44 #define EAP_SERR_DISABLE 0x00000001 45 #define EAP_CDC_EN 0x00000002 46 #define EAP_JYSTK_EN 0x00000004 47 #define EAP_UART_EN 0x00000008 48 #define EAP_ADC_EN 0x00000010 49 #define EAP_DAC2_EN 0x00000020 50 #define EAP_DAC1_EN 0x00000040 51 #define EAP_BREQ 0x00000080 52 #define EAP_XTCL0 0x00000100 53 #define EAP_M_CB 0x00000200 54 #define EAP_CCB_INTRM 0x00000400 55 #define EAP_DAC_SYNC 0x00000800 56 #define EAP_WTSRSEL 0x00003000 57 #define EAP_WTSRSEL_5 0x00000000 58 #define EAP_WTSRSEL_11 0x00001000 59 #define EAP_WTSRSEL_22 0x00002000 60 #define EAP_WTSRSEL_44 0x00003000 61 #define EAP_M_SBB 0x00004000 62 #define E1371_SYNC_RES 0x00004000 63 #define EAP_MSFMTSEL 0x00008000 64 #define EAP_DAC_EN(i) (EAP_DAC2_EN << (i)) 65 #define EAP_SET_PCLKDIV(n) (((n)&0x1fff)<<16) 66 #define EAP_GET_PCLKDIV(n) (((n)>>16)&0x1fff) 67 #define EAP_PCLKBITS 0x1fff0000 68 #define E1371_JOY_ASEL(n) (((n)&3)<<24) 69 #define E1371_JOY_ASELBITS 0x03000000 70 #define EAP_XTCL1 0x40000000 71 #define EAP_ADC_STOP 0x80000000 72 73 #define EAP_ICSS 0x04 /* interrupt / chip select status */ 74 /* on the 5880 control / status */ 75 #define EAP_I_ADC 0x00000001 76 #define EAP_I_DAC2 0x00000002 77 #define EAP_I_DAC1 0x00000004 78 #define EAP_I_UART 0x00000008 79 #define EAP_I_MCCB 0x00000010 80 #define EAP_VC 0x00000060 81 #define EAP_CWRIP 0x00000100 82 #define EAP_CBUSY 0x00000200 83 #define EAP_CSTAT 0x00000400 84 #define EAP_CT5880_AC97_RESET 0x20000000 85 #define EAP_INTR 0x80000000 86 87 #define EAP_UART_DATA 0x08 88 #define EAP_UART_STATUS 0x09 89 #define EAP_US_RXRDY 0x01 90 #define EAP_US_TXRDY 0x02 91 #define EAP_US_TXINT 0x04 92 #define EAP_US_RXINT 0x80 93 #define EAP_UART_CONTROL 0x09 94 #define EAP_UC_CNTRL 0x03 95 #define EAP_UC_TXINTEN 0x20 96 #define EAP_UC_RXINTEN 0x80 97 #define EAP_MEMPAGE 0x0c 98 #define EAP_CODEC 0x10 99 #define EAP_SET_CODEC(a,d) (((a)<<8) | (d)) 100 101 /* 102 * ES1371/ES1373 registers 103 */ 104 105 #define E1371_CODEC 0x14 106 #define E1371_CODEC_VALID 0x80000000 107 #define E1371_CODEC_WIP 0x40000000 108 #define E1371_CODEC_READ 0x00800000 109 #define E1371_SET_CODEC(a,d) (((a)<<16) | (d)) 110 111 #define E1371_SRC 0x10 112 #define E1371_SRC_RAMWE 0x01000000 113 #define E1371_SRC_RBUSY 0x00800000 114 #define E1371_SRC_DISABLE 0x00400000 115 #define E1371_SRC_DISP1 0x00200000 116 #define E1371_SRC_DISP2 0x00100000 117 #define E1371_SRC_DISREC 0x00080000 118 #define E1371_SRC_DATAMASK 0x0000ffff 119 #define E1371_SRC_ADDR(a) ((a)<<25) 120 #define E1371_SRC_DATA(d) ((d) & E1371_SRC_DATAMASK) 121 #define E1371_SRC_CTLMASK (E1371_SRC_DISABLE | E1371_SRC_DISP1 | \ 122 E1371_SRC_DISP2 | E1371_SRC_DISREC) 123 #define E1371_SRC_STATE_MASK 0x00870000 124 #define E1371_SRC_STATE_OK 0x00010000 125 126 #define E1371_LEGACY 0x18 127 128 /* 129 * ES1371/ES1373 sample rate converter registers 130 */ 131 132 #define ESRC_ADC 0x78 133 #define ESRC_DAC1 0x70 134 #define ESRC_DAC2 0x74 135 #define ESRC_ADC_VOLL 0x6c 136 #define ESRC_ADC_VOLR 0x6d 137 #define ESRC_DAC1_VOLL 0x7c 138 #define ESRC_DAC1_VOLR 0x7d 139 #define ESRC_DAC2_VOLL 0x7e 140 #define ESRC_DAC2_VOLR 0x7f 141 #define ESRC_TRUNC_N 0x00 142 #define ESRC_IREGS 0x01 143 #define ESRC_ACF 0x02 144 #define ESRC_VFF 0x03 145 #define ESRC_SET_TRUNC(n) ((n)<<9) 146 #define ESRC_SET_N(n) ((n)<<4) 147 #define ESRC_SMF 0x8000 148 #define ESRC_SET_VFI(n) ((n)<<10) 149 #define ESRC_SET_ACI(n) (n) 150 #define ESRC_SET_ADC_VOL(n) ((n)<<8) 151 #define ESRC_SET_DAC_VOLI(n) ((n)<<12) 152 #define ESRC_SET_DAC_VOLF(n) (n) 153 #define SRC_MAGIC ((1<15)|(1<<13)|(1<<11)|(1<<9)) 154 155 #define EAP_SIC 0x20 156 #define EAP_P1_S_MB 0x00000001 157 #define EAP_P1_S_EB 0x00000002 158 #define EAP_P2_S_MB 0x00000004 159 #define EAP_P2_S_EB 0x00000008 160 #define EAP_R1_S_MB 0x00000010 161 #define EAP_R1_S_EB 0x00000020 162 #define EAP_P2_DAC_SEN 0x00000040 163 #define EAP_P1_SCT_RLD 0x00000080 164 #define EAP_P1_INTR_EN 0x00000100 165 #define EAP_P2_INTR_EN 0x00000200 166 #define EAP_R1_INTR_EN 0x00000400 167 #define EAP_P1_PAUSE 0x00000800 168 #define EAP_P2_PAUSE 0x00001000 169 #define EAP_P1_LOOP_SEL 0x00002000 170 #define EAP_P2_LOOP_SEL 0x00004000 171 #define EAP_R1_LOOP_SEL 0x00008000 172 #define EAP_S_EB(i) (EAP_P2_S_EB >> 2*(i)) 173 #define EAP_S_MB(i) (EAP_P2_S_MB >> 2*(i)) 174 #define EAP_P_INTR_EN(i) (EAP_P2_INTR_EN >> (i)) 175 #define EAP_SET_P2_ST_INC(i) ((i) << 16) 176 #define EAP_SET_P2_END_INC(i) ((i) << 19) 177 #define EAP_INC_BITS 0x003f0000 178 179 #define EAP_DAC1_CSR 0x24 180 #define EAP_DAC2_CSR 0x28 181 #define EAP_ADC_CSR 0x2c 182 #define EAP_GET_CURRSAMP(r) ((r) >> 16) 183 184 #define EAP_DAC_PAGE 0xc 185 #define EAP_ADC_PAGE 0xd 186 #define EAP_UART_PAGE1 0xe 187 #define EAP_UART_PAGE2 0xf 188 189 #define EAP_DAC1_ADDR 0x30 190 #define EAP_DAC1_SIZE 0x34 191 #define EAP_DAC2_ADDR 0x38 192 #define EAP_DAC2_SIZE 0x3c 193 #define EAP_ADC_ADDR 0x30 194 #define EAP_ADC_SIZE 0x34 195 #define EAP_SET_SIZE(c,s) (((c)<<16) | (s)) 196 197 #define EAP_READ_TIMEOUT 5000 198 #define EAP_WRITE_TIMEOUT 5000 199 200 201 #define EAP_XTAL_FREQ 1411200 /* 22.5792 / 16 MHz */ 202 203 /* AK4531 registers */ 204 #define AK_MASTER_L 0x00 205 #define AK_MASTER_R 0x01 206 #define AK_VOICE_L 0x02 207 #define AK_VOICE_R 0x03 208 #define AK_FM_L 0x04 209 #define AK_FM_R 0x05 210 #define AK_CD_L 0x06 211 #define AK_CD_R 0x07 212 #define AK_LINE_L 0x08 213 #define AK_LINE_R 0x09 214 #define AK_AUX_L 0x0a 215 #define AK_AUX_R 0x0b 216 #define AK_MONO1 0x0c 217 #define AK_MONO2 0x0d 218 #define AK_MIC 0x0e 219 #define AK_MONO 0x0f 220 #define AK_OUT_MIXER1 0x10 221 #define AK_M_FM_L 0x40 222 #define AK_M_FM_R 0x20 223 #define AK_M_LINE_L 0x10 224 #define AK_M_LINE_R 0x08 225 #define AK_M_CD_L 0x04 226 #define AK_M_CD_R 0x02 227 #define AK_M_MIC 0x01 228 #define AK_OUT_MIXER2 0x11 229 #define AK_M_AUX_L 0x20 230 #define AK_M_AUX_R 0x10 231 #define AK_M_VOICE_L 0x08 232 #define AK_M_VOICE_R 0x04 233 #define AK_M_MONO2 0x02 234 #define AK_M_MONO1 0x01 235 #define AK_IN_MIXER1_L 0x12 236 #define AK_IN_MIXER1_R 0x13 237 #define AK_IN_MIXER2_L 0x14 238 #define AK_IN_MIXER2_R 0x15 239 #define AK_M_TMIC 0x80 240 #define AK_M_TMONO1 0x40 241 #define AK_M_TMONO2 0x20 242 #define AK_M2_AUX_L 0x10 243 #define AK_M2_AUX_R 0x08 244 #define AK_M_VOICE 0x04 245 #define AK_M2_MONO2 0x02 246 #define AK_M2_MONO1 0x01 247 #define AK_RESET 0x16 248 #define AK_PD 0x02 249 #define AK_NRST 0x01 250 #define AK_CS 0x17 251 #define AK_ADSEL 0x18 252 #define AK_MGAIN 0x19 253 #define AK_NPORTS 0x20 254 255 /* Not sensical for AC97? */ 256 #define VOL_TO_ATT5(v) (0x1f - ((v) >> 3)) 257 #define VOL_TO_GAIN5(v) VOL_TO_ATT5(v) 258 #define ATT5_TO_VOL(v) ((0x1f - (v)) << 3) 259 #define GAIN5_TO_VOL(v) ATT5_TO_VOL(v) 260 #define VOL_0DB 200 261 262 /* Futzable parms */ 263 #define EAP_MASTER_VOL 0 264 #define EAP_VOICE_VOL 1 265 #define EAP_FM_VOL 2 266 #define EAP_VIDEO_VOL 2 /* ES1371 */ 267 #define EAP_CD_VOL 3 268 #define EAP_LINE_VOL 4 269 #define EAP_AUX_VOL 5 270 #define EAP_MIC_VOL 6 271 #define EAP_RECORD_SOURCE 7 272 #define EAP_INPUT_SOURCE 8 273 #define EAP_MIC_PREAMP 9 274 #define EAP_OUTPUT_CLASS 10 275 #define EAP_RECORD_CLASS 11 276 #define EAP_INPUT_CLASS 12 277 278 #define MIDI_BUSY_WAIT 100 279 #define MIDI_BUSY_DELAY 100 /* Delay when UART is busy */ 280 281 #define EAP_EV1938_A 0x00 282 #define EAP_CT5880_C 0x02 283 #define EAP_CT5880_D 0x03 284 #define EAP_CT5880_E 0x04 285 #define EAP_ES1373_A 0x04 286 #define EAP_ES1373_B 0x06 287 #define EAP_CT5880_A 0x07 288 #define EAP_ES1373_8 0x08 289 #define EAP_ES1371_B 0x09 290
Indexes created Fri Sep 26 08:10:20 GMT 2025