eapreg.h revision 1.12
1 /* $NetBSD: eapreg.h,v 1.12 2006/06/30 13:56:25 chap Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson <augustss (at) NetBSD.org> and Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * ES1370/ES1371/ES1373 registers 41 */ 42 43 #define EAP_ICSC 0x00 /* interrupt / chip select control */ 44 45 #define EAP_SERR_DISABLE 0x00000001 /* do not present SERR on PCI bus */ 46 #define E1371_PCICLKDIS 0x00000001 /* PCIclk to essential modules only*/ 47 48 #define EAP_CDC_EN 0x00000002 /* enable codec i/f */ 49 #define E1371_XTALCKDIS 0x00000002 /* gate xtal clk to all modules */ 50 51 #define EAP_JYSTK_EN 0x00000004 52 #define EAP_UART_EN 0x00000008 53 #define EAP_ADC_EN 0x00000010 54 #define EAP_DAC2_EN 0x00000020 /* intended as CODEC DAC */ 55 #define EAP_DAC1_EN 0x00000040 /* intended as CODEC FM DAC */ 56 #define EAP_BREQ 0x00000080 57 58 #define EAP_XCTL0 0x00000100 /* a gp out pin on 1370 */ 59 #define EAP_M_CB 0x00000200 /* rec src mpeg (!adc) */ 60 #define E1371_PDLEV(n) ((n)<<8) /* pwr dwn lvl D0 - D3 */ 61 #define E1371_PDLEVBITS 0x00000300 62 63 #define EAP_CCB_INTRM 0x00000400 /* enable CCB module voice intrs */ 64 65 #define EAP_DAC_SYNC 0x00000800 66 #define E1371_M_CB 0x00000800 /* rec src i2s (!adc); cf EAP_M_CB!*/ 67 68 #define EAP_WTSRSEL 0x00003000 69 #define EAP_WTSRSEL_5 0x00000000 70 #define EAP_WTSRSEL_11 0x00001000 71 #define EAP_WTSRSEL_22 0x00002000 72 #define EAP_WTSRSEL_44 0x00003000 73 #define E1371_PWR_INTRM 0x00001000 /* ena intr on pwr lvl change */ 74 #define E1371_ADC_STOP 0x00002000 /* cf EAP_ADC_STOP! */ 75 76 #define EAP_M_SBB 0x00004000 77 #define E1371_SYNC_RES 0x00004000 78 79 #define EAP_MSFMTSEL 0x00008000 80 81 #define EAP_DAC_EN(i) (EAP_DAC2_EN << (i)) /* yes, it's twisted */ 82 83 #define EAP_SET_PCLKDIV(n) (((n)&0x1fff)<<16) 84 #define EAP_GET_PCLKDIV(n) (((n)>>16)&0x1fff) 85 #define EAP_PCLKBITS 0x1fff0000 86 #define E1371_OUT_GPIO(n) (((n)&0xf)<<16) 87 #define E1371_IN_GPIO(n) (((n)>>20)&0xf) 88 #define E1371_OUTGPIOBITS 0x000f0000 89 #define E1371_INGPIOBITS 0x00f00000 90 #define E1371_JOY_ASEL(n) (((n)&3)<<24) 91 #define E1371_JOY_ASELBITS 0x03000000 92 #define E1373_SPDIFEN_B 0x04000000 /* spdif generated (!spdif thru) */ 93 #define E1373_RECEN_B 0x08000000 /* !(rec monitor to spdif out) */ 94 #define E1373_TEST_BIT 0x10000000 /* 0 except to test block preamble */ 95 #define E1373_BYPASS_R 0x20000000 /* rec bypass rate converter */ 96 #define EAP_XCTL1 0x40000000 /* a gp out pin on 1370 */ 97 #define E1373_BYPASS_P2 0x40000000 /* play2 bypass rate converter */ 98 #define EAP_ADC_STOP 0x80000000 99 #define E1373_BYPASS_P1 0x80000000 /* play1 bypass rate converter */ 100 101 #define EAP_ICSS 0x04 /* interrupt / chip select status */ 102 /* on the 5880 control / status */ 103 #define EAP_I_ADC 0x00000001 104 #define EAP_I_DAC2 0x00000002 105 #define EAP_I_DAC1 0x00000004 106 #define EAP_I_UART 0x00000008 107 #define EAP_I_MCCB 0x00000010 108 #define EAP_VC 0x00000060 109 110 #define EAP_CWRIP 0x00000100 111 #define E1371_SYNC_ERR 0x00000100 112 113 #define EAP_CBUSY 0x00000200 /* tied 1 on 1371, 1373 */ 114 #define EAP_CSTAT 0x00000400 /* tied 1 on 1371, 1373 */ 115 #define E1373_GPIO_INT(n) (((n)>>12)&0xf) /* which gpios interrupted */ 116 #define E1373_TEST_MODE 0x00010000 117 #define E1373_TEST_SPDIF 0x00020000 118 #define E1373_ENABLE_SPDIF 0x00040000 119 #define E1373_GPIO_INTEN(n) (((n)&0xf)<<20) 120 #define EAP_CT5880_AC97_RESET 0x20000000 121 #define EAP_INTR 0x80000000 122 123 #define EAP_UART_DATA 0x08 124 #define EAP_UART_STATUS 0x09 125 #define EAP_US_RXRDY 0x01 126 #define EAP_US_TXRDY 0x02 127 #define EAP_US_TXINT 0x04 128 #define EAP_US_RXINT 0x80 129 #define EAP_UART_CONTROL 0x09 130 #define EAP_UC_CNTRL 0x03 131 #define EAP_UC_TXINTEN 0x20 132 #define EAP_UC_TXINTENBITS 0x60 133 #define EAP_UC_RXINTEN 0x80 134 #define EAP_UART_RESERVED 0x0a 135 #define EAP_UR_TEST_MODE 0x01 136 #define EAP_MEMPAGE 0x0c 137 #define EAP_CODEC 0x10 138 #define EAP_SET_CODEC(a,d) (((a)<<8) | (d)) 139 140 /* 141 * ES1371/ES1373 registers 142 */ 143 144 #define E1371_CODEC 0x14 145 #define E1371_CODEC_VALID 0x80000000 146 #define E1371_CODEC_WIP 0x40000000 147 #define E1371_CODEC_READ 0x00800000 148 #define E1371_SET_CODEC(a,d) (((a)<<16) | (d)) 149 150 #define E1371_SRC 0x10 151 #define E1371_SRC_RAMWE 0x01000000 152 #define E1371_SRC_RBUSY 0x00800000 153 #define E1371_SRC_DISABLE 0x00400000 154 #define E1371_SRC_DISP1 0x00200000 155 #define E1371_SRC_DISP2 0x00100000 156 #define E1371_SRC_DISREC 0x00080000 157 #define E1371_SRC_DATAMASK 0x0000ffff 158 #define E1371_SRC_ADDR(a) ((a)<<25) 159 #define E1371_SRC_DATA(d) ((d) & E1371_SRC_DATAMASK) 160 #define E1371_SRC_CTLMASK (E1371_SRC_DISABLE | E1371_SRC_DISP1 | \ 161 E1371_SRC_DISP2 | E1371_SRC_DISREC) 162 #define E1371_SRC_STATE_MASK 0x00870000 163 #define E1371_SRC_STATE_OK 0x00010000 164 165 #define E1371_LEGACY 0x18 166 167 /* 168 * ES1371/ES1373 sample rate converter registers 169 */ 170 171 #define ESRC_ADC 0x78 172 #define ESRC_DAC1 0x70 173 #define ESRC_DAC2 0x74 174 #define ESRC_ADC_VOLL 0x6c 175 #define ESRC_ADC_VOLR 0x6d 176 #define ESRC_DAC1_VOLL 0x7c 177 #define ESRC_DAC1_VOLR 0x7d 178 #define ESRC_DAC2_VOLL 0x7e 179 #define ESRC_DAC2_VOLR 0x7f 180 #define ESRC_TRUNC_N 0x00 181 #define ESRC_IREGS 0x01 182 #define ESRC_ACF 0x02 183 #define ESRC_VFF 0x03 184 #define ESRC_SET_TRUNC(n) ((n)<<9) 185 #define ESRC_SET_N(n) ((n)<<4) 186 #define ESRC_SMF 0x8000 187 #define ESRC_SET_VFI(n) ((n)<<10) 188 #define ESRC_SET_ACI(n) (n) 189 #define ESRC_SET_ADC_VOL(n) ((n)<<8) 190 #define ESRC_SET_DAC_VOLI(n) ((n)<<12) 191 #define ESRC_SET_DAC_VOLF(n) (n) 192 #define SRC_MAGIC ((1<15)|(1<<13)|(1<<11)|(1<<9)) 193 194 #define EAP_SIC 0x20 195 #define EAP_P1_S_MB 0x00000001 196 #define EAP_P1_S_EB 0x00000002 197 #define EAP_P2_S_MB 0x00000004 198 #define EAP_P2_S_EB 0x00000008 199 #define EAP_R1_S_MB 0x00000010 200 #define EAP_R1_S_EB 0x00000020 201 #define EAP_P2_DAC_SEN 0x00000040 202 #define EAP_P1_SCT_RLD 0x00000080 203 #define EAP_P1_INTR_EN 0x00000100 204 #define EAP_P2_INTR_EN 0x00000200 205 #define EAP_R1_INTR_EN 0x00000400 206 #define EAP_P1_PAUSE 0x00000800 207 #define EAP_P2_PAUSE 0x00001000 208 #define EAP_P1_LOOP_SEL 0x00002000 209 #define EAP_P2_LOOP_SEL 0x00004000 210 #define EAP_R1_LOOP_SEL 0x00008000 211 #define EAP_S_EB(i) (EAP_P2_S_EB >> 2*(i)) 212 #define EAP_S_MB(i) (EAP_P2_S_MB >> 2*(i)) 213 #define EAP_P_INTR_EN(i) (EAP_P2_INTR_EN >> (i)) 214 #define EAP_SET_P2_ST_INC(i) ((i) << 16) 215 #define EAP_SET_P2_END_INC(i) ((i) << 19) 216 #define EAP_INC_BITS 0x003f0000 217 218 #define EAP_DAC1_CSR 0x24 219 #define EAP_DAC2_CSR 0x28 220 #define EAP_ADC_CSR 0x2c 221 #define EAP_GET_CURRSAMP(r) ((r) >> 16) 222 223 #define EAP_DAC_PAGE 0xc 224 #define EAP_ADC_PAGE 0xd 225 #define EAP_UART_PAGE1 0xe 226 #define EAP_UART_PAGE2 0xf 227 228 #define EAP_DAC1_ADDR 0x30 229 #define EAP_DAC1_SIZE 0x34 230 #define EAP_DAC2_ADDR 0x38 231 #define EAP_DAC2_SIZE 0x3c 232 #define EAP_ADC_ADDR 0x30 233 #define EAP_ADC_SIZE 0x34 234 #define EAP_SET_SIZE(c,s) (((c)<<16) | (s)) 235 236 #define EAP_READ_TIMEOUT 5000 237 #define EAP_WRITE_TIMEOUT 5000 238 239 240 #define EAP_XTAL_FREQ 1411200 /* 22.5792 / 16 MHz */ 241 242 /* AK4531 registers */ 243 #define AK_MASTER_L 0x00 244 #define AK_MASTER_R 0x01 245 #define AK_VOICE_L 0x02 246 #define AK_VOICE_R 0x03 247 #define AK_FM_L 0x04 248 #define AK_FM_R 0x05 249 #define AK_CD_L 0x06 250 #define AK_CD_R 0x07 251 #define AK_LINE_L 0x08 252 #define AK_LINE_R 0x09 253 #define AK_AUX_L 0x0a 254 #define AK_AUX_R 0x0b 255 #define AK_MONO1 0x0c 256 #define AK_MONO2 0x0d 257 #define AK_MIC 0x0e 258 #define AK_MONO 0x0f 259 #define AK_OUT_MIXER1 0x10 260 #define AK_M_FM_L 0x40 261 #define AK_M_FM_R 0x20 262 #define AK_M_LINE_L 0x10 263 #define AK_M_LINE_R 0x08 264 #define AK_M_CD_L 0x04 265 #define AK_M_CD_R 0x02 266 #define AK_M_MIC 0x01 267 #define AK_OUT_MIXER2 0x11 268 #define AK_M_AUX_L 0x20 269 #define AK_M_AUX_R 0x10 270 #define AK_M_VOICE_L 0x08 271 #define AK_M_VOICE_R 0x04 272 #define AK_M_MONO2 0x02 273 #define AK_M_MONO1 0x01 274 #define AK_IN_MIXER1_L 0x12 275 #define AK_IN_MIXER1_R 0x13 276 #define AK_IN_MIXER2_L 0x14 277 #define AK_IN_MIXER2_R 0x15 278 #define AK_M_TMIC 0x80 279 #define AK_M_TMONO1 0x40 280 #define AK_M_TMONO2 0x20 281 #define AK_M2_AUX_L 0x10 282 #define AK_M2_AUX_R 0x08 283 #define AK_M_VOICE 0x04 284 #define AK_M2_MONO2 0x02 285 #define AK_M2_MONO1 0x01 286 #define AK_RESET 0x16 287 #define AK_PD 0x02 288 #define AK_NRST 0x01 289 #define AK_CS 0x17 290 #define AK_ADSEL 0x18 291 #define AK_MGAIN 0x19 292 #define AK_NPORTS 0x20 293 294 /* Not sensical for AC97? */ 295 #define VOL_TO_ATT5(v) (0x1f - ((v) >> 3)) 296 #define VOL_TO_GAIN5(v) VOL_TO_ATT5(v) 297 #define ATT5_TO_VOL(v) ((0x1f - (v)) << 3) 298 #define GAIN5_TO_VOL(v) ATT5_TO_VOL(v) 299 #define VOL_0DB 200 300 301 /* Futzable parms */ 302 #define EAP_MASTER_VOL 0 303 #define EAP_VOICE_VOL 1 304 #define EAP_FM_VOL 2 305 #define EAP_VIDEO_VOL 2 /* ES1371 */ 306 #define EAP_CD_VOL 3 307 #define EAP_LINE_VOL 4 308 #define EAP_AUX_VOL 5 309 #define EAP_MIC_VOL 6 310 #define EAP_RECORD_SOURCE 7 311 #define EAP_INPUT_SOURCE 8 312 #define EAP_MIC_PREAMP 9 313 #define EAP_OUTPUT_CLASS 10 314 #define EAP_RECORD_CLASS 11 315 #define EAP_INPUT_CLASS 12 316 317 #define MIDI_BUSY_WAIT 100 318 #define MIDI_BUSY_DELAY 100 /* Delay when UART is busy */ 319 320 #define EAP_EV1938_A 0x00 321 #define EAP_CT5880_C 0x02 322 #define EAP_CT5880_D 0x03 323 #define EAP_CT5880_E 0x04 324 #define EAP_ES1373_A 0x04 325 #define EAP_ES1373_B 0x06 326 #define EAP_CT5880_A 0x07 327 #define EAP_ES1373_8 0x08 328 #define EAP_ES1371_B 0x09 329
Indexes created Sun Sep 28 12:09:53 GMT 2025