ehci_pci.c revision 1.37 1 1.37 drochner /* $NetBSD: ehci_pci.c,v 1.37 2008/03/28 17:14:45 drochner Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.8 augustss * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.1 augustss * by Lennart Augustsson (lennart (at) augustsson.net).
9 1.1 augustss *
10 1.1 augustss * Redistribution and use in source and binary forms, with or without
11 1.1 augustss * modification, are permitted provided that the following conditions
12 1.1 augustss * are met:
13 1.1 augustss * 1. Redistributions of source code must retain the above copyright
14 1.1 augustss * notice, this list of conditions and the following disclaimer.
15 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer in the
17 1.1 augustss * documentation and/or other materials provided with the distribution.
18 1.1 augustss * 3. All advertising materials mentioning features or use of this software
19 1.1 augustss * must display the following acknowledgement:
20 1.1 augustss * This product includes software developed by the NetBSD
21 1.1 augustss * Foundation, Inc. and its contributors.
22 1.1 augustss * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 augustss * contributors may be used to endorse or promote products derived
24 1.1 augustss * from this software without specific prior written permission.
25 1.1 augustss *
26 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
37 1.1 augustss */
38 1.6 lukem
39 1.6 lukem #include <sys/cdefs.h>
40 1.37 drochner __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.37 2008/03/28 17:14:45 drochner Exp $");
41 1.1 augustss
42 1.1 augustss #include <sys/param.h>
43 1.1 augustss #include <sys/systm.h>
44 1.1 augustss #include <sys/kernel.h>
45 1.1 augustss #include <sys/device.h>
46 1.1 augustss #include <sys/proc.h>
47 1.1 augustss #include <sys/queue.h>
48 1.1 augustss
49 1.31 ad #include <sys/bus.h>
50 1.1 augustss
51 1.22 xtraeme #include <dev/pci/pcidevs.h>
52 1.1 augustss #include <dev/pci/pcivar.h>
53 1.4 augustss #include <dev/pci/usb_pci.h>
54 1.1 augustss
55 1.1 augustss #include <dev/usb/usb.h>
56 1.1 augustss #include <dev/usb/usbdi.h>
57 1.1 augustss #include <dev/usb/usbdivar.h>
58 1.1 augustss #include <dev/usb/usb_mem.h>
59 1.1 augustss
60 1.1 augustss #include <dev/usb/ehcireg.h>
61 1.1 augustss #include <dev/usb/ehcivar.h>
62 1.1 augustss
63 1.5 augustss #ifdef EHCI_DEBUG
64 1.5 augustss #define DPRINTF(x) if (ehcidebug) printf x
65 1.5 augustss extern int ehcidebug;
66 1.5 augustss #else
67 1.5 augustss #define DPRINTF(x)
68 1.5 augustss #endif
69 1.5 augustss
70 1.34 jmcneill static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc,
71 1.34 jmcneill pcitag_t tag);
72 1.19 augustss static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc,
73 1.19 augustss pcitag_t tag);
74 1.35 dyoung static bool ehci_pci_suspend(device_t PMF_FN_PROTO);
75 1.35 dyoung static bool ehci_pci_resume(device_t PMF_FN_PROTO);
76 1.19 augustss
77 1.1 augustss struct ehci_pci_softc {
78 1.1 augustss ehci_softc_t sc;
79 1.1 augustss pci_chipset_tag_t sc_pc;
80 1.1 augustss pcitag_t sc_tag;
81 1.1 augustss void *sc_ih; /* interrupt vectoring */
82 1.1 augustss };
83 1.1 augustss
84 1.19 augustss #define EHCI_MAX_BIOS_WAIT 1000 /* ms */
85 1.19 augustss
86 1.18 thorpej static int
87 1.26 christos ehci_pci_match(struct device *parent, struct cfdata *match,
88 1.25 christos void *aux)
89 1.1 augustss {
90 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *) aux;
91 1.1 augustss
92 1.1 augustss if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
93 1.1 augustss PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
94 1.1 augustss PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI)
95 1.1 augustss return (1);
96 1.17 perry
97 1.1 augustss return (0);
98 1.1 augustss }
99 1.1 augustss
100 1.18 thorpej static void
101 1.26 christos ehci_pci_attach(struct device *parent, struct device *self, void *aux)
102 1.1 augustss {
103 1.37 drochner struct ehci_pci_softc *sc = device_private(self);
104 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *)aux;
105 1.1 augustss pci_chipset_tag_t pc = pa->pa_pc;
106 1.1 augustss pcitag_t tag = pa->pa_tag;
107 1.1 augustss char const *intrstr;
108 1.1 augustss pci_intr_handle_t ih;
109 1.1 augustss pcireg_t csr;
110 1.16 mycroft const char *vendor;
111 1.37 drochner const char *devname = device_xname(self);
112 1.1 augustss char devinfo[256];
113 1.1 augustss usbd_status r;
114 1.5 augustss int ncomp;
115 1.5 augustss struct usb_pci *up;
116 1.1 augustss
117 1.37 drochner sc->sc.sc_dev = self;
118 1.37 drochner sc->sc.sc_bus.hci_private = sc;
119 1.37 drochner
120 1.13 thorpej aprint_naive(": USB controller\n");
121 1.13 thorpej
122 1.15 itojun pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
123 1.13 thorpej aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
124 1.13 thorpej PCI_REVISION(pa->pa_class));
125 1.1 augustss
126 1.1 augustss /* Map I/O registers */
127 1.1 augustss if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
128 1.1 augustss &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
129 1.13 thorpej aprint_error("%s: can't map memory space\n", devname);
130 1.1 augustss return;
131 1.1 augustss }
132 1.1 augustss
133 1.1 augustss sc->sc_pc = pc;
134 1.1 augustss sc->sc_tag = tag;
135 1.1 augustss sc->sc.sc_bus.dmatag = pa->pa_dmat;
136 1.1 augustss
137 1.1 augustss /* Enable the device. */
138 1.1 augustss csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
139 1.1 augustss pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
140 1.1 augustss csr | PCI_COMMAND_MASTER_ENABLE);
141 1.1 augustss
142 1.4 augustss /* Disable interrupts, so we don't get any spurious ones. */
143 1.5 augustss sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
144 1.5 augustss DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs));
145 1.4 augustss EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
146 1.4 augustss
147 1.1 augustss /* Map and establish the interrupt. */
148 1.3 sommerfe if (pci_intr_map(pa, &ih)) {
149 1.13 thorpej aprint_error("%s: couldn't map interrupt\n", devname);
150 1.1 augustss return;
151 1.1 augustss }
152 1.1 augustss intrstr = pci_intr_string(pc, ih);
153 1.1 augustss sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc);
154 1.1 augustss if (sc->sc_ih == NULL) {
155 1.13 thorpej aprint_error("%s: couldn't establish interrupt", devname);
156 1.1 augustss if (intrstr != NULL)
157 1.13 thorpej aprint_normal(" at %s", intrstr);
158 1.13 thorpej aprint_normal("\n");
159 1.1 augustss return;
160 1.1 augustss }
161 1.13 thorpej aprint_normal("%s: interrupting at %s\n", devname, intrstr);
162 1.1 augustss
163 1.1 augustss switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) {
164 1.1 augustss case PCI_USBREV_PRE_1_0:
165 1.1 augustss case PCI_USBREV_1_0:
166 1.1 augustss case PCI_USBREV_1_1:
167 1.4 augustss sc->sc.sc_bus.usbrev = USBREV_UNKNOWN;
168 1.27 ad aprint_verbose("%s: pre-2.0 USB rev\n", devname);
169 1.4 augustss return;
170 1.1 augustss case PCI_USBREV_2_0:
171 1.1 augustss sc->sc.sc_bus.usbrev = USBREV_2_0;
172 1.1 augustss break;
173 1.1 augustss default:
174 1.1 augustss sc->sc.sc_bus.usbrev = USBREV_UNKNOWN;
175 1.1 augustss break;
176 1.1 augustss }
177 1.1 augustss
178 1.1 augustss /* Figure out vendor for root hub descriptor. */
179 1.1 augustss vendor = pci_findvendor(pa->pa_id);
180 1.1 augustss sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id);
181 1.1 augustss if (vendor)
182 1.14 itojun strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor));
183 1.1 augustss else
184 1.14 itojun snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
185 1.14 itojun "vendor 0x%04x", PCI_VENDOR(pa->pa_id));
186 1.17 perry
187 1.22 xtraeme /* Enable workaround for dropped interrupts as required */
188 1.30 tsutsui switch (sc->sc.sc_id_vendor) {
189 1.30 tsutsui case PCI_VENDOR_ATI:
190 1.30 tsutsui case PCI_VENDOR_VIATECH:
191 1.22 xtraeme sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND;
192 1.30 tsutsui aprint_normal("%s: dropped intr workaround enabled\n", devname);
193 1.30 tsutsui break;
194 1.30 tsutsui default:
195 1.30 tsutsui break;
196 1.30 tsutsui }
197 1.22 xtraeme
198 1.5 augustss /*
199 1.5 augustss * Find companion controllers. According to the spec they always
200 1.5 augustss * have lower function numbers so they should be enumerated already.
201 1.5 augustss */
202 1.5 augustss ncomp = 0;
203 1.5 augustss TAILQ_FOREACH(up, &ehci_pci_alldevs, next) {
204 1.5 augustss if (up->bus == pa->pa_bus && up->device == pa->pa_device) {
205 1.5 augustss DPRINTF(("ehci_pci_attach: companion %s\n",
206 1.37 drochner device_xname(up->usb)));
207 1.5 augustss sc->sc.sc_comps[ncomp++] = up->usb;
208 1.5 augustss if (ncomp >= EHCI_COMPANION_MAX)
209 1.5 augustss break;
210 1.5 augustss }
211 1.5 augustss }
212 1.5 augustss sc->sc.sc_ncomp = ncomp;
213 1.5 augustss
214 1.19 augustss ehci_get_ownership(&sc->sc, pc, tag);
215 1.19 augustss
216 1.1 augustss r = ehci_init(&sc->sc);
217 1.1 augustss if (r != USBD_NORMAL_COMPLETION) {
218 1.13 thorpej aprint_error("%s: init failed, error=%d\n", devname, r);
219 1.1 augustss return;
220 1.1 augustss }
221 1.1 augustss
222 1.36 dyoung if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume,
223 1.36 dyoung ehci_shutdown))
224 1.32 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
225 1.32 jmcneill
226 1.1 augustss /* Attach usb device. */
227 1.37 drochner sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
228 1.1 augustss }
229 1.1 augustss
230 1.18 thorpej static int
231 1.1 augustss ehci_pci_detach(device_ptr_t self, int flags)
232 1.1 augustss {
233 1.37 drochner struct ehci_pci_softc *sc = device_private(self);
234 1.1 augustss int rv;
235 1.1 augustss
236 1.32 jmcneill pmf_device_deregister(self);
237 1.1 augustss rv = ehci_detach(&sc->sc, flags);
238 1.1 augustss if (rv)
239 1.1 augustss return (rv);
240 1.1 augustss if (sc->sc_ih != NULL) {
241 1.1 augustss pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
242 1.1 augustss sc->sc_ih = NULL;
243 1.1 augustss }
244 1.1 augustss if (sc->sc.sc_size) {
245 1.34 jmcneill ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
246 1.1 augustss bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
247 1.1 augustss sc->sc.sc_size = 0;
248 1.1 augustss }
249 1.34 jmcneill
250 1.1 augustss return (0);
251 1.1 augustss }
252 1.18 thorpej
253 1.37 drochner CFATTACH_DECL2_NEW(ehci_pci, sizeof(struct ehci_pci_softc),
254 1.35 dyoung ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL,
255 1.35 dyoung ehci_childdet);
256 1.19 augustss
257 1.19 augustss #ifdef EHCI_DEBUG
258 1.19 augustss static void
259 1.19 augustss ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
260 1.19 augustss {
261 1.19 augustss u_int32_t cparams, legctlsts, addr, cap, id;
262 1.19 augustss int maxdump = 10;
263 1.19 augustss
264 1.19 augustss cparams = EREAD4(sc, EHCI_HCCPARAMS);
265 1.19 augustss addr = EHCI_HCC_EECP(cparams);
266 1.19 augustss while (addr != 0) {
267 1.19 augustss cap = pci_conf_read(pc, tag, addr);
268 1.19 augustss id = EHCI_CAP_GET_ID(cap);
269 1.19 augustss switch (id) {
270 1.19 augustss case EHCI_CAP_ID_LEGACY:
271 1.19 augustss legctlsts = pci_conf_read(pc, tag,
272 1.19 augustss addr + PCI_EHCI_USBLEGCTLSTS);
273 1.20 augustss printf("ehci_dump_caps: legsup=0x%08x "
274 1.20 augustss "legctlsts=0x%08x\n", cap, legctlsts);
275 1.19 augustss break;
276 1.19 augustss default:
277 1.20 augustss printf("ehci_dump_caps: cap=0x%08x\n", cap);
278 1.19 augustss break;
279 1.19 augustss }
280 1.19 augustss if (--maxdump < 0)
281 1.19 augustss break;
282 1.19 augustss addr = EHCI_CAP_GET_NEXT(cap);
283 1.19 augustss }
284 1.19 augustss }
285 1.19 augustss #endif
286 1.19 augustss
287 1.19 augustss static void
288 1.34 jmcneill ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
289 1.34 jmcneill {
290 1.37 drochner const char *devname = device_xname(sc->sc_dev);
291 1.34 jmcneill u_int32_t cparams, addr, cap;
292 1.34 jmcneill pcireg_t legsup;
293 1.34 jmcneill int maxcap = 10;
294 1.34 jmcneill
295 1.34 jmcneill cparams = EREAD4(sc, EHCI_HCCPARAMS);
296 1.34 jmcneill addr = EHCI_HCC_EECP(cparams);
297 1.34 jmcneill while (addr != 0) {
298 1.34 jmcneill cap = pci_conf_read(pc, tag, addr);
299 1.34 jmcneill if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
300 1.34 jmcneill goto next;
301 1.34 jmcneill legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
302 1.34 jmcneill pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
303 1.34 jmcneill legsup & ~EHCI_LEG_HC_OS_OWNED);
304 1.34 jmcneill
305 1.34 jmcneill next:
306 1.34 jmcneill if (--maxcap < 0) {
307 1.34 jmcneill aprint_normal("%s: broken extended capabilities "
308 1.34 jmcneill "ignored\n", devname);
309 1.34 jmcneill return;
310 1.34 jmcneill }
311 1.34 jmcneill addr = EHCI_CAP_GET_NEXT(cap);
312 1.34 jmcneill }
313 1.34 jmcneill }
314 1.34 jmcneill
315 1.34 jmcneill static void
316 1.19 augustss ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
317 1.19 augustss {
318 1.37 drochner const char *devname = device_xname(sc->sc_dev);
319 1.33 jmcneill u_int32_t cparams, addr, cap;
320 1.33 jmcneill pcireg_t legsup;
321 1.19 augustss int maxcap = 10;
322 1.19 augustss int ms;
323 1.19 augustss
324 1.19 augustss #ifdef EHCI_DEBUG
325 1.20 augustss if (ehcidebug)
326 1.20 augustss ehci_dump_caps(sc, pc, tag);
327 1.19 augustss #endif
328 1.19 augustss cparams = EREAD4(sc, EHCI_HCCPARAMS);
329 1.19 augustss addr = EHCI_HCC_EECP(cparams);
330 1.19 augustss while (addr != 0) {
331 1.19 augustss cap = pci_conf_read(pc, tag, addr);
332 1.34 jmcneill if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
333 1.34 jmcneill goto next;
334 1.34 jmcneill legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
335 1.34 jmcneill /* Ask BIOS to give up ownership */
336 1.34 jmcneill pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
337 1.34 jmcneill legsup | EHCI_LEG_HC_OS_OWNED);
338 1.34 jmcneill if (legsup & EHCI_LEG_HC_BIOS_OWNED) {
339 1.34 jmcneill for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) {
340 1.34 jmcneill legsup = pci_conf_read(pc, tag,
341 1.34 jmcneill addr + PCI_EHCI_USBLEGSUP);
342 1.34 jmcneill if (!(legsup & EHCI_LEG_HC_BIOS_OWNED))
343 1.34 jmcneill break;
344 1.34 jmcneill delay(1000);
345 1.34 jmcneill }
346 1.34 jmcneill if (ms == EHCI_MAX_BIOS_WAIT) {
347 1.34 jmcneill aprint_normal("%s: BIOS refuses to give up "
348 1.34 jmcneill "ownership, using force\n", devname);
349 1.34 jmcneill pci_conf_write(pc, tag,
350 1.34 jmcneill addr + PCI_EHCI_USBLEGSUP, 0);
351 1.34 jmcneill } else
352 1.34 jmcneill aprint_verbose("%s: BIOS has given up "
353 1.34 jmcneill "ownership\n", devname);
354 1.34 jmcneill }
355 1.34 jmcneill
356 1.34 jmcneill /* Disable SMIs */
357 1.34 jmcneill pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS,
358 1.34 jmcneill EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD |
359 1.34 jmcneill EHCI_LEG_EXT_SMI_OS_CHANGE);
360 1.34 jmcneill
361 1.34 jmcneill next:
362 1.21 augustss if (--maxcap < 0) {
363 1.21 augustss aprint_normal("%s: broken extended capabilities "
364 1.21 augustss "ignored\n", devname);
365 1.19 augustss return;
366 1.21 augustss }
367 1.19 augustss addr = EHCI_CAP_GET_NEXT(cap);
368 1.19 augustss }
369 1.19 augustss
370 1.34 jmcneill }
371 1.34 jmcneill
372 1.34 jmcneill static bool
373 1.35 dyoung ehci_pci_suspend(device_t dv PMF_FN_ARGS)
374 1.34 jmcneill {
375 1.34 jmcneill struct ehci_pci_softc *sc = device_private(dv);
376 1.28 jmcneill
377 1.35 dyoung ehci_suspend(dv PMF_FN_CALL);
378 1.34 jmcneill ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
379 1.33 jmcneill
380 1.34 jmcneill return true;
381 1.19 augustss }
382 1.23 jmcneill
383 1.32 jmcneill static bool
384 1.35 dyoung ehci_pci_resume(device_t dv PMF_FN_ARGS)
385 1.23 jmcneill {
386 1.32 jmcneill struct ehci_pci_softc *sc = device_private(dv);
387 1.23 jmcneill
388 1.32 jmcneill ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
389 1.35 dyoung return ehci_resume(dv PMF_FN_CALL);
390 1.23 jmcneill }
391