ehci_pci.c revision 1.38.16.1.2.1 1 1.38.16.1.2.1 matt /* $NetBSD: ehci_pci.c,v 1.38.16.1.2.1 2010/04/21 00:27:39 matt Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.8 augustss * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.1 augustss * by Lennart Augustsson (lennart (at) augustsson.net).
9 1.1 augustss *
10 1.1 augustss * Redistribution and use in source and binary forms, with or without
11 1.1 augustss * modification, are permitted provided that the following conditions
12 1.1 augustss * are met:
13 1.1 augustss * 1. Redistributions of source code must retain the above copyright
14 1.1 augustss * notice, this list of conditions and the following disclaimer.
15 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer in the
17 1.1 augustss * documentation and/or other materials provided with the distribution.
18 1.1 augustss *
19 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
30 1.1 augustss */
31 1.6 lukem
32 1.6 lukem #include <sys/cdefs.h>
33 1.38.16.1.2.1 matt __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.38.16.1.2.1 2010/04/21 00:27:39 matt Exp $");
34 1.1 augustss
35 1.1 augustss #include <sys/param.h>
36 1.1 augustss #include <sys/systm.h>
37 1.1 augustss #include <sys/kernel.h>
38 1.1 augustss #include <sys/device.h>
39 1.1 augustss #include <sys/proc.h>
40 1.1 augustss #include <sys/queue.h>
41 1.1 augustss
42 1.31 ad #include <sys/bus.h>
43 1.1 augustss
44 1.22 xtraeme #include <dev/pci/pcidevs.h>
45 1.1 augustss #include <dev/pci/pcivar.h>
46 1.4 augustss #include <dev/pci/usb_pci.h>
47 1.1 augustss
48 1.1 augustss #include <dev/usb/usb.h>
49 1.1 augustss #include <dev/usb/usbdi.h>
50 1.1 augustss #include <dev/usb/usbdivar.h>
51 1.1 augustss #include <dev/usb/usb_mem.h>
52 1.1 augustss
53 1.1 augustss #include <dev/usb/ehcireg.h>
54 1.1 augustss #include <dev/usb/ehcivar.h>
55 1.1 augustss
56 1.5 augustss #ifdef EHCI_DEBUG
57 1.5 augustss #define DPRINTF(x) if (ehcidebug) printf x
58 1.5 augustss extern int ehcidebug;
59 1.5 augustss #else
60 1.5 augustss #define DPRINTF(x)
61 1.5 augustss #endif
62 1.5 augustss
63 1.38.16.1 bouyer enum ehci_pci_quirk_flags {
64 1.38.16.1 bouyer EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */
65 1.38.16.1 bouyer EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */
66 1.38.16.1 bouyer };
67 1.38.16.1 bouyer
68 1.38.16.1 bouyer static const struct pci_quirkdata ehci_pci_quirks[] = {
69 1.38.16.1 bouyer { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI,
70 1.38.16.1 bouyer EHCI_PCI_QUIRK_AMD_SB600 },
71 1.38.16.1 bouyer { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI,
72 1.38.16.1 bouyer EHCI_PCI_QUIRK_AMD_SB700 },
73 1.38.16.1 bouyer };
74 1.38.16.1 bouyer
75 1.34 jmcneill static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc,
76 1.34 jmcneill pcitag_t tag);
77 1.19 augustss static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc,
78 1.19 augustss pcitag_t tag);
79 1.35 dyoung static bool ehci_pci_suspend(device_t PMF_FN_PROTO);
80 1.35 dyoung static bool ehci_pci_resume(device_t PMF_FN_PROTO);
81 1.19 augustss
82 1.1 augustss struct ehci_pci_softc {
83 1.1 augustss ehci_softc_t sc;
84 1.1 augustss pci_chipset_tag_t sc_pc;
85 1.1 augustss pcitag_t sc_tag;
86 1.1 augustss void *sc_ih; /* interrupt vectoring */
87 1.1 augustss };
88 1.1 augustss
89 1.38.16.1 bouyer static int ehci_sb700_match(struct pci_attach_args *pa);
90 1.38.16.1 bouyer static int ehci_apply_amd_quirks(struct ehci_pci_softc *sc);
91 1.38.16.1 bouyer enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t,
92 1.38.16.1 bouyer pci_product_id_t);
93 1.38.16.1 bouyer
94 1.19 augustss #define EHCI_MAX_BIOS_WAIT 1000 /* ms */
95 1.38.16.1 bouyer #define EHCI_SBx00_WORKAROUND_REG 0x50
96 1.38.16.1 bouyer #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27)
97 1.38.16.1 bouyer
98 1.19 augustss
99 1.18 thorpej static int
100 1.26 christos ehci_pci_match(struct device *parent, struct cfdata *match,
101 1.25 christos void *aux)
102 1.1 augustss {
103 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *) aux;
104 1.1 augustss
105 1.1 augustss if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
106 1.1 augustss PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
107 1.1 augustss PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI)
108 1.1 augustss return (1);
109 1.17 perry
110 1.1 augustss return (0);
111 1.1 augustss }
112 1.1 augustss
113 1.18 thorpej static void
114 1.26 christos ehci_pci_attach(struct device *parent, struct device *self, void *aux)
115 1.1 augustss {
116 1.37 drochner struct ehci_pci_softc *sc = device_private(self);
117 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *)aux;
118 1.1 augustss pci_chipset_tag_t pc = pa->pa_pc;
119 1.1 augustss pcitag_t tag = pa->pa_tag;
120 1.1 augustss char const *intrstr;
121 1.1 augustss pci_intr_handle_t ih;
122 1.1 augustss pcireg_t csr;
123 1.16 mycroft const char *vendor;
124 1.37 drochner const char *devname = device_xname(self);
125 1.1 augustss char devinfo[256];
126 1.1 augustss usbd_status r;
127 1.5 augustss int ncomp;
128 1.5 augustss struct usb_pci *up;
129 1.38.16.1 bouyer int quirk;
130 1.1 augustss
131 1.37 drochner sc->sc.sc_dev = self;
132 1.37 drochner sc->sc.sc_bus.hci_private = sc;
133 1.37 drochner
134 1.13 thorpej aprint_naive(": USB controller\n");
135 1.13 thorpej
136 1.15 itojun pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
137 1.13 thorpej aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
138 1.13 thorpej PCI_REVISION(pa->pa_class));
139 1.1 augustss
140 1.38.16.1 bouyer /* Check for quirks */
141 1.38.16.1 bouyer quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
142 1.38.16.1 bouyer PCI_PRODUCT(pa->pa_id));
143 1.38.16.1 bouyer
144 1.1 augustss /* Map I/O registers */
145 1.1 augustss if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
146 1.1 augustss &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
147 1.13 thorpej aprint_error("%s: can't map memory space\n", devname);
148 1.1 augustss return;
149 1.1 augustss }
150 1.1 augustss
151 1.1 augustss sc->sc_pc = pc;
152 1.1 augustss sc->sc_tag = tag;
153 1.1 augustss sc->sc.sc_bus.dmatag = pa->pa_dmat;
154 1.1 augustss
155 1.38.16.1 bouyer /* Handle quirks */
156 1.38.16.1 bouyer switch (quirk) {
157 1.38.16.1 bouyer case EHCI_PCI_QUIRK_AMD_SB600:
158 1.38.16.1 bouyer ehci_apply_amd_quirks(sc);
159 1.38.16.1 bouyer break;
160 1.38.16.1 bouyer case EHCI_PCI_QUIRK_AMD_SB700:
161 1.38.16.1 bouyer if (pci_find_device(NULL, ehci_sb700_match))
162 1.38.16.1 bouyer ehci_apply_amd_quirks(sc);
163 1.38.16.1 bouyer break;
164 1.38.16.1 bouyer }
165 1.38.16.1 bouyer
166 1.1 augustss /* Enable the device. */
167 1.1 augustss csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
168 1.1 augustss pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
169 1.1 augustss csr | PCI_COMMAND_MASTER_ENABLE);
170 1.1 augustss
171 1.4 augustss /* Disable interrupts, so we don't get any spurious ones. */
172 1.5 augustss sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
173 1.5 augustss DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs));
174 1.4 augustss EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
175 1.4 augustss
176 1.1 augustss /* Map and establish the interrupt. */
177 1.3 sommerfe if (pci_intr_map(pa, &ih)) {
178 1.13 thorpej aprint_error("%s: couldn't map interrupt\n", devname);
179 1.1 augustss return;
180 1.1 augustss }
181 1.1 augustss intrstr = pci_intr_string(pc, ih);
182 1.1 augustss sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc);
183 1.1 augustss if (sc->sc_ih == NULL) {
184 1.13 thorpej aprint_error("%s: couldn't establish interrupt", devname);
185 1.1 augustss if (intrstr != NULL)
186 1.13 thorpej aprint_normal(" at %s", intrstr);
187 1.13 thorpej aprint_normal("\n");
188 1.1 augustss return;
189 1.1 augustss }
190 1.13 thorpej aprint_normal("%s: interrupting at %s\n", devname, intrstr);
191 1.1 augustss
192 1.1 augustss switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) {
193 1.1 augustss case PCI_USBREV_PRE_1_0:
194 1.1 augustss case PCI_USBREV_1_0:
195 1.1 augustss case PCI_USBREV_1_1:
196 1.4 augustss sc->sc.sc_bus.usbrev = USBREV_UNKNOWN;
197 1.27 ad aprint_verbose("%s: pre-2.0 USB rev\n", devname);
198 1.4 augustss return;
199 1.1 augustss case PCI_USBREV_2_0:
200 1.1 augustss sc->sc.sc_bus.usbrev = USBREV_2_0;
201 1.1 augustss break;
202 1.1 augustss default:
203 1.1 augustss sc->sc.sc_bus.usbrev = USBREV_UNKNOWN;
204 1.1 augustss break;
205 1.1 augustss }
206 1.1 augustss
207 1.1 augustss /* Figure out vendor for root hub descriptor. */
208 1.1 augustss vendor = pci_findvendor(pa->pa_id);
209 1.1 augustss sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id);
210 1.1 augustss if (vendor)
211 1.14 itojun strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor));
212 1.1 augustss else
213 1.14 itojun snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
214 1.14 itojun "vendor 0x%04x", PCI_VENDOR(pa->pa_id));
215 1.17 perry
216 1.22 xtraeme /* Enable workaround for dropped interrupts as required */
217 1.30 tsutsui switch (sc->sc.sc_id_vendor) {
218 1.30 tsutsui case PCI_VENDOR_ATI:
219 1.30 tsutsui case PCI_VENDOR_VIATECH:
220 1.22 xtraeme sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND;
221 1.30 tsutsui aprint_normal("%s: dropped intr workaround enabled\n", devname);
222 1.30 tsutsui break;
223 1.30 tsutsui default:
224 1.30 tsutsui break;
225 1.30 tsutsui }
226 1.22 xtraeme
227 1.5 augustss /*
228 1.5 augustss * Find companion controllers. According to the spec they always
229 1.5 augustss * have lower function numbers so they should be enumerated already.
230 1.5 augustss */
231 1.5 augustss ncomp = 0;
232 1.5 augustss TAILQ_FOREACH(up, &ehci_pci_alldevs, next) {
233 1.5 augustss if (up->bus == pa->pa_bus && up->device == pa->pa_device) {
234 1.5 augustss DPRINTF(("ehci_pci_attach: companion %s\n",
235 1.37 drochner device_xname(up->usb)));
236 1.5 augustss sc->sc.sc_comps[ncomp++] = up->usb;
237 1.5 augustss if (ncomp >= EHCI_COMPANION_MAX)
238 1.5 augustss break;
239 1.5 augustss }
240 1.5 augustss }
241 1.5 augustss sc->sc.sc_ncomp = ncomp;
242 1.5 augustss
243 1.19 augustss ehci_get_ownership(&sc->sc, pc, tag);
244 1.19 augustss
245 1.1 augustss r = ehci_init(&sc->sc);
246 1.1 augustss if (r != USBD_NORMAL_COMPLETION) {
247 1.13 thorpej aprint_error("%s: init failed, error=%d\n", devname, r);
248 1.1 augustss return;
249 1.1 augustss }
250 1.1 augustss
251 1.36 dyoung if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume,
252 1.36 dyoung ehci_shutdown))
253 1.32 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
254 1.32 jmcneill
255 1.1 augustss /* Attach usb device. */
256 1.37 drochner sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
257 1.1 augustss }
258 1.1 augustss
259 1.18 thorpej static int
260 1.1 augustss ehci_pci_detach(device_ptr_t self, int flags)
261 1.1 augustss {
262 1.37 drochner struct ehci_pci_softc *sc = device_private(self);
263 1.1 augustss int rv;
264 1.1 augustss
265 1.32 jmcneill pmf_device_deregister(self);
266 1.1 augustss rv = ehci_detach(&sc->sc, flags);
267 1.1 augustss if (rv)
268 1.1 augustss return (rv);
269 1.1 augustss if (sc->sc_ih != NULL) {
270 1.1 augustss pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
271 1.1 augustss sc->sc_ih = NULL;
272 1.1 augustss }
273 1.1 augustss if (sc->sc.sc_size) {
274 1.34 jmcneill ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
275 1.1 augustss bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
276 1.1 augustss sc->sc.sc_size = 0;
277 1.1 augustss }
278 1.34 jmcneill
279 1.1 augustss return (0);
280 1.1 augustss }
281 1.18 thorpej
282 1.37 drochner CFATTACH_DECL2_NEW(ehci_pci, sizeof(struct ehci_pci_softc),
283 1.35 dyoung ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL,
284 1.35 dyoung ehci_childdet);
285 1.19 augustss
286 1.19 augustss #ifdef EHCI_DEBUG
287 1.19 augustss static void
288 1.19 augustss ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
289 1.19 augustss {
290 1.19 augustss u_int32_t cparams, legctlsts, addr, cap, id;
291 1.19 augustss int maxdump = 10;
292 1.19 augustss
293 1.19 augustss cparams = EREAD4(sc, EHCI_HCCPARAMS);
294 1.19 augustss addr = EHCI_HCC_EECP(cparams);
295 1.19 augustss while (addr != 0) {
296 1.19 augustss cap = pci_conf_read(pc, tag, addr);
297 1.19 augustss id = EHCI_CAP_GET_ID(cap);
298 1.19 augustss switch (id) {
299 1.19 augustss case EHCI_CAP_ID_LEGACY:
300 1.19 augustss legctlsts = pci_conf_read(pc, tag,
301 1.19 augustss addr + PCI_EHCI_USBLEGCTLSTS);
302 1.20 augustss printf("ehci_dump_caps: legsup=0x%08x "
303 1.20 augustss "legctlsts=0x%08x\n", cap, legctlsts);
304 1.19 augustss break;
305 1.19 augustss default:
306 1.20 augustss printf("ehci_dump_caps: cap=0x%08x\n", cap);
307 1.19 augustss break;
308 1.19 augustss }
309 1.19 augustss if (--maxdump < 0)
310 1.19 augustss break;
311 1.19 augustss addr = EHCI_CAP_GET_NEXT(cap);
312 1.19 augustss }
313 1.19 augustss }
314 1.19 augustss #endif
315 1.19 augustss
316 1.19 augustss static void
317 1.34 jmcneill ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
318 1.34 jmcneill {
319 1.37 drochner const char *devname = device_xname(sc->sc_dev);
320 1.34 jmcneill u_int32_t cparams, addr, cap;
321 1.34 jmcneill pcireg_t legsup;
322 1.34 jmcneill int maxcap = 10;
323 1.34 jmcneill
324 1.34 jmcneill cparams = EREAD4(sc, EHCI_HCCPARAMS);
325 1.34 jmcneill addr = EHCI_HCC_EECP(cparams);
326 1.34 jmcneill while (addr != 0) {
327 1.34 jmcneill cap = pci_conf_read(pc, tag, addr);
328 1.34 jmcneill if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
329 1.34 jmcneill goto next;
330 1.34 jmcneill legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
331 1.34 jmcneill pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
332 1.34 jmcneill legsup & ~EHCI_LEG_HC_OS_OWNED);
333 1.34 jmcneill
334 1.34 jmcneill next:
335 1.34 jmcneill if (--maxcap < 0) {
336 1.34 jmcneill aprint_normal("%s: broken extended capabilities "
337 1.34 jmcneill "ignored\n", devname);
338 1.34 jmcneill return;
339 1.34 jmcneill }
340 1.34 jmcneill addr = EHCI_CAP_GET_NEXT(cap);
341 1.34 jmcneill }
342 1.34 jmcneill }
343 1.34 jmcneill
344 1.34 jmcneill static void
345 1.19 augustss ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
346 1.19 augustss {
347 1.37 drochner const char *devname = device_xname(sc->sc_dev);
348 1.33 jmcneill u_int32_t cparams, addr, cap;
349 1.33 jmcneill pcireg_t legsup;
350 1.19 augustss int maxcap = 10;
351 1.19 augustss int ms;
352 1.19 augustss
353 1.19 augustss #ifdef EHCI_DEBUG
354 1.20 augustss if (ehcidebug)
355 1.20 augustss ehci_dump_caps(sc, pc, tag);
356 1.19 augustss #endif
357 1.19 augustss cparams = EREAD4(sc, EHCI_HCCPARAMS);
358 1.19 augustss addr = EHCI_HCC_EECP(cparams);
359 1.19 augustss while (addr != 0) {
360 1.19 augustss cap = pci_conf_read(pc, tag, addr);
361 1.34 jmcneill if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
362 1.34 jmcneill goto next;
363 1.34 jmcneill legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
364 1.34 jmcneill /* Ask BIOS to give up ownership */
365 1.34 jmcneill pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
366 1.34 jmcneill legsup | EHCI_LEG_HC_OS_OWNED);
367 1.34 jmcneill if (legsup & EHCI_LEG_HC_BIOS_OWNED) {
368 1.34 jmcneill for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) {
369 1.34 jmcneill legsup = pci_conf_read(pc, tag,
370 1.34 jmcneill addr + PCI_EHCI_USBLEGSUP);
371 1.34 jmcneill if (!(legsup & EHCI_LEG_HC_BIOS_OWNED))
372 1.34 jmcneill break;
373 1.34 jmcneill delay(1000);
374 1.34 jmcneill }
375 1.34 jmcneill if (ms == EHCI_MAX_BIOS_WAIT) {
376 1.34 jmcneill aprint_normal("%s: BIOS refuses to give up "
377 1.34 jmcneill "ownership, using force\n", devname);
378 1.34 jmcneill pci_conf_write(pc, tag,
379 1.34 jmcneill addr + PCI_EHCI_USBLEGSUP, 0);
380 1.34 jmcneill } else
381 1.34 jmcneill aprint_verbose("%s: BIOS has given up "
382 1.34 jmcneill "ownership\n", devname);
383 1.34 jmcneill }
384 1.34 jmcneill
385 1.34 jmcneill /* Disable SMIs */
386 1.34 jmcneill pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS,
387 1.34 jmcneill EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD |
388 1.34 jmcneill EHCI_LEG_EXT_SMI_OS_CHANGE);
389 1.34 jmcneill
390 1.34 jmcneill next:
391 1.21 augustss if (--maxcap < 0) {
392 1.21 augustss aprint_normal("%s: broken extended capabilities "
393 1.21 augustss "ignored\n", devname);
394 1.19 augustss return;
395 1.21 augustss }
396 1.19 augustss addr = EHCI_CAP_GET_NEXT(cap);
397 1.19 augustss }
398 1.19 augustss
399 1.34 jmcneill }
400 1.34 jmcneill
401 1.34 jmcneill static bool
402 1.35 dyoung ehci_pci_suspend(device_t dv PMF_FN_ARGS)
403 1.34 jmcneill {
404 1.34 jmcneill struct ehci_pci_softc *sc = device_private(dv);
405 1.28 jmcneill
406 1.35 dyoung ehci_suspend(dv PMF_FN_CALL);
407 1.34 jmcneill ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
408 1.33 jmcneill
409 1.34 jmcneill return true;
410 1.19 augustss }
411 1.23 jmcneill
412 1.32 jmcneill static bool
413 1.35 dyoung ehci_pci_resume(device_t dv PMF_FN_ARGS)
414 1.23 jmcneill {
415 1.32 jmcneill struct ehci_pci_softc *sc = device_private(dv);
416 1.23 jmcneill
417 1.32 jmcneill ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
418 1.35 dyoung return ehci_resume(dv PMF_FN_CALL);
419 1.23 jmcneill }
420 1.38.16.1 bouyer
421 1.38.16.1 bouyer static int
422 1.38.16.1 bouyer ehci_sb700_match(struct pci_attach_args *pa)
423 1.38.16.1 bouyer {
424 1.38.16.1 bouyer if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
425 1.38.16.1 bouyer PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB))
426 1.38.16.1 bouyer return 0;
427 1.38.16.1 bouyer
428 1.38.16.1 bouyer switch (PCI_REVISION(pa->pa_class)) {
429 1.38.16.1 bouyer case 0x3a:
430 1.38.16.1 bouyer case 0x3b:
431 1.38.16.1 bouyer return 1;
432 1.38.16.1 bouyer }
433 1.38.16.1 bouyer
434 1.38.16.1 bouyer return 0;
435 1.38.16.1 bouyer }
436 1.38.16.1 bouyer
437 1.38.16.1 bouyer static int
438 1.38.16.1 bouyer ehci_apply_amd_quirks(struct ehci_pci_softc *sc)
439 1.38.16.1 bouyer {
440 1.38.16.1 bouyer pcireg_t value;
441 1.38.16.1 bouyer
442 1.38.16.1 bouyer aprint_normal_dev(sc->sc.sc_dev,
443 1.38.16.1 bouyer "applying AMD SB600/SB700 USB freeze workaround\n");
444 1.38.16.1 bouyer value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG);
445 1.38.16.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG,
446 1.38.16.1 bouyer value | EHCI_SBx00_WORKAROUND_ENABLE);
447 1.38.16.1 bouyer
448 1.38.16.1 bouyer return 0;
449 1.38.16.1 bouyer }
450 1.38.16.1 bouyer
451 1.38.16.1 bouyer enum ehci_pci_quirk_flags
452 1.38.16.1 bouyer ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product)
453 1.38.16.1 bouyer {
454 1.38.16.1 bouyer int i;
455 1.38.16.1 bouyer
456 1.38.16.1 bouyer for (i = 0; i < __arraycount(ehci_pci_quirks); i++) {
457 1.38.16.1 bouyer if (vendor == ehci_pci_quirks[i].vendor &&
458 1.38.16.1 bouyer product == ehci_pci_quirks[i].product)
459 1.38.16.1 bouyer return ehci_pci_quirks[i].quirks;
460 1.38.16.1 bouyer }
461 1.38.16.1 bouyer return 0;
462 1.38.16.1 bouyer }
463 1.38.16.1 bouyer
464